diff options
Diffstat (limited to 'opcodes/i386-reg.tbl')
| -rw-r--r-- | opcodes/i386-reg.tbl | 208 |
1 files changed, 104 insertions, 104 deletions
diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl index 5d6dc53..fb2330e 100644 --- a/opcodes/i386-reg.tbl +++ b/opcodes/i386-reg.tbl @@ -172,112 +172,112 @@ tr5, Class=RegTR, 0, 5, Dw2Inval, Dw2Inval tr6, Class=RegTR, 0, 6, Dw2Inval, Dw2Inval tr7, Class=RegTR, 0, 7, Dw2Inval, Dw2Inval // MMX and simd registers. -mm0, RegMMX, 0, 0, 29, 41 -mm1, RegMMX, 0, 1, 30, 42 -mm2, RegMMX, 0, 2, 31, 43 -mm3, RegMMX, 0, 3, 32, 44 -mm4, RegMMX, 0, 4, 33, 45 -mm5, RegMMX, 0, 5, 34, 46 -mm6, RegMMX, 0, 6, 35, 47 -mm7, RegMMX, 0, 7, 36, 48 -xmm0, RegSIMD|Acc|Xmmword, 0, 0, 21, 17 -xmm1, RegSIMD|Xmmword, 0, 1, 22, 18 -xmm2, RegSIMD|Xmmword, 0, 2, 23, 19 -xmm3, RegSIMD|Xmmword, 0, 3, 24, 20 -xmm4, RegSIMD|Xmmword, 0, 4, 25, 21 -xmm5, RegSIMD|Xmmword, 0, 5, 26, 22 -xmm6, RegSIMD|Xmmword, 0, 6, 27, 23 -xmm7, RegSIMD|Xmmword, 0, 7, 28, 24 -xmm8, RegSIMD|Xmmword, RegRex, 0, Dw2Inval, 25 -xmm9, RegSIMD|Xmmword, RegRex, 1, Dw2Inval, 26 -xmm10, RegSIMD|Xmmword, RegRex, 2, Dw2Inval, 27 -xmm11, RegSIMD|Xmmword, RegRex, 3, Dw2Inval, 28 -xmm12, RegSIMD|Xmmword, RegRex, 4, Dw2Inval, 29 -xmm13, RegSIMD|Xmmword, RegRex, 5, Dw2Inval, 30 -xmm14, RegSIMD|Xmmword, RegRex, 6, Dw2Inval, 31 -xmm15, RegSIMD|Xmmword, RegRex, 7, Dw2Inval, 32 -xmm16, RegSIMD|Xmmword, RegVRex, 0, Dw2Inval, 67 -xmm17, RegSIMD|Xmmword, RegVRex, 1, Dw2Inval, 68 -xmm18, RegSIMD|Xmmword, RegVRex, 2, Dw2Inval, 69 -xmm19, RegSIMD|Xmmword, RegVRex, 3, Dw2Inval, 70 -xmm20, RegSIMD|Xmmword, RegVRex, 4, Dw2Inval, 71 -xmm21, RegSIMD|Xmmword, RegVRex, 5, Dw2Inval, 72 -xmm22, RegSIMD|Xmmword, RegVRex, 6, Dw2Inval, 73 -xmm23, RegSIMD|Xmmword, RegVRex, 7, Dw2Inval, 74 -xmm24, RegSIMD|Xmmword, RegVRex|RegRex, 0, Dw2Inval, 75 -xmm25, RegSIMD|Xmmword, RegVRex|RegRex, 1, Dw2Inval, 76 -xmm26, RegSIMD|Xmmword, RegVRex|RegRex, 2, Dw2Inval, 77 -xmm27, RegSIMD|Xmmword, RegVRex|RegRex, 3, Dw2Inval, 78 -xmm28, RegSIMD|Xmmword, RegVRex|RegRex, 4, Dw2Inval, 79 -xmm29, RegSIMD|Xmmword, RegVRex|RegRex, 5, Dw2Inval, 80 -xmm30, RegSIMD|Xmmword, RegVRex|RegRex, 6, Dw2Inval, 81 -xmm31, RegSIMD|Xmmword, RegVRex|RegRex, 7, Dw2Inval, 82 +mm0, Class=RegMMX, 0, 0, 29, 41 +mm1, Class=RegMMX, 0, 1, 30, 42 +mm2, Class=RegMMX, 0, 2, 31, 43 +mm3, Class=RegMMX, 0, 3, 32, 44 +mm4, Class=RegMMX, 0, 4, 33, 45 +mm5, Class=RegMMX, 0, 5, 34, 46 +mm6, Class=RegMMX, 0, 6, 35, 47 +mm7, Class=RegMMX, 0, 7, 36, 48 +xmm0, Class=RegSIMD|Acc|Xmmword, 0, 0, 21, 17 +xmm1, Class=RegSIMD|Xmmword, 0, 1, 22, 18 +xmm2, Class=RegSIMD|Xmmword, 0, 2, 23, 19 +xmm3, Class=RegSIMD|Xmmword, 0, 3, 24, 20 +xmm4, Class=RegSIMD|Xmmword, 0, 4, 25, 21 +xmm5, Class=RegSIMD|Xmmword, 0, 5, 26, 22 +xmm6, Class=RegSIMD|Xmmword, 0, 6, 27, 23 +xmm7, Class=RegSIMD|Xmmword, 0, 7, 28, 24 +xmm8, Class=RegSIMD|Xmmword, RegRex, 0, Dw2Inval, 25 +xmm9, Class=RegSIMD|Xmmword, RegRex, 1, Dw2Inval, 26 +xmm10, Class=RegSIMD|Xmmword, RegRex, 2, Dw2Inval, 27 +xmm11, Class=RegSIMD|Xmmword, RegRex, 3, Dw2Inval, 28 +xmm12, Class=RegSIMD|Xmmword, RegRex, 4, Dw2Inval, 29 +xmm13, Class=RegSIMD|Xmmword, RegRex, 5, Dw2Inval, 30 +xmm14, Class=RegSIMD|Xmmword, RegRex, 6, Dw2Inval, 31 +xmm15, Class=RegSIMD|Xmmword, RegRex, 7, Dw2Inval, 32 +xmm16, Class=RegSIMD|Xmmword, RegVRex, 0, Dw2Inval, 67 +xmm17, Class=RegSIMD|Xmmword, RegVRex, 1, Dw2Inval, 68 +xmm18, Class=RegSIMD|Xmmword, RegVRex, 2, Dw2Inval, 69 +xmm19, Class=RegSIMD|Xmmword, RegVRex, 3, Dw2Inval, 70 +xmm20, Class=RegSIMD|Xmmword, RegVRex, 4, Dw2Inval, 71 +xmm21, Class=RegSIMD|Xmmword, RegVRex, 5, Dw2Inval, 72 +xmm22, Class=RegSIMD|Xmmword, RegVRex, 6, Dw2Inval, 73 +xmm23, Class=RegSIMD|Xmmword, RegVRex, 7, Dw2Inval, 74 +xmm24, Class=RegSIMD|Xmmword, RegVRex|RegRex, 0, Dw2Inval, 75 +xmm25, Class=RegSIMD|Xmmword, RegVRex|RegRex, 1, Dw2Inval, 76 +xmm26, Class=RegSIMD|Xmmword, RegVRex|RegRex, 2, Dw2Inval, 77 +xmm27, Class=RegSIMD|Xmmword, RegVRex|RegRex, 3, Dw2Inval, 78 +xmm28, Class=RegSIMD|Xmmword, RegVRex|RegRex, 4, Dw2Inval, 79 +xmm29, Class=RegSIMD|Xmmword, RegVRex|RegRex, 5, Dw2Inval, 80 +xmm30, Class=RegSIMD|Xmmword, RegVRex|RegRex, 6, Dw2Inval, 81 +xmm31, Class=RegSIMD|Xmmword, RegVRex|RegRex, 7, Dw2Inval, 82 // AVX registers. -ymm0, RegSIMD|Ymmword, 0, 0, Dw2Inval, Dw2Inval -ymm1, RegSIMD|Ymmword, 0, 1, Dw2Inval, Dw2Inval -ymm2, RegSIMD|Ymmword, 0, 2, Dw2Inval, Dw2Inval -ymm3, RegSIMD|Ymmword, 0, 3, Dw2Inval, Dw2Inval -ymm4, RegSIMD|Ymmword, 0, 4, Dw2Inval, Dw2Inval -ymm5, RegSIMD|Ymmword, 0, 5, Dw2Inval, Dw2Inval -ymm6, RegSIMD|Ymmword, 0, 6, Dw2Inval, Dw2Inval -ymm7, RegSIMD|Ymmword, 0, 7, Dw2Inval, Dw2Inval -ymm8, RegSIMD|Ymmword, RegRex, 0, Dw2Inval, Dw2Inval -ymm9, RegSIMD|Ymmword, RegRex, 1, Dw2Inval, Dw2Inval -ymm10, RegSIMD|Ymmword, RegRex, 2, Dw2Inval, Dw2Inval -ymm11, RegSIMD|Ymmword, RegRex, 3, Dw2Inval, Dw2Inval -ymm12, RegSIMD|Ymmword, RegRex, 4, Dw2Inval, Dw2Inval -ymm13, RegSIMD|Ymmword, RegRex, 5, Dw2Inval, Dw2Inval -ymm14, RegSIMD|Ymmword, RegRex, 6, Dw2Inval, Dw2Inval -ymm15, RegSIMD|Ymmword, RegRex, 7, Dw2Inval, Dw2Inval -ymm16, RegSIMD|Ymmword, RegVRex, 0, Dw2Inval, Dw2Inval -ymm17, RegSIMD|Ymmword, RegVRex, 1, Dw2Inval, Dw2Inval -ymm18, RegSIMD|Ymmword, RegVRex, 2, Dw2Inval, Dw2Inval -ymm19, RegSIMD|Ymmword, RegVRex, 3, Dw2Inval, Dw2Inval -ymm20, RegSIMD|Ymmword, RegVRex, 4, Dw2Inval, Dw2Inval -ymm21, RegSIMD|Ymmword, RegVRex, 5, Dw2Inval, Dw2Inval -ymm22, RegSIMD|Ymmword, RegVRex, 6, Dw2Inval, Dw2Inval -ymm23, RegSIMD|Ymmword, RegVRex, 7, Dw2Inval, Dw2Inval -ymm24, RegSIMD|Ymmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval -ymm25, RegSIMD|Ymmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval -ymm26, RegSIMD|Ymmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval -ymm27, RegSIMD|Ymmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval -ymm28, RegSIMD|Ymmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval -ymm29, RegSIMD|Ymmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval -ymm30, RegSIMD|Ymmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval -ymm31, RegSIMD|Ymmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval +ymm0, Class=RegSIMD|Ymmword, 0, 0, Dw2Inval, Dw2Inval +ymm1, Class=RegSIMD|Ymmword, 0, 1, Dw2Inval, Dw2Inval +ymm2, Class=RegSIMD|Ymmword, 0, 2, Dw2Inval, Dw2Inval +ymm3, Class=RegSIMD|Ymmword, 0, 3, Dw2Inval, Dw2Inval +ymm4, Class=RegSIMD|Ymmword, 0, 4, Dw2Inval, Dw2Inval +ymm5, Class=RegSIMD|Ymmword, 0, 5, Dw2Inval, Dw2Inval +ymm6, Class=RegSIMD|Ymmword, 0, 6, Dw2Inval, Dw2Inval +ymm7, Class=RegSIMD|Ymmword, 0, 7, Dw2Inval, Dw2Inval +ymm8, Class=RegSIMD|Ymmword, RegRex, 0, Dw2Inval, Dw2Inval +ymm9, Class=RegSIMD|Ymmword, RegRex, 1, Dw2Inval, Dw2Inval +ymm10, Class=RegSIMD|Ymmword, RegRex, 2, Dw2Inval, Dw2Inval +ymm11, Class=RegSIMD|Ymmword, RegRex, 3, Dw2Inval, Dw2Inval +ymm12, Class=RegSIMD|Ymmword, RegRex, 4, Dw2Inval, Dw2Inval +ymm13, Class=RegSIMD|Ymmword, RegRex, 5, Dw2Inval, Dw2Inval +ymm14, Class=RegSIMD|Ymmword, RegRex, 6, Dw2Inval, Dw2Inval +ymm15, Class=RegSIMD|Ymmword, RegRex, 7, Dw2Inval, Dw2Inval +ymm16, Class=RegSIMD|Ymmword, RegVRex, 0, Dw2Inval, Dw2Inval +ymm17, Class=RegSIMD|Ymmword, RegVRex, 1, Dw2Inval, Dw2Inval +ymm18, Class=RegSIMD|Ymmword, RegVRex, 2, Dw2Inval, Dw2Inval +ymm19, Class=RegSIMD|Ymmword, RegVRex, 3, Dw2Inval, Dw2Inval +ymm20, Class=RegSIMD|Ymmword, RegVRex, 4, Dw2Inval, Dw2Inval +ymm21, Class=RegSIMD|Ymmword, RegVRex, 5, Dw2Inval, Dw2Inval +ymm22, Class=RegSIMD|Ymmword, RegVRex, 6, Dw2Inval, Dw2Inval +ymm23, Class=RegSIMD|Ymmword, RegVRex, 7, Dw2Inval, Dw2Inval +ymm24, Class=RegSIMD|Ymmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval +ymm25, Class=RegSIMD|Ymmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval +ymm26, Class=RegSIMD|Ymmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval +ymm27, Class=RegSIMD|Ymmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval +ymm28, Class=RegSIMD|Ymmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval +ymm29, Class=RegSIMD|Ymmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval +ymm30, Class=RegSIMD|Ymmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval +ymm31, Class=RegSIMD|Ymmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval // AVX512 registers. -zmm0, RegSIMD|Zmmword, 0, 0, Dw2Inval, Dw2Inval -zmm1, RegSIMD|Zmmword, 0, 1, Dw2Inval, Dw2Inval -zmm2, RegSIMD|Zmmword, 0, 2, Dw2Inval, Dw2Inval -zmm3, RegSIMD|Zmmword, 0, 3, Dw2Inval, Dw2Inval -zmm4, RegSIMD|Zmmword, 0, 4, Dw2Inval, Dw2Inval -zmm5, RegSIMD|Zmmword, 0, 5, Dw2Inval, Dw2Inval -zmm6, RegSIMD|Zmmword, 0, 6, Dw2Inval, Dw2Inval -zmm7, RegSIMD|Zmmword, 0, 7, Dw2Inval, Dw2Inval -zmm8, RegSIMD|Zmmword, RegRex, 0, Dw2Inval, Dw2Inval -zmm9, RegSIMD|Zmmword, RegRex, 1, Dw2Inval, Dw2Inval -zmm10, RegSIMD|Zmmword, RegRex, 2, Dw2Inval, Dw2Inval -zmm11, RegSIMD|Zmmword, RegRex, 3, Dw2Inval, Dw2Inval -zmm12, RegSIMD|Zmmword, RegRex, 4, Dw2Inval, Dw2Inval -zmm13, RegSIMD|Zmmword, RegRex, 5, Dw2Inval, Dw2Inval -zmm14, RegSIMD|Zmmword, RegRex, 6, Dw2Inval, Dw2Inval -zmm15, RegSIMD|Zmmword, RegRex, 7, Dw2Inval, Dw2Inval -zmm16, RegSIMD|Zmmword, RegVRex, 0, Dw2Inval, Dw2Inval -zmm17, RegSIMD|Zmmword, RegVRex, 1, Dw2Inval, Dw2Inval -zmm18, RegSIMD|Zmmword, RegVRex, 2, Dw2Inval, Dw2Inval -zmm19, RegSIMD|Zmmword, RegVRex, 3, Dw2Inval, Dw2Inval -zmm20, RegSIMD|Zmmword, RegVRex, 4, Dw2Inval, Dw2Inval -zmm21, RegSIMD|Zmmword, RegVRex, 5, Dw2Inval, Dw2Inval -zmm22, RegSIMD|Zmmword, RegVRex, 6, Dw2Inval, Dw2Inval -zmm23, RegSIMD|Zmmword, RegVRex, 7, Dw2Inval, Dw2Inval -zmm24, RegSIMD|Zmmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval -zmm25, RegSIMD|Zmmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval -zmm26, RegSIMD|Zmmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval -zmm27, RegSIMD|Zmmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval -zmm28, RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval -zmm29, RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval -zmm30, RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval -zmm31, RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval +zmm0, Class=RegSIMD|Zmmword, 0, 0, Dw2Inval, Dw2Inval +zmm1, Class=RegSIMD|Zmmword, 0, 1, Dw2Inval, Dw2Inval +zmm2, Class=RegSIMD|Zmmword, 0, 2, Dw2Inval, Dw2Inval +zmm3, Class=RegSIMD|Zmmword, 0, 3, Dw2Inval, Dw2Inval +zmm4, Class=RegSIMD|Zmmword, 0, 4, Dw2Inval, Dw2Inval +zmm5, Class=RegSIMD|Zmmword, 0, 5, Dw2Inval, Dw2Inval +zmm6, Class=RegSIMD|Zmmword, 0, 6, Dw2Inval, Dw2Inval +zmm7, Class=RegSIMD|Zmmword, 0, 7, Dw2Inval, Dw2Inval +zmm8, Class=RegSIMD|Zmmword, RegRex, 0, Dw2Inval, Dw2Inval +zmm9, Class=RegSIMD|Zmmword, RegRex, 1, Dw2Inval, Dw2Inval +zmm10, Class=RegSIMD|Zmmword, RegRex, 2, Dw2Inval, Dw2Inval +zmm11, Class=RegSIMD|Zmmword, RegRex, 3, Dw2Inval, Dw2Inval +zmm12, Class=RegSIMD|Zmmword, RegRex, 4, Dw2Inval, Dw2Inval +zmm13, Class=RegSIMD|Zmmword, RegRex, 5, Dw2Inval, Dw2Inval +zmm14, Class=RegSIMD|Zmmword, RegRex, 6, Dw2Inval, Dw2Inval +zmm15, Class=RegSIMD|Zmmword, RegRex, 7, Dw2Inval, Dw2Inval +zmm16, Class=RegSIMD|Zmmword, RegVRex, 0, Dw2Inval, Dw2Inval +zmm17, Class=RegSIMD|Zmmword, RegVRex, 1, Dw2Inval, Dw2Inval +zmm18, Class=RegSIMD|Zmmword, RegVRex, 2, Dw2Inval, Dw2Inval +zmm19, Class=RegSIMD|Zmmword, RegVRex, 3, Dw2Inval, Dw2Inval +zmm20, Class=RegSIMD|Zmmword, RegVRex, 4, Dw2Inval, Dw2Inval +zmm21, Class=RegSIMD|Zmmword, RegVRex, 5, Dw2Inval, Dw2Inval +zmm22, Class=RegSIMD|Zmmword, RegVRex, 6, Dw2Inval, Dw2Inval +zmm23, Class=RegSIMD|Zmmword, RegVRex, 7, Dw2Inval, Dw2Inval +zmm24, Class=RegSIMD|Zmmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval +zmm25, Class=RegSIMD|Zmmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval +zmm26, Class=RegSIMD|Zmmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval +zmm27, Class=RegSIMD|Zmmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval +zmm28, Class=RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval +zmm29, Class=RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval +zmm30, Class=RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval +zmm31, Class=RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval // Bound registers for MPX bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval |