diff options
Diffstat (limited to 'opcodes/i386-opc.h')
| -rw-r--r-- | opcodes/i386-opc.h | 29 |
1 files changed, 26 insertions, 3 deletions
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index f90dff5..1a791e4 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -92,6 +92,8 @@ enum CpuSSE4_2, /* AVX support required */ CpuAVX, + /* AVX2 support required */ + CpuAVX2, /* Intel L1OM support required */ CpuL1OM, /* Xsave/xrstor New Instructions support required */ @@ -126,6 +128,12 @@ enum CpuRdRnd, /* F16C Instructions required */ CpuF16C, + /* Intel BMI2 support required */ + CpuBMI2, + /* LZCNT support required */ + CpuLZCNT, + /* INVPCID Instructions required */ + CpuINVPCID, /* 64bit support available, used by -march= in assembler. */ CpuLM, /* 64bit support required */ @@ -181,6 +189,7 @@ typedef union i386_cpu_flags unsigned int cpusse4_1:1; unsigned int cpusse4_2:1; unsigned int cpuavx:1; + unsigned int cpuavx2:1; unsigned int cpul1om:1; unsigned int cpuxsave:1; unsigned int cpuxsaveopt:1; @@ -198,6 +207,9 @@ typedef union i386_cpu_flags unsigned int cpufsgsbase:1; unsigned int cpurdrnd:1; unsigned int cpuf16c:1; + unsigned int cpubmi2:1; + unsigned int cpulzcnt:1; + unsigned int cpuinvpcid:1; unsigned int cpulm:1; unsigned int cpu64:1; unsigned int cpuno64:1; @@ -307,9 +319,12 @@ enum VEX.DDS. The second register operand is encoded in VEX.vvvv where the content of first source register will be overwritten by the result. - For assembler, there are no difference between VEX.NDS and - VEX.DDS. - 2. VEX.NDD. Register destination is encoded in VEX.vvvv. + VEX.NDD2. The second destination register operand is encoded in + VEX.vvvv for instructions with 2 destination register operands. + For assembler, there are no difference between VEX.NDS, VEX.DDS + and VEX.NDD2. + 2. VEX.NDD. Register destination is encoded in VEX.vvvv for + instructions with 1 destination register operand. 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one of the operands can access a memory location. */ @@ -350,6 +365,13 @@ enum VexSources, /* instruction has VEX 8 bit imm */ VexImmExt, + /* Instruction with vector SIB byte: + 1: 128bit vector register. + 2: 256bit vector register. + */ +#define VecSIB128 1 +#define VecSIB256 2 + VecSIB, /* SSE to AVX support required */ SSE2AVX, /* No AVX equivalent */ @@ -412,6 +434,7 @@ typedef struct i386_opcode_modifier unsigned int vexopcode:3; unsigned int vexsources:2; unsigned int veximmext:1; + unsigned int vecsib:2; unsigned int sse2avx:1; unsigned int noavx:1; unsigned int oldgcc:1; |