diff options
Diffstat (limited to 'opcodes/fr30-desc.c')
-rw-r--r-- | opcodes/fr30-desc.c | 120 |
1 files changed, 60 insertions, 60 deletions
diff --git a/opcodes/fr30-desc.c b/opcodes/fr30-desc.c index 3e15cfa..10378a5 100644 --- a/opcodes/fr30-desc.c +++ b/opcodes/fr30-desc.c @@ -263,13 +263,13 @@ const CGEN_HW_ENTRY fr30_cgen_hw_table[] = { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } }, - { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, - { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, - { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_dr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, - { "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, { { { (1<<MACH_BASE), 0 } } } } }, - { "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, { { { (1<<MACH_BASE), 0 } } } } }, - { "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, { { { (1<<MACH_BASE), 0 } } } } }, - { "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, & fr30_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, & fr30_cgen_opval_dr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, & fr30_cgen_opval_h_ps, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, & fr30_cgen_opval_h_r13, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, & fr30_cgen_opval_h_r14, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, & fr30_cgen_opval_h_r15, { 0, { { { (1<<MACH_BASE), 0 } } } } }, { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, @@ -352,9 +352,9 @@ const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [] = { - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I20_4] } }, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I20_16] } }, - { 0, { (const PTR) 0 } } + { 0, { &fr30_cgen_ifld_table[FR30_F_I20_4] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_I20_16] } }, + { 0, { 0 } } }; /* The operand table. */ @@ -366,203 +366,203 @@ const CGEN_OPERAND fr30_cgen_operand_table[] = { /* pc: program counter */ { "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_NIL] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_NIL] } }, { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* Ri: destination register */ { "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RI] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_RI] } }, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* Rj: source register */ { "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJ] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_RJ] } }, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* Ric: target register coproc insn */ { "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RIC] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_RIC] } }, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* Rjc: source register coproc insn */ { "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJC] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_RJC] } }, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* CRi: coprocessor register */ { "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRI] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_CRI] } }, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* CRj: coprocessor register */ { "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRJ] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_CRJ] } }, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* Rs1: dedicated register */ { "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS1] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_RS1] } }, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* Rs2: dedicated register */ { "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS2] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_RS2] } }, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* R13: General Register 13 */ { "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0, - { 0, { (const PTR) 0 } }, + { 0, { 0 } }, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* R14: General Register 14 */ { "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0, - { 0, { (const PTR) 0 } }, + { 0, { 0 } }, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* R15: General Register 15 */ { "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0, - { 0, { (const PTR) 0 } }, + { 0, { 0 } }, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ps: Program Status register */ { "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0, - { 0, { (const PTR) 0 } }, + { 0, { 0 } }, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* u4: 4 bit unsigned immediate */ { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_U4] } }, { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* u4c: 4 bit unsigned immediate */ { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4C] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_U4C] } }, { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* u8: 8 bit unsigned immediate */ { "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U8] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_U8] } }, { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* i8: 8 bit unsigned immediate */ { "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I8] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_I8] } }, { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* udisp6: 6 bit unsigned immediate */ { "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_UDISP6] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_UDISP6] } }, { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* disp8: 8 bit signed immediate */ { "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP8] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_DISP8] } }, { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* disp9: 9 bit signed immediate */ { "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP9] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_DISP9] } }, { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* disp10: 10 bit signed immediate */ { "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP10] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_DISP10] } }, { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* s10: 10 bit signed immediate */ { "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_S10] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_S10] } }, { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* u10: 10 bit unsigned immediate */ { "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U10] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_U10] } }, { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* i32: 32 bit immediate */ { "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I32] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_I32] } }, { 0|A(HASH_PREFIX)|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, /* m4: 4 bit negative immediate */ { "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_M4] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_M4] } }, { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* i20: 20 bit immediate */ { "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20, - { 2, { (const PTR) &FR30_F_I20_MULTI_IFIELD[0] } }, + { 2, { &FR30_F_I20_MULTI_IFIELD[0] } }, { 0|A(HASH_PREFIX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, /* dir8: 8 bit direct address */ { "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR8] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_DIR8] } }, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* dir9: 9 bit direct address */ { "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR9] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_DIR9] } }, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* dir10: 10 bit direct address */ { "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR10] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_DIR10] } }, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* label9: 9 bit pc relative address */ { "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL9] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_REL9] } }, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* label12: 12 bit pc relative address */ { "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL12] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_REL12] } }, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, /* reglist_low_ld: 8 bit low register mask for ldm */ { "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_LD] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_LD] } }, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* reglist_hi_ld: 8 bit high register mask for ldm */ { "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_LD] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_LD] } }, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* reglist_low_st: 8 bit low register mask for stm */ { "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_ST] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_ST] } }, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* reglist_hi_st: 8 bit high register mask for stm */ { "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_ST] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_ST] } }, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* cc: condition codes */ { "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CC] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_CC] } }, { 0, { { { (1<<MACH_BASE), 0 } } } } }, /* ccc: coprocessor calc */ { "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8, - { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CCC] } }, + { 0, { &fr30_cgen_ifld_table[FR30_F_CCC] } }, { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, /* nbit: negative bit */ { "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0, - { 0, { (const PTR) 0 } }, + { 0, { 0 } }, { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* vbit: overflow bit */ { "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0, - { 0, { (const PTR) 0 } }, + { 0, { 0 } }, { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* zbit: zero bit */ { "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0, - { 0, { (const PTR) 0 } }, + { 0, { 0 } }, { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* cbit: carry bit */ { "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0, - { 0, { (const PTR) 0 } }, + { 0, { 0 } }, { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* ibit: interrupt bit */ { "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0, - { 0, { (const PTR) 0 } }, + { 0, { 0 } }, { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* sbit: stack bit */ { "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0, - { 0, { (const PTR) 0 } }, + { 0, { 0 } }, { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* tbit: trace trap bit */ { "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0, - { 0, { (const PTR) 0 } }, + { 0, { 0 } }, { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* d0bit: division 0 bit */ { "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0, - { 0, { (const PTR) 0 } }, + { 0, { 0 } }, { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* d1bit: division 1 bit */ { "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0, - { 0, { (const PTR) 0 } }, + { 0, { 0 } }, { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* ccr: condition code bits */ { "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0, - { 0, { (const PTR) 0 } }, + { 0, { 0 } }, { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* scr: system condition bits */ { "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0, - { 0, { (const PTR) 0 } }, + { 0, { 0 } }, { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* ilm: interrupt level mask */ { "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0, - { 0, { (const PTR) 0 } }, + { 0, { 0 } }, { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, /* sentinel */ { 0, 0, 0, 0, 0, - { 0, { (const PTR) 0 } }, + { 0, { 0 } }, { 0, { { { (1<<MACH_BASE), 0 } } } } } }; |