diff options
Diffstat (limited to 'opcodes/fr30-desc.c')
| -rw-r--r-- | opcodes/fr30-desc.c | 74 |
1 files changed, 69 insertions, 5 deletions
diff --git a/opcodes/fr30-desc.c b/opcodes/fr30-desc.c index d9b347f..fd6afee 100644 --- a/opcodes/fr30-desc.c +++ b/opcodes/fr30-desc.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -346,6 +346,21 @@ const CGEN_IFLD fr30_cgen_ifld_table[] = #undef A + +/* multi ifield declarations */ + +const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD []; + + +/* multi ifield definitions */ + +const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [] = +{ + { 0, &(fr30_cgen_ifld_table[23]) }, + { 0, &(fr30_cgen_ifld_table[24]) }, + {0,0} +}; + /* The operand table. */ #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) @@ -363,150 +378,199 @@ const CGEN_OPERAND fr30_cgen_operand_table[] = { /* pc: program counter */ { "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0, + { 0, &(fr30_cgen_ifld_table[0]) }, { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, /* Ri: destination register */ { "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4, + { 0, &(fr30_cgen_ifld_table[10]) }, { 0, { (1<<MACH_BASE) } } }, /* Rj: source register */ { "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4, + { 0, &(fr30_cgen_ifld_table[9]) }, { 0, { (1<<MACH_BASE) } } }, /* Ric: target register coproc insn */ { "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4, + { 0, &(fr30_cgen_ifld_table[14]) }, { 0, { (1<<MACH_BASE) } } }, /* Rjc: source register coproc insn */ { "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4, + { 0, &(fr30_cgen_ifld_table[13]) }, { 0, { (1<<MACH_BASE) } } }, /* CRi: coprocessor register */ { "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4, + { 0, &(fr30_cgen_ifld_table[16]) }, { 0, { (1<<MACH_BASE) } } }, /* CRj: coprocessor register */ { "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4, + { 0, &(fr30_cgen_ifld_table[15]) }, { 0, { (1<<MACH_BASE) } } }, /* Rs1: dedicated register */ { "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4, + { 0, &(fr30_cgen_ifld_table[11]) }, { 0, { (1<<MACH_BASE) } } }, /* Rs2: dedicated register */ { "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4, + { 0, &(fr30_cgen_ifld_table[12]) }, { 0, { (1<<MACH_BASE) } } }, /* R13: General Register 13 */ { "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0, + { 0, 0 }, { 0, { (1<<MACH_BASE) } } }, /* R14: General Register 14 */ { "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0, + { 0, 0 }, { 0, { (1<<MACH_BASE) } } }, /* R15: General Register 15 */ { "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0, + { 0, 0 }, { 0, { (1<<MACH_BASE) } } }, /* ps: Program Status register */ { "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0, + { 0, 0 }, { 0, { (1<<MACH_BASE) } } }, /* u4: 4 bit unsigned immediate */ { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4, + { 0, &(fr30_cgen_ifld_table[17]) }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* u4c: 4 bit unsigned immediate */ { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4, + { 0, &(fr30_cgen_ifld_table[18]) }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* u8: 8 bit unsigned immediate */ { "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8, + { 0, &(fr30_cgen_ifld_table[21]) }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* i8: 8 bit unsigned immediate */ { "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8, + { 0, &(fr30_cgen_ifld_table[22]) }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* udisp6: 6 bit unsigned immediate */ { "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4, + { 0, &(fr30_cgen_ifld_table[26]) }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* disp8: 8 bit signed immediate */ { "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8, + { 0, &(fr30_cgen_ifld_table[27]) }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* disp9: 9 bit signed immediate */ { "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8, + { 0, &(fr30_cgen_ifld_table[28]) }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* disp10: 10 bit signed immediate */ { "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8, + { 0, &(fr30_cgen_ifld_table[29]) }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* s10: 10 bit signed immediate */ { "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8, + { 0, &(fr30_cgen_ifld_table[30]) }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* u10: 10 bit unsigned immediate */ { "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8, + { 0, &(fr30_cgen_ifld_table[31]) }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* i32: 32 bit immediate */ { "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32, + { 0, &(fr30_cgen_ifld_table[25]) }, { 0|A(HASH_PREFIX)|A(SIGN_OPT), { (1<<MACH_BASE) } } }, /* m4: 4 bit negative immediate */ { "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4, + { 0, &(fr30_cgen_ifld_table[20]) }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* i20: 20 bit immediate */ { "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20, + { 2, &(FR30_F_I20_MULTI_IFIELD[0]) }, { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } } }, /* dir8: 8 bit direct address */ { "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8, + { 0, &(fr30_cgen_ifld_table[33]) }, { 0, { (1<<MACH_BASE) } } }, /* dir9: 9 bit direct address */ { "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8, + { 0, &(fr30_cgen_ifld_table[34]) }, { 0, { (1<<MACH_BASE) } } }, /* dir10: 10 bit direct address */ { "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8, + { 0, &(fr30_cgen_ifld_table[35]) }, { 0, { (1<<MACH_BASE) } } }, /* label9: 9 bit pc relative address */ { "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8, + { 0, &(fr30_cgen_ifld_table[32]) }, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, /* label12: 12 bit pc relative address */ { "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11, + { 0, &(fr30_cgen_ifld_table[36]) }, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, /* reglist_low_ld: 8 bit low register mask for ldm */ { "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8, + { 0, &(fr30_cgen_ifld_table[40]) }, { 0, { (1<<MACH_BASE) } } }, /* reglist_hi_ld: 8 bit high register mask for ldm */ { "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8, + { 0, &(fr30_cgen_ifld_table[39]) }, { 0, { (1<<MACH_BASE) } } }, /* reglist_low_st: 8 bit low register mask for stm */ { "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8, + { 0, &(fr30_cgen_ifld_table[38]) }, { 0, { (1<<MACH_BASE) } } }, /* reglist_hi_st: 8 bit high register mask for stm */ { "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8, + { 0, &(fr30_cgen_ifld_table[37]) }, { 0, { (1<<MACH_BASE) } } }, /* cc: condition codes */ { "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4, + { 0, &(fr30_cgen_ifld_table[7]) }, { 0, { (1<<MACH_BASE) } } }, /* ccc: coprocessor calc */ { "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8, + { 0, &(fr30_cgen_ifld_table[8]) }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* nbit: negative bit */ { "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0, + { 0, 0 }, { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, /* vbit: overflow bit */ { "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0, + { 0, 0 }, { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, /* zbit: zero bit */ { "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0, + { 0, 0 }, { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, /* cbit: carry bit */ { "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0, + { 0, 0 }, { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, /* ibit: interrupt bit */ { "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0, + { 0, 0 }, { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, /* sbit: stack bit */ { "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0, + { 0, 0 }, { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, /* tbit: trace trap bit */ { "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0, + { 0, 0 }, { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, /* d0bit: division 0 bit */ { "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0, + { 0, 0 }, { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, /* d1bit: division 1 bit */ { "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0, + { 0, 0 }, { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, /* ccr: condition code bits */ { "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0, + { 0, 0 }, { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, /* scr: system condition bits */ { "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0, + { 0, 0 }, { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, /* ilm: interrupt level mask */ { "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0, + { 0, 0 }, { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, { 0, 0, 0, 0, 0, {0, {0}} } }; @@ -1501,8 +1565,8 @@ fr30_cgen_rebuild_tables (cd) { const CGEN_ISA *isa = & fr30_cgen_isa_table[i]; - /* Default insn sizes of all selected isas must be equal or we set - the result to 0, meaning "unknown". */ + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ if (cd->default_insn_bitsize == UNSET) cd->default_insn_bitsize = isa->default_insn_bitsize; else if (isa->default_insn_bitsize == cd->default_insn_bitsize) @@ -1510,8 +1574,8 @@ fr30_cgen_rebuild_tables (cd) else cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; - /* Base insn sizes of all selected isas must be equal or we set - the result to 0, meaning "unknown". */ + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ if (cd->base_insn_bitsize == UNSET) cd->base_insn_bitsize = isa->base_insn_bitsize; else if (isa->base_insn_bitsize == cd->base_insn_bitsize) |