diff options
Diffstat (limited to 'opcodes/d10v-opc.c')
| -rw-r--r-- | opcodes/d10v-opc.c | 95 |
1 files changed, 53 insertions, 42 deletions
diff --git a/opcodes/d10v-opc.c b/opcodes/d10v-opc.c index 80e7180..755d230 100644 --- a/opcodes/d10v-opc.c +++ b/opcodes/d10v-opc.c @@ -66,7 +66,6 @@ reg_name_cnt() return (sizeof(pre_defined_registers) / sizeof(struct pd_reg)); } - const struct d10v_operand d10v_operands[] = { #define UNUSED (0) @@ -84,17 +83,21 @@ const struct d10v_operand d10v_operands[] = #define RDSTE (RSRCE + 1) { 4, 5, OPERAND_EVEN|OPERAND_DEST|OPERAND_REG }, #define NUM16 (RDSTE + 1) - { 16, 0, OPERAND_NUM }, -#define NUM3 (NUM16 + 1) - { 3, 1, OPERAND_NUM }, + { 16, 0, OPERAND_NUM|OPERAND_SIGNED }, +#define NUM3 (NUM16 + 1) /* rac, rachi */ + { 3, 1, OPERAND_NUM|OPERAND_SIGNED }, #define NUM4 (NUM3 + 1) + { 4, 1, OPERAND_NUM|OPERAND_SIGNED }, +#define UNUM4 (NUM4 + 1) { 4, 1, OPERAND_NUM }, -#define NUM8 (NUM4 + 1) /* only used in REPI */ +#define UNUM8 (UNUM4 + 1) /* repi */ { 8, 16, OPERAND_NUM }, -#define ANUM16 (NUM8 + 1) - { 16, 0, OPERAND_ADDR }, +#define UNUM16 (UNUM8 + 1) /* cmpui */ + { 16, 0, OPERAND_NUM }, +#define ANUM16 (UNUM16 + 1) + { 16, 0, OPERAND_ADDR|OPERAND_SIGNED }, #define ANUM8 (ANUM16 + 1) - { 8, 0, OPERAND_ADDR }, + { 8, 0, OPERAND_ADDR|OPERAND_SIGNED }, #define ASRC2 (ANUM8 + 1) { 1, 8, OPERAND_ACC|OPERAND_REG }, #define RSRC2 (ASRC2 + 1) @@ -137,42 +140,49 @@ const struct d10v_opcode d10v_opcodes[] = { { "addac3", LONG_R, 1, IU, SEQ, 0x17000202, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, { "addac3s", LONG_R, 1, IU, SEQ, 0x17001200, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, { "addac3s", LONG_R, 1, IU, SEQ, 0x17001202, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, - { "addi", SHORT_2, 1, EITHER, PAR, 0x201, 0x7e01, { RDST, NUM4 } }, + { "addi", SHORT_2, 1, EITHER, PAR, 0x201, 0x7e01, { RDST, UNUM4 } }, { "and", SHORT_2, 1, EITHER, PAR, 0xc00, 0x7e01, { RDST, RSRC } }, { "and3", LONG_L, 1, MU, SEQ, 0x6000000, 0x3f000000, { RDST, RSRC, NUM16 } }, - { "bclri", SHORT_2, 1, IU, PAR, 0xc01, 0x7e01, { RDST, NUM4 } }, - { "bl", LONG_B, 3, MU, BRANCH_LINK, 0x24800000, 0x3fff8000, { ANUM16 } }, + { "bclri", SHORT_2, 1, IU, PAR, 0xc01, 0x7e01, { RDST, UNUM4 } }, + { "bl", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } }, { "bl.s", SHORT_B, 3, MU, BRANCH_LINK, 0x4900, 0x7f00, { ANUM8 } }, - { "bnoti", SHORT_2, 1, IU, PAR, 0xa01, 0x7e01, { RDST, NUM4 } }, - { "bra", LONG_B, 3, MU, SEQ, 0x24000000, 0x3fff0000, { ANUM16 } }, + { "bl.l", LONG_B, 3, MU, BRANCH_LINK, 0x24800000, 0x3fff8000, { ANUM16 } }, + { "bnoti", SHORT_2, 1, IU, PAR, 0xa01, 0x7e01, { RDST, UNUM4 } }, + { "bra", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } }, { "bra.s", SHORT_B, 3, MU, PAR, 0x4800, 0x7f00, { ANUM8 } }, - { "brf0f", LONG_B, 3, MU, SEQ, 0x25000000, 0x3fff0000, { ANUM16 } }, + { "bra.l", LONG_B, 3, MU, SEQ, 0x24000000, 0x3fff0000, { ANUM16 } }, + { "brf0f", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } }, { "brf0f.s", SHORT_B, 3, MU, PAR, 0x4a00, 0x7f00, { ANUM8 } }, - { "brf0t", LONG_B, 3, MU, SEQ, 0x25800000, 0x3fff0000, { ANUM16 } }, + { "brf0f.l", LONG_B, 3, MU, SEQ, 0x25000000, 0x3fff0000, { ANUM16 } }, + { "brf0t", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } }, { "brf0t.s", SHORT_B, 3, MU, PAR, 0x4b00, 0x7f00, { ANUM8 } }, - { "bseti", SHORT_2, 1, IU, PAR, 0x801, 0x7e01, { RDST, NUM4 } }, - { "btsti", SHORT_2, 1, IU, PAR, 0xe01, 0x7e01, { RDST, NUM4 } }, + { "brf0t.l", LONG_B, 3, MU, SEQ, 0x25800000, 0x3fff0000, { ANUM16 } }, + { "bseti", SHORT_2, 1, IU, PAR, 0x801, 0x7e01, { RDST, UNUM4 } }, + { "btsti", SHORT_2, 1, IU, PAR, 0xe01, 0x7e01, { RDST, UNUM4 } }, { "clrac", SHORT_2, 1, IU, PAR, 0x5601, 0x7eff, { ADST } }, { "cmp", SHORT_2, 1, EITHER, PAR, 0x600, 0x7e01, { RSRC2, RSRC } }, { "cmp", SHORT_2, 1, IU, PAR, 0x1603, 0x7eef, { ASRC2, ASRC } }, { "cmpeq", SHORT_2, 1, EITHER, PAR, 0x400, 0x7e01, { RSRC2, RSRC } }, { "cmpeq", SHORT_2, 1, IU, PAR, 0x1403, 0x7eef, { ASRC2, ASRC } }, - { "cmpeqi", SHORT_2, 1, EITHER, PAR, 0x401, 0x7e01, { RSRC2, NUM4 } }, - { "cmpeqi", LONG_L, 1, MU, SEQ, 0x2000000, 0x3f0f0000, { RSRC2, NUM16 } }, - { "cmpi", SHORT_2, 1, EITHER, PAR, 0x601, 0x7e01, { RSRC2, NUM4 } }, - { "cmpi", LONG_L, 1, MU, SEQ, 0x3000000, 0x3f0f0000, { RSRC2, NUM16 } }, + { "cmpeqi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } }, + { "cmpeqi.s", SHORT_2, 1, EITHER, PAR, 0x401, 0x7e01, { RSRC2, NUM4 } }, + { "cmpeqi.l", LONG_L, 1, MU, SEQ, 0x2000000, 0x3f0f0000, { RSRC2, NUM16 } }, + { "cmpi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } }, + { "cmpi.s", SHORT_2, 1, EITHER, PAR, 0x601, 0x7e01, { RSRC2, NUM4 } }, + { "cmpi.l", LONG_L, 1, MU, SEQ, 0x3000000, 0x3f0f0000, { RSRC2, NUM16 } }, { "cmpu", SHORT_2, 1, EITHER, PAR, 0x4600, 0x7e01, { RSRC2, RSRC } }, - { "cmpui", LONG_L, 1, MU, SEQ, 0x23000000, 0x3f0f0000, { RSRC2, NUM16 } }, + { "cmpui", LONG_L, 1, MU, SEQ, 0x23000000, 0x3f0f0000, { RSRC2, UNUM16 } }, { "cpfg", SHORT_2, 1, MU, PAR, 0x4e09, 0x7fd9, { FDST, FSRC } }, { "dbt", SHORT_2, 5, MU, PAR, 0x5f20, 0x7fff, { 0 } }, - { "exef0f", SHORT_2, 1, EITHER, PAR, 0x4e04, 0x7fff, { 0 } }, - { "exef0t", SHORT_2, 1, EITHER, PAR, 0x4e24, 0x7fff, { 0 } }, - { "exef1f", SHORT_2, 1, EITHER, PAR, 0x4e40, 0x7fff, { 0 } }, - { "exef1t", SHORT_2, 1, EITHER, PAR, 0x4e42, 0x7fff, { 0 } }, - { "exefaf", SHORT_2, 1, EITHER, PAR, 0x4e00, 0x7fff, { 0 } }, - { "exefat", SHORT_2, 1, EITHER, PAR, 0x4e02, 0x7fff, { 0 } }, - { "exetaf", SHORT_2, 1, EITHER, PAR, 0x4e20, 0x7fff, { 0 } }, - { "exetat", SHORT_2, 1, EITHER, PAR, 0x4e22, 0x7fff, { 0 } }, + { "divs", LONG_L, 1, BOTH, SEQ, 0x14002800, 0x3f10fe21, { RDSTE, RSRC } }, + { "exef0f", SHORT_2, 1, EITHER, PARONLY, 0x4e04, 0x7fff, { 0 } }, + { "exef0t", SHORT_2, 1, EITHER, PARONLY, 0x4e24, 0x7fff, { 0 } }, + { "exef1f", SHORT_2, 1, EITHER, PARONLY, 0x4e40, 0x7fff, { 0 } }, + { "exef1t", SHORT_2, 1, EITHER, PARONLY, 0x4e42, 0x7fff, { 0 } }, + { "exefaf", SHORT_2, 1, EITHER, PARONLY, 0x4e00, 0x7fff, { 0 } }, + { "exefat", SHORT_2, 1, EITHER, PARONLY, 0x4e02, 0x7fff, { 0 } }, + { "exetaf", SHORT_2, 1, EITHER, PARONLY, 0x4e20, 0x7fff, { 0 } }, + { "exetat", SHORT_2, 1, EITHER, PARONLY, 0x4e22, 0x7fff, { 0 } }, { "exp", LONG_R, 1, IU, SEQ, 0x15002a00, 0x3ffffe03, { RDST, RSRCE } }, { "exp", LONG_R, 1, IU, SEQ, 0x15002a02, 0x3ffffe0f, { RDST, ASRC } }, { "jl", SHORT_2, 3, MU, BRANCH_LINK, 0x4d00, 0x7fe1, { RSRC } }, @@ -187,8 +197,9 @@ const struct d10v_opcode d10v_opcodes[] = { { "ld2w", SHORT_2, 1, MU, PAR, 0x6200, 0x7e21, { RDSTE, ATSIGN, RSRC } }, { "ldb", LONG_L, 1, MU, SEQ, 0x38000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } }, { "ldb", SHORT_2, 1, MU, PAR, 0x7000, 0x7e01, { RDST, ATSIGN, RSRC } }, - { "ldi", LONG_L, 1, MU, SEQ, 0x20000000, 0x3f0f0000, { RDST, NUM16 } }, - { "ldi", SHORT_2, 1, EITHER, PAR,0x4001, 0x7e01 , { RDST, NUM4 } }, + { "ldi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } }, + { "ldi.s", SHORT_2, 1, EITHER, PAR,0x4001, 0x7e01 , { RDST, NUM4 } }, + { "ldi.l", LONG_L, 1, MU, SEQ, 0x20000000, 0x3f0f0000, { RDST, NUM16 } }, { "ldub", LONG_L, 1, MU, SEQ, 0x39000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } }, { "ldub", SHORT_2, 1, MU, PAR, 0x7200, 0x7e01, { RDST, ATSIGN, RSRC } }, { "mac", SHORT_2, 1, IU, PAR, 0x2a00, 0x7e00, { ADST0, RSRC2, RSRC } }, @@ -233,7 +244,7 @@ const struct d10v_opcode d10v_opcodes[] = { { "rac", SHORT_2, 1, IU, PAR, 0x5201, 0x7e21, { RDSTE, ASRC, NUM3 } }, { "rachi", SHORT_2, 1, IU, PAR, 0x4201, 0x7e01, { RDST, ASRC, NUM3 } }, { "rep", LONG_L, 2, MU, SEQ, 0x27000000, 0x3ff00000, { RSRC, ANUM16 } }, - { "repi", LONG_L, 2, MU, SEQ, 0x2f000000, 0x3f000000, { NUM8, ANUM16 } }, + { "repi", LONG_L, 2, MU, SEQ, 0x2f000000, 0x3f000000, { UNUM8, ANUM16 } }, { "rtd", SHORT_2, 3, MU, PAR, 0x5f60, 0x7fff, { 0 } }, { "rte", SHORT_2, 3, MU, PAR, 0x5f40, 0x7ff, { 0 } }, { "sadd", SHORT_2, 1, IU, PAR, 0x1223, 0x7eef, { ADST, ASRC } }, @@ -242,17 +253,17 @@ const struct d10v_opcode d10v_opcodes[] = { { "sleep", SHORT_2, 1, MU, PAR, 0x5fc0, 0x7fff, { 0 } }, { "sll", SHORT_2, 1, IU, PAR, 0x2200, 0x7e01, { RDST, RSRC } }, { "sll", SHORT_2, 1, IU, PAR, 0x3200, 0x7ee1, { ADST, RSRC } }, - { "slli", SHORT_2, 1, IU, PAR, 0x2201, 0x7e01, { RDST, NUM4 } }, - { "slli", SHORT_2, 1, IU, PAR, 0x3201, 0x7ee1, { ADST, NUM4 } }, + { "slli", SHORT_2, 1, IU, PAR, 0x2201, 0x7e01, { RDST, UNUM4 } }, + { "slli", SHORT_2, 1, IU, PAR, 0x3201, 0x7ee1, { ADST, UNUM4 } }, { "slx", SHORT_2, 1, IU, PAR, 0x460b, 0x7e1f, { RDST } }, { "sra", SHORT_2, 1, IU, PAR, 0x2400, 0x7e01, { RDST, RSRC } }, { "sra", SHORT_2, 1, IU, PAR, 0x3400, 0x7ee1, { ADST, RSRC } }, - { "srai", SHORT_2, 1, IU, PAR, 0x2401, 0x7e01, { RDST, NUM4 } }, - { "srai", SHORT_2, 1, IU, PAR, 0x3401, 0x7ee1, { ADST, NUM4 } }, + { "srai", SHORT_2, 1, IU, PAR, 0x2401, 0x7e01, { RDST, UNUM4 } }, + { "srai", SHORT_2, 1, IU, PAR, 0x3401, 0x7ee1, { ADST, UNUM4 } }, { "srl", SHORT_2, 1, IU, PAR, 0x2000, 0x7e01, { RDST, RSRC } }, { "srl", SHORT_2, 1, IU, PAR, 0x3000, 0x7ee1, { ADST, RSRC } }, - { "srli", SHORT_2, 1, IU, PAR, 0x2001, 0x7e01, { RDST, NUM4 } }, - { "srli", SHORT_2, 1, IU, PAR, 0x3001, 0x7ee1, { ADST, NUM4 } }, + { "srli", SHORT_2, 1, IU, PAR, 0x2001, 0x7e01, { RDST, UNUM4 } }, + { "srli", SHORT_2, 1, IU, PAR, 0x3001, 0x7ee1, { ADST, UNUM4 } }, { "srx", SHORT_2, 1, IU, PAR, 0x4609, 0x7e1f, { RDST } }, { "st", LONG_L, 1, MU, SEQ, 0x34000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } }, { "st", SHORT_2, 1, MU, PAR, 0x6800, 0x7e01, { RSRC2, ATSIGN, RSRC } }, @@ -266,15 +277,15 @@ const struct d10v_opcode d10v_opcodes[] = { { "st2w", SHORT_2, 1, MU, PAR, 0x6e01, 0x7e21, { RSRC2E, ATSIGN, RSRC, MINUS } }, { "stb", LONG_L, 1, MU, SEQ, 0x3c000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } }, { "stb", SHORT_2, 1, MU, PAR, 0x7800, 0x7e01, { RSRC2, ATSIGN, RSRC } }, - /* { "stop", SHORT_2, 1, MU, PAR, 0x5fe0, 0x7fff, { 0 } }, */ + { "stop", SHORT_2, 1, MU, PAR, 0x5fe0, 0x7fff, { 0 } }, { "sub", SHORT_2, 1, EITHER, PAR, 0x0, 0x7e01, { RDST, RSRC } }, { "sub2w", SHORT_2, 1, IU, PAR, 0x1000, 0x7e23, { RDSTE, RSRCE } }, { "subac3", LONG_R, 1, IU, SEQ, 0x17000000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, { "subac3", LONG_R, 1, IU, SEQ, 0x17000002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, { "subac3s", LONG_R, 1, IU, SEQ, 0x17001000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, { "subac3s", LONG_R, 1, IU, SEQ, 0x17001002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, - { "subi", SHORT_2, 1, EITHER, PAR, 0x1, 0x7e01, { RDST, NUM4 } }, - { "trap", SHORT_2, 5, MU, PAR, 0x5f00, 0x7fe1, { NUM4 } }, + { "subi", SHORT_2, 1, EITHER, PAR, 0x1, 0x7e01, { RDST, UNUM4 } }, + { "trap", SHORT_2, 5, MU, PAR, 0x5f00, 0x7fe1, { UNUM4 } }, { "tst0i", LONG_L, 1, MU, SEQ, 0x7000000, 0x3f0f0000, { RSRC2, NUM16 } }, { "tst1i", LONG_L, 1, MU, SEQ, 0xf000000, 0x3f0f0000, { RSRC2, NUM16 } }, { "wait", SHORT_2, 1, MU, PAR, 0x5f80, 0x7fff, { 0 } }, |