diff options
Diffstat (limited to 'opcodes/arm-dis.c')
| -rw-r--r-- | opcodes/arm-dis.c | 30 |
1 files changed, 18 insertions, 12 deletions
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 94fe304..34f0e62 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -1581,33 +1581,33 @@ static const struct opcode32 arm_opcodes[] = 0x0320f005, 0x0fffffff, "sevl"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS), 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"}, /* CRC32 instructions. */ {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), @@ -2524,6 +2524,12 @@ static const struct opcode16 thumb_opcodes[] = makes heavy use of special-case bit patterns. */ static const struct opcode32 thumb32_opcodes[] = { + /* V8-M instructions. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), + 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), + 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"}, + /* V8 instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3af8005, 0xffffffff, "sevl%c.w"}, |