diff options
Diffstat (limited to 'opcodes/arc-dis.c')
| -rw-r--r-- | opcodes/arc-dis.c | 266 |
1 files changed, 116 insertions, 150 deletions
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c index f614cc3..fe835ae 100644 --- a/opcodes/arc-dis.c +++ b/opcodes/arc-dis.c @@ -1,5 +1,5 @@ /* Instruction printing code for the ARC. - Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002 + Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2005 Free Software Foundation, Inc. Contributed by Doug Evans (dje@cygnus.com). @@ -15,7 +15,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "ansidecl.h" #include "libiberty.h" @@ -34,11 +35,11 @@ #define dbg (0) #endif - /* Classification of the opcodes for the decoder to print the instructions. */ -typedef enum { +typedef enum +{ CLASS_A4_ARITH, CLASS_A4_OP3_GENERAL, CLASS_A4_FLAG, @@ -56,7 +57,6 @@ typedef enum { CLASS_A4_LR } a4_decoding_class; - #define BIT(word,n) ((word) & (1 << n)) #define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e))) #define OPCODE(word) (BITS ((word), 27, 31)) @@ -64,7 +64,6 @@ typedef enum { #define FIELDB(word) (BITS ((word), 15, 20)) #define FIELDC(word) (BITS ((word), 9, 14)) - /* FIELD D is signed in all of its uses, so we make sure argument is treated as signed for bit shifting purposes: */ #define FIELDD(word) (BITS (((signed int)word), 0, 8)) @@ -146,15 +145,15 @@ typedef enum { } \ while (0) -#define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257)) -#define IS_REG(x) (field##x##isReg) -#define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT(x,"[","]","","") -#define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT(x,"",",[","",",[") -#define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT(x,",","]",",","]") -#define WRITE_FORMAT_x_RB(x) WRITE_FORMAT(x,"","]","","]") -#define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT(x,",","",",","") -#define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT(x,"",",","",",") -#define WRITE_FORMAT_x(x) WRITE_FORMAT(x,"","","","") +#define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257)) +#define IS_REG(x) (field##x##isReg) +#define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT (x, "[","]","","") +#define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT (x, "",",[","",",[") +#define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT (x, ",","]",",","]") +#define WRITE_FORMAT_x_RB(x) WRITE_FORMAT (x, "","]","","]") +#define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT (x, ",","",",","") +#define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT (x, "",",","",",") +#define WRITE_FORMAT_x(x) WRITE_FORMAT (x, "","","","") #define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \ (IS_REG (x) ? cb1"%r"ca1 : \ usesAuxReg ? cb"%a"ca : \ @@ -169,25 +168,8 @@ typedef enum { static char comment_prefix[] = "\t; "; -static const char *core_reg_name PARAMS ((struct arcDisState *, int)); -static const char *aux_reg_name PARAMS ((struct arcDisState *, int)); -static const char *cond_code_name PARAMS ((struct arcDisState *, int)); -static const char *instruction_name - PARAMS ((struct arcDisState *, int, int, int *)); -static void mwerror PARAMS ((struct arcDisState *, const char *)); -static const char *post_address PARAMS ((struct arcDisState *, int)); -static void write_comments_ - PARAMS ((struct arcDisState *, int, int, long int)); -static void write_instr_name_ - PARAMS ((struct arcDisState *, const char *, int, int, int, int, int, int)); -static int dsmOneArcInst PARAMS ((bfd_vma, struct arcDisState *)); -static const char *_coreRegName PARAMS ((void *, int)); -static int decodeInstr PARAMS ((bfd_vma, disassemble_info *)); - static const char * -core_reg_name (state, val) - struct arcDisState * state; - int val; +core_reg_name (struct arcDisState * state, int val) { if (state->coreRegName) return (*state->coreRegName)(state->_this, val); @@ -195,9 +177,7 @@ core_reg_name (state, val) } static const char * -aux_reg_name (state, val) - struct arcDisState * state; - int val; +aux_reg_name (struct arcDisState * state, int val) { if (state->auxRegName) return (*state->auxRegName)(state->_this, val); @@ -205,9 +185,7 @@ aux_reg_name (state, val) } static const char * -cond_code_name (state, val) - struct arcDisState * state; - int val; +cond_code_name (struct arcDisState * state, int val) { if (state->condCodeName) return (*state->condCodeName)(state->_this, val); @@ -215,11 +193,10 @@ cond_code_name (state, val) } static const char * -instruction_name (state, op1, op2, flags) - struct arcDisState * state; - int op1; - int op2; - int * flags; +instruction_name (struct arcDisState * state, + int op1, + int op2, + int * flags) { if (state->instName) return (*state->instName)(state->_this, op1, op2, flags); @@ -227,18 +204,14 @@ instruction_name (state, op1, op2, flags) } static void -mwerror (state, msg) - struct arcDisState * state; - const char * msg; +mwerror (struct arcDisState * state, const char * msg) { if (state->err != 0) (*state->err)(state->_this, (msg)); } static const char * -post_address (state, addr) - struct arcDisState * state; - int addr; +post_address (struct arcDisState * state, int addr) { static char id[3 * ARRAY_SIZE (state->addresses)]; int j, i = state->acnt; @@ -257,22 +230,16 @@ post_address (state, addr) return ""; } -static void my_sprintf PARAMS ((struct arcDisState *, char *, const char *, - ...)); - static void -my_sprintf VPARAMS ((struct arcDisState *state, char *buf, const char *format, - ...)) +arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...) { char *bp; const char *p; int size, leading_zero, regMap[2]; long auxNum; + va_list ap; - VA_OPEN (ap, format); - VA_FIXEDARG (ap, struct arcDisState *, state); - VA_FIXEDARG (ap, char *, buf); - VA_FIXEDARG (ap, const char *, format); + va_start (ap, format); bp = buf; *bp = 0; @@ -413,7 +380,7 @@ my_sprintf VPARAMS ((struct arcDisState *state, char *buf, const char *format, if (ext) sprintf (bp, "%s", ext); else - my_sprintf (state, bp, "%h", val); + arc_sprintf (state, bp, "%h", val); } break; } @@ -435,15 +402,14 @@ my_sprintf VPARAMS ((struct arcDisState *state, char *buf, const char *format, } DOCOMM: *bp = 0; - VA_CLOSE (ap); + va_end (ap); } static void -write_comments_(state, shimm, is_limm, limm_value) - struct arcDisState * state; - int shimm; - int is_limm; - long limm_value; +write_comments_(struct arcDisState * state, + int shimm, + int is_limm, + long limm_value) { if (state->commentBuffer != 0) { @@ -468,25 +434,25 @@ write_comments_(state, shimm, is_limm, limm_value) } } -#define write_comments2(x) write_comments_(state, x, is_limm, limm_value) -#define write_comments() write_comments2(0) +#define write_comments2(x) write_comments_ (state, x, is_limm, limm_value) +#define write_comments() write_comments2 (0) -static const char *condName[] = { +static const char *condName[] = +{ /* 0..15. */ "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" , "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz" }; static void -write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend, addrWriteBack, directMem) - struct arcDisState * state; - const char * instrName; - int cond; - int condCodeIsPartOfName; - int flag; - int signExtend; - int addrWriteBack; - int directMem; +write_instr_name_(struct arcDisState * state, + const char * instrName, + int cond, + int condCodeIsPartOfName, + int flag, + int signExtend, + int addrWriteBack, + int directMem) { strcpy (state->instrBuffer, instrName); @@ -540,7 +506,8 @@ write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend } \ while (0) -enum { +enum +{ op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3, op_BC = 4, op_BLC = 5, op_LPC = 6, op_JC = 7, op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11, @@ -550,9 +517,7 @@ enum { extern disassemble_info tm_print_insn_info; static int -dsmOneArcInst (addr, state) - bfd_vma addr; - struct arcDisState * state; +dsmOneArcInst (bfd_vma addr, struct arcDisState * state) { int condCodeIsPartOfName = 0; a4_decoding_class decodingClass; @@ -641,7 +606,7 @@ dsmOneArcInst (addr, state) } else { - switch (BITS (state->words[0],10,11)) + switch (BITS (state->words[0], 10, 11)) { case 0: instrName = "ld"; @@ -665,14 +630,14 @@ dsmOneArcInst (addr, state) break; case op_ST: - if (BIT (state->words[0],25)) + if (BIT (state->words[0], 25)) { instrName = "sr"; decodingClass = CLASS_A4_SR; } else { - switch (BITS (state->words[0],22,23)) + switch (BITS (state->words[0], 22, 23)) { case 0: instrName = "st"; @@ -727,7 +692,7 @@ dsmOneArcInst (addr, state) case 0x3f: { decodingClass = CLASS_A4_OP3_SUBOPC3F; - switch( FIELDD (state->words[0]) ) + switch (FIELDD (state->words[0])) { case 0: instrName = "brk"; @@ -822,7 +787,7 @@ dsmOneArcInst (addr, state) case op_XOR: if (state->words[0] == 0x7fffffff) { - /* nop encoded as xor -1, -1, -1 */ + /* NOP encoded as xor -1, -1, -1. */ instrName = "nop"; decodingClass = CLASS_A4_OP3_SUBOPC3F; } @@ -866,7 +831,7 @@ dsmOneArcInst (addr, state) if (!repeatsOp) WRITE_FORMAT_COMMA_x (C); WRITE_NOP_COMMENT (); - my_sprintf (state, state->operandBuffer, formatString, + arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); } else @@ -874,7 +839,7 @@ dsmOneArcInst (addr, state) WRITE_FORMAT_x (B); if (!repeatsOp) WRITE_FORMAT_COMMA_x (C); - my_sprintf (state, state->operandBuffer, formatString, + arc_sprintf (state, state->operandBuffer, formatString, fieldB, fieldC); } write_comments (); @@ -891,13 +856,13 @@ dsmOneArcInst (addr, state) WRITE_FORMAT_x (A); WRITE_FORMAT_COMMA_x (B); WRITE_NOP_COMMENT (); - my_sprintf (state, state->operandBuffer, formatString, + arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB); } else { WRITE_FORMAT_x (B); - my_sprintf (state, state->operandBuffer, formatString, fieldB); + arc_sprintf (state, state->operandBuffer, formatString, fieldB); } write_comments (); break; @@ -905,17 +870,17 @@ dsmOneArcInst (addr, state) case CLASS_A4_FLAG: CHECK_FIELD_B (); CHECK_FLAG_COND_NULLIFY (); - flag = 0; /* this is the FLAG instruction -- it's redundant */ + flag = 0; /* This is the FLAG instruction -- it's redundant. */ write_instr_name (); WRITE_FORMAT_x (B); - my_sprintf (state, state->operandBuffer, formatString, fieldB); + arc_sprintf (state, state->operandBuffer, formatString, fieldB); write_comments (); break; case CLASS_A4_BRANCH: fieldA = BITS (state->words[0],7,26) << 2; - fieldA = (fieldA << 10) >> 10; /* make it signed */ + fieldA = (fieldA << 10) >> 10; /* Make it signed. */ fieldA += addr + 4; CHECK_FLAG_COND_NULLIFY (); flag = 0; @@ -932,8 +897,8 @@ dsmOneArcInst (addr, state) lr dest<- func addr; j [dest]" */ } - strcat (formatString, "%s"); /* address/label name */ - my_sprintf (state, state->operandBuffer, formatString, + strcat (formatString, "%s"); /* Address/label name. */ + arc_sprintf (state, state->operandBuffer, formatString, post_address (state, fieldA)); write_comments (); break; @@ -949,12 +914,12 @@ dsmOneArcInst (addr, state) if (!fieldBisReg) { fieldAisReg = 0; - fieldA = (fieldB >> 25) & 0x7F; /* flags */ + fieldA = (fieldB >> 25) & 0x7F; /* Flags. */ fieldB = (fieldB & 0xFFFFFF) << 2; state->flow = is_linked ? direct_call : direct_jump; add_target (fieldB); - /* screwy JLcc requires .jd mode to execute correctly - * but we pretend it is .nd (no delay slot). */ + /* Screwy JLcc requires .jd mode to execute correctly + but we pretend it is .nd (no delay slot). */ if (is_linked && state->nullifyMode == BR_exec_when_jump) state->nullifyMode = BR_exec_when_no_jump; } @@ -962,24 +927,24 @@ dsmOneArcInst (addr, state) { state->flow = is_linked ? indirect_call : indirect_jump; /* We should also treat this as indirect call if NOT linked - * but the preceding instruction was a "lr blink,[status]" - * and we have a delay slot with "add blink,blink,2". - * For now we can't detect such. */ + but the preceding instruction was a "lr blink,[status]" + and we have a delay slot with "add blink,blink,2". + For now we can't detect such. */ state->register_for_indirect_jump = fieldB; } write_instr_name (); strcat (formatString, - IS_REG (B) ? "[%r]" : "%s"); /* address/label name */ + IS_REG (B) ? "[%r]" : "%s"); /* Address/label name. */ if (fieldA != 0) { fieldAisReg = 0; WRITE_FORMAT_COMMA_x (A); } if (IS_REG (B)) - my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA); + arc_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA); else - my_sprintf (state, state->operandBuffer, formatString, + arc_sprintf (state, state->operandBuffer, formatString, post_address (state, fieldB), fieldA); write_comments (); break; @@ -1005,9 +970,9 @@ dsmOneArcInst (addr, state) state->_offset += fieldC; state->_mem_load = 1; - directMem = BIT (state->words[0],5); - addrWriteBack = BIT (state->words[0],3); - signExtend = BIT (state->words[0],0); + directMem = BIT (state->words[0], 5); + addrWriteBack = BIT (state->words[0], 3); + signExtend = BIT (state->words[0], 0); write_instr_name (); WRITE_FORMAT_x_COMMA_LB(A); @@ -1017,7 +982,7 @@ dsmOneArcInst (addr, state) fieldB = fieldC; WRITE_FORMAT_x_RB (C); - my_sprintf (state, state->operandBuffer, formatString, + arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); write_comments (); break; @@ -1036,7 +1001,7 @@ dsmOneArcInst (addr, state) state->_mem_load = 1; if (fieldBisReg) state->ea_reg1 = fieldB; - /* field B is either a shimm (same as fieldC) or limm (different!) + /* Field B is either a shimm (same as fieldC) or limm (different!) Say ea is not present, so only one of us will do the name lookup. */ else state->_offset += fieldB, state->_ea_present = 0; @@ -1063,7 +1028,7 @@ dsmOneArcInst (addr, state) else WRITE_FORMAT_RB (); } - my_sprintf (state, state->operandBuffer, formatString, + arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); write_comments (); break; @@ -1081,26 +1046,26 @@ dsmOneArcInst (addr, state) state->_offset = fieldA; if (fieldBisReg) state->ea_reg1 = fieldB; - /* field B is either a shimm (same as fieldA) or limm (different!) + /* Field B is either a shimm (same as fieldA) or limm (different!) Say ea is not present, so only one of us will do the name lookup. (for is_limm we do the name translation here). */ else state->_offset += fieldB, state->_ea_present = 0; - directMem = BIT(state->words[0],26); - addrWriteBack = BIT(state->words[0],24); + directMem = BIT (state->words[0], 26); + addrWriteBack = BIT (state->words[0], 24); - write_instr_name(); + write_instr_name (); WRITE_FORMAT_x_COMMA_LB(C); if (!fieldBisReg) { fieldB = state->_offset; - WRITE_FORMAT_x_RB(B); + WRITE_FORMAT_x_RB (B); } else { - WRITE_FORMAT_x(B); + WRITE_FORMAT_x (B); if (fieldBisReg && fieldA != 0) { fieldAisReg = 0; @@ -1109,9 +1074,9 @@ dsmOneArcInst (addr, state) else WRITE_FORMAT_RB(); } - my_sprintf (state, state->operandBuffer, formatString, + arc_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB, fieldA); - write_comments2(fieldA); + write_comments2 (fieldA); break; case CLASS_A4_SR: @@ -1119,37 +1084,36 @@ dsmOneArcInst (addr, state) CHECK_FIELD_B(); CHECK_FIELD_C(); - write_instr_name(); + write_instr_name (); WRITE_FORMAT_x_COMMA_LB(C); /* Try to print B as an aux reg if it is not a core reg. */ usesAuxReg = 1; - WRITE_FORMAT_x(B); - WRITE_FORMAT_RB(); - my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB); - write_comments(); + WRITE_FORMAT_x (B); + WRITE_FORMAT_RB (); + arc_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB); + write_comments (); break; case CLASS_A4_OP3_SUBOPC3F: - write_instr_name(); + write_instr_name (); state->operandBuffer[0] = '\0'; break; case CLASS_A4_LR: /* LR instruction */ - CHECK_FIELD_A(); - CHECK_FIELD_B(); + CHECK_FIELD_A (); + CHECK_FIELD_B (); - write_instr_name(); - WRITE_FORMAT_x_COMMA_LB(A); + write_instr_name (); + WRITE_FORMAT_x_COMMA_LB (A); /* Try to print B as an aux reg if it is not a core reg. */ usesAuxReg = 1; - WRITE_FORMAT_x(B); - WRITE_FORMAT_RB(); - my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB); - write_comments(); + WRITE_FORMAT_x (B); + WRITE_FORMAT_RB (); + arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB); + write_comments (); break; - default: mwerror (state, "Bad decoding class in ARC disassembler"); break; @@ -1161,23 +1125,23 @@ dsmOneArcInst (addr, state) /* Returns the name the user specified core extension register. */ + static const char * -_coreRegName(arg, regval) - void * arg ATTRIBUTE_UNUSED; - int regval; +_coreRegName(void * arg ATTRIBUTE_UNUSED, int regval) { return arcExtMap_coreRegName (regval); } /* Returns the name the user specified AUX extension register. */ + static const char * _auxRegName(void *_this ATTRIBUTE_UNUSED, int regval) { return arcExtMap_auxRegName(regval); } - /* Returns the name the user specified condition code name. */ + static const char * _condCodeName(void *_this ATTRIBUTE_UNUSED, int regval) { @@ -1185,6 +1149,7 @@ _condCodeName(void *_this ATTRIBUTE_UNUSED, int regval) } /* Returns the name the user specified extension instruction. */ + static const char * _instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags) { @@ -1193,15 +1158,15 @@ _instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags) /* Decode an instruction returning the size of the instruction in bytes or zero if unrecognized. */ + static int -decodeInstr (address, info) - bfd_vma address; /* Address of this instruction. */ - disassemble_info * info; +decodeInstr (bfd_vma address, /* Address of this instruction. */ + disassemble_info * info) { int status; bfd_byte buffer[4]; - struct arcDisState s; /* ARC Disassembler state */ - void *stream = info->stream; /* output stream */ + struct arcDisState s; /* ARC Disassembler state. */ + void *stream = info->stream; /* Output stream. */ fprintf_ftype func = info->fprintf_func; int bytes; @@ -1218,9 +1183,9 @@ decodeInstr (address, info) s.words[0] = bfd_getl32(buffer); else s.words[0] = bfd_getb32(buffer); - /* always read second word in case of limm */ + /* Always read second word in case of limm. */ - /* we ignore the result since last insn may not have a limm */ + /* We ignore the result since last insn may not have a limm. */ status = (*info->read_memory_func) (address + 4, buffer, 4, info); if (info->endian == BFD_ENDIAN_LITTLE) s.words[1] = bfd_getl32(buffer); @@ -1233,23 +1198,24 @@ decodeInstr (address, info) s.condCodeName = _condCodeName; s.instName = _instName; - /* disassemble */ - bytes = dsmOneArcInst(address, (void *)&s); + /* Disassemble. */ + bytes = dsmOneArcInst (address, (void *)& s); - /* display the disassembly instruction */ + /* Display the disassembly instruction. */ (*func) (stream, "%08x ", s.words[0]); (*func) (stream, " "); - (*func) (stream, "%-10s ", s.instrBuffer); - if (__TRANSLATION_REQUIRED(s)) + if (__TRANSLATION_REQUIRED (s)) { bfd_vma addr = s.addresses[s.operandBuffer[1] - '0']; + (*info->print_address_func) ((bfd_vma) addr, info); (*func) (stream, "\n"); } else (*func) (stream, "%s",s.operandBuffer); + return s.instructionLen; } |