diff options
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 27f0f78..c7be6d0 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1855,9 +1855,17 @@ struct aarch64_opcode aarch64_opcode_table[] = {"sqrshl", 0x5e205c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE}, {"sqdmulh", 0x5e20b400, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE}, {"fmulx", 0x5e20dc00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE}, + {"fmulx", 0x5e401c00, 0xffe0fc00, asisdsame, 0, SIMD_F16, + OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE}, {"fcmeq", 0x5e20e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE}, + {"fcmeq", 0x5e402400, 0xffe0fc00, asisdsame, 0, SIMD_F16, + OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE}, {"frecps", 0x5e20fc00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE}, + {"frecps", 0x5e403c00, 0xffe0fc00, asisdsame, 0, SIMD_F16, + OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE}, {"frsqrts", 0x5ea0fc00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE}, + {"frsqrts", 0x5ec03c00, 0xffe0fc00, asisdsame, 0, SIMD_F16, + OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE}, {"cmgt", 0x5ee03400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE}, {"cmge", 0x5ee03c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE}, {"sshl", 0x5ee04400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE}, @@ -1870,10 +1878,20 @@ struct aarch64_opcode aarch64_opcode_table[] = {"uqrshl", 0x7e205c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE}, {"sqrdmulh", 0x7e20b400, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE}, {"fcmge", 0x7e20e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE}, + {"fcmge", 0x7e402400, 0xffe0fc00, asisdsame, 0, SIMD_F16, + OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE}, {"facge", 0x7e20ec00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE}, + {"facge", 0x7e402c00, 0xffe0fc00, asisdsame, 0, SIMD_F16, + OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE}, {"fabd", 0x7ea0d400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE}, + {"fabd", 0x7ec01400, 0xffe0fc00, asisdsame, 0, SIMD_F16, + OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE}, {"fcmgt", 0x7ea0e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE}, + {"fcmgt", 0x7ec02400, 0xffe0fc00, asisdsame, 0, SIMD_F16, + OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE}, {"facgt", 0x7ea0ec00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE}, + {"facgt", 0x7ec02c00, 0xffe0fc00, asisdsame, 0, SIMD_F16, + OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE}, {"cmhi", 0x7ee03400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE}, {"cmhs", 0x7ee03c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE}, {"ushl", 0x7ee04400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE}, |