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-rw-r--r--opcodes/aarch64-asm.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 345d599..9294910 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -135,6 +135,13 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
assert (0);
}
}
+ else if (inst->opcode->iclass == cryptosm3)
+ {
+ /* index for e.g. SM3TT2A <Vd>.4S, <Vn>.4S, <Vm>S[<imm2>]. */
+ unsigned reglane_index = info->reglane.index;
+ assert (reglane_index < 4);
+ insert_field (FLD_SM3_imm2, code, reglane_index, 0);
+ }
else
{
/* index for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
@@ -620,6 +627,29 @@ aarch64_ins_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED,
return NULL;
}
+/* Encode the address operand for e.g.
+ stlur <Xt>, [<Xn|SP>{, <amount>}]. */
+const char *
+aarch64_ins_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+ /* Rn */
+ insert_field (self->fields[0], code, info->addr.base_regno, 0);
+
+ /* simm9 */
+ int imm = info->addr.offset.imm;
+ insert_field (self->fields[1], code, imm, 0);
+
+ /* writeback */
+ if (info->addr.writeback)
+ {
+ assert (info->addr.preind == 1 && info->addr.postind == 0);
+ insert_field (self->fields[2], code, 1, 0);
+ }
+ return NULL;
+}
+
/* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>, #<simm>]!. */
const char *
aarch64_ins_addr_simm (const aarch64_operand *self,