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-rw-r--r--ld/ChangeLog6
-rw-r--r--ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp1
-rw-r--r--ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d5
-rw-r--r--ld/testsuite/ld-riscv-elf/pcrel-lo-addend.s17
4 files changed, 29 insertions, 0 deletions
diff --git a/ld/ChangeLog b/ld/ChangeLog
index c8a967a..a1d0049 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,9 @@
+2018-02-15 Jim Wilson <jimw@sifive.com>
+
+ * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run pcrel-lo-addend test.
+ * testsuite/ld-riscv-elf/pcrel-lo-addend.d: New.
+ * testsuite/ld-riscv-elf/pcrel-lo-addend.s: New.
+
2018-02-14 H.J. Lu <hongjiu.lu@intel.com>
PR ld/22842
diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
index 2b6a1d7..cd11680 100644
--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
@@ -22,6 +22,7 @@
if [istarget "riscv*-*-*"] {
run_dump_test "c-lui"
run_dump_test "disas-jalr"
+ run_dump_test "pcrel-lo-addend"
# The following tests require shared library support.
if ![check_shared_lib_support] {
diff --git a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d
new file mode 100644
index 0000000..bd61b4b
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.d
@@ -0,0 +1,5 @@
+#name: %pcrel_lo with an addend
+#source: pcrel-lo-addend.s
+#as: -march=rv32ic
+#ld: -melf32lriscv
+#error: .*dangerous relocation: %pcrel_lo with addend
diff --git a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.s b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.s
new file mode 100644
index 0000000..50cdccc
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend.s
@@ -0,0 +1,17 @@
+ .text
+ .globl _start
+_start:
+ auipc ra, %pcrel_hi(tdata)
+ addi ra, ra, %pcrel_lo(.text)
+ lb t1, 0(ra)
+foo:
+ auipc ra, %pcrel_hi(tdata)
+ addi ra, ra, %pcrel_lo(.text+12)
+ lb t2, 1(ra)
+
+ .data
+tdata:
+ .byte 0xff
+ .byte 0x00
+ .byte 0xf0
+ .byte 0x0f