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-rw-r--r--ld/ChangeLog5
-rw-r--r--ld/testsuite/ld-aarch64/emit-relocs-280.d4
-rw-r--r--ld/testsuite/ld-aarch64/weak-undefined.d12
3 files changed, 13 insertions, 8 deletions
diff --git a/ld/ChangeLog b/ld/ChangeLog
index b9b335d..01c8a04 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,8 @@
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ * testsuite/ld-aarch64/emit-relocs-280.d: Match branch comments.
+ * testsuite/ld-aarch64/weak-undefined.d: Likewise.
+
2016-09-20 Andrew Burgess <andrew.burgess@embecosm.com>
* ld.texinfo (Input Section Basics): Expand the description of
diff --git a/ld/testsuite/ld-aarch64/emit-relocs-280.d b/ld/testsuite/ld-aarch64/emit-relocs-280.d
index 9b954ff..85f5c98 100644
--- a/ld/testsuite/ld-aarch64/emit-relocs-280.d
+++ b/ld/testsuite/ld-aarch64/emit-relocs-280.d
@@ -6,7 +6,7 @@
+10004: 8a000000 and .*
+10008: 8a000000 and .*
+1000c: 8a000000 and .*
- +10010: 54fdff80 b.eq c000 <target>
+ +10010: 54fdff80 b.eq c000 <target> // .*
+10010: R_AARCH64_CONDBR19 target
- +10014: 54fdffe0 b.eq c010 <target\+0x10>
+ +10014: 54fdffe0 b.eq c010 <target\+0x10> // .*
+10014: R_AARCH64_CONDBR19 target\+0x10
diff --git a/ld/testsuite/ld-aarch64/weak-undefined.d b/ld/testsuite/ld-aarch64/weak-undefined.d
index 22a9860..29ba2e5 100644
--- a/ld/testsuite/ld-aarch64/weak-undefined.d
+++ b/ld/testsuite/ld-aarch64/weak-undefined.d
@@ -2,13 +2,13 @@
#ld: -Ttext 0xF0000000 -T relocs.ld -e0 --emit-relocs
#objdump: -d
#...
- +f0000000: 54000001 b\.ne f0000000 <main>
- +f0000004: 54000000 b\.eq f0000004 <main\+0x4>
- +f0000008: 54000002 b\.cs f0000008 <main\+0x8>
- +f000000c: 54000003 b\.cc f000000c <main\+0xc>
+ +f0000000: 54000001 b\.ne f0000000 <main> // .*
+ +f0000004: 54000000 b\.eq f0000004 <main\+0x4> // .*
+ +f0000008: 54000002 b\.cs f0000008 <main\+0x8> // .*
+ +f000000c: 54000003 b\.cc f000000c <main\+0xc> // .*
+f0000010: 5400000c b\.gt f0000010 <main\+0x10>
- +f0000014: 5400000a b\.ge f0000014 <main\+0x14>
- +f0000018: 5400000b b\.lt f0000018 <main\+0x18>
+ +f0000014: 5400000a b\.ge f0000014 <main\+0x14> // .*
+ +f0000018: 5400000b b\.lt f0000018 <main\+0x18> // .*
+f000001c: 5400000d b\.le f000001c <main\+0x1c>
+f0000020: d503201f nop
+f0000024: d503201f nop