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-rw-r--r--ld/testsuite/ChangeLog5
-rw-r--r--ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s2
2 files changed, 6 insertions, 1 deletions
diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index e239ce8..ae0fa89 100644
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2014-04-15 Marcus Shawcroft <marcus.shawcroft@arm.com>
+
+ * ld-aarch64/tls-relax-gdesc-ie.s (var): Adjust test case
+ to include all 5 bits of LDR destination register.
+
2014-04-10 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
* ld-avr/norelax_diff.d: New testcase.
diff --git a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s
index c20690c..38b3721 100644
--- a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s
+++ b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s
@@ -4,7 +4,7 @@ var:
.word 2
.text
adrp x0, :tlsdesc:var
- ldr x1, [x0, #:tlsdesc_lo12:var]
+ ldr x17, [x0, #:tlsdesc_lo12:var]
add x0, x0, :tlsdesc_lo12:var
.tlsdesccall var
blr x1