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-rw-r--r--ld/testsuite/ChangeLog16
-rw-r--r--ld/testsuite/ld-powerpc/tls.d64
-rw-r--r--ld/testsuite/ld-powerpc/tls32.d56
-rw-r--r--ld/testsuite/ld-powerpc/tlsexe.d112
-rw-r--r--ld/testsuite/ld-powerpc/tlsexe32.d56
-rw-r--r--ld/testsuite/ld-powerpc/tlsexetoc.d86
-rw-r--r--ld/testsuite/ld-powerpc/tlsso.d122
-rw-r--r--ld/testsuite/ld-powerpc/tlsso32.d56
-rw-r--r--ld/testsuite/ld-powerpc/tlstoc.d36
-rw-r--r--ld/testsuite/ld-powerpc/tlstocso.d90
10 files changed, 353 insertions, 341 deletions
diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index 9d755d3..3d24b20 100644
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,15 @@
+2004-03-16 Alan Modra <amodra@bigpond.net.au>
+
+ * ld-powerpc/tls.d: Update.
+ * ld-powerpc/tls32.d: Update.
+ * ld-powerpc/tlsexe.d: Update.
+ * ld-powerpc/tlsexe32.d: Update.
+ * ld-powerpc/tlsexetoc.d: Update.
+ * ld-powerpc/tlsso.d: Update.
+ * ld-powerpc/tlsso32.d: Update.
+ * ld-powerpc/tlstoc.d: Update.
+ * ld-powerpc/tlstocso.d: Update.
+
2004-03-05 Nathan Sidwell <nathan@codesourcery.com>
* ld-scripts/size-1.d: Add bigendian regexps.
@@ -58,7 +70,7 @@
relocations.
2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
-
+
* ld-h8300/relax-5.s: New file: Source for relax-5 test.
* ld-h8300/relax-5.d: New file: Expected output and commands for
assembling and linking the relax-5 test.
@@ -83,7 +95,7 @@
ld-arm/arm-static-app.r: New files.
2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
-
+
* ld-h8300/h8300-exp: Run the relax-4 test.
* ld-h8300/relax-4.s: New file: Source for relax-4 test.
* ld-h8300/relax-4.d: New file: Expected output and commands for
diff --git a/ld/testsuite/ld-powerpc/tls.d b/ld/testsuite/ld-powerpc/tls.d
index 621fcb0..abae98a 100644
--- a/ld/testsuite/ld-powerpc/tls.d
+++ b/ld/testsuite/ld-powerpc/tls.d
@@ -10,44 +10,44 @@
Disassembly of section \.text:
0+100000e8 <_start>:
- 100000e8: 3c 6d 00 00 addis r3,r13,0
+ 100000e8: 3c 6d 00 00 addis r3,r13,0
100000ec: 60 00 00 00 nop
- 100000f0: 38 63 90 78 addi r3,r3,-28552
- 100000f4: 3c 6d 00 00 addis r3,r13,0
+ 100000f0: 38 63 90 78 addi r3,r3,-28552
+ 100000f4: 3c 6d 00 00 addis r3,r13,0
100000f8: 60 00 00 00 nop
- 100000fc: 38 63 10 00 addi r3,r3,4096
- 10000100: 3c 6d 00 00 addis r3,r13,0
+ 100000fc: 38 63 10 00 addi r3,r3,4096
+ 10000100: 3c 6d 00 00 addis r3,r13,0
10000104: 60 00 00 00 nop
- 10000108: 38 63 90 40 addi r3,r3,-28608
- 1000010c: 3c 6d 00 00 addis r3,r13,0
+ 10000108: 38 63 90 40 addi r3,r3,-28608
+ 1000010c: 3c 6d 00 00 addis r3,r13,0
10000110: 60 00 00 00 nop
- 10000114: 38 63 10 00 addi r3,r3,4096
- 10000118: 39 23 80 48 addi r9,r3,-32696
- 1000011c: 3d 23 00 00 addis r9,r3,0
- 10000120: 81 49 80 50 lwz r10,-32688\(r9\)
- 10000124: e9 22 80 10 ld r9,-32752\(r2\)
- 10000128: 7d 49 18 2a ldx r10,r9,r3
- 1000012c: 3d 2d 00 00 addis r9,r13,0
- 10000130: a1 49 90 60 lhz r10,-28576\(r9\)
- 10000134: 89 4d 90 68 lbz r10,-28568\(r13\)
- 10000138: 3d 2d 00 00 addis r9,r13,0
- 1000013c: 99 49 90 70 stb r10,-28560\(r9\)
- 10000140: 3c 6d 00 00 addis r3,r13,0
+ 10000114: 38 63 10 00 addi r3,r3,4096
+ 10000118: 39 23 80 48 addi r9,r3,-32696
+ 1000011c: 3d 23 00 00 addis r9,r3,0
+ 10000120: 81 49 80 50 lwz r10,-32688\(r9\)
+ 10000124: e9 22 80 10 ld r9,-32752\(r2\)
+ 10000128: 7d 49 18 2a ldx r10,r9,r3
+ 1000012c: 3d 2d 00 00 addis r9,r13,0
+ 10000130: a1 49 90 60 lhz r10,-28576\(r9\)
+ 10000134: 89 4d 90 68 lbz r10,-28568\(r13\)
+ 10000138: 3d 2d 00 00 addis r9,r13,0
+ 1000013c: 99 49 90 70 stb r10,-28560\(r9\)
+ 10000140: 3c 6d 00 00 addis r3,r13,0
10000144: 60 00 00 00 nop
- 10000148: 38 63 90 00 addi r3,r3,-28672
- 1000014c: 3c 6d 00 00 addis r3,r13,0
+ 10000148: 38 63 90 00 addi r3,r3,-28672
+ 1000014c: 3c 6d 00 00 addis r3,r13,0
10000150: 60 00 00 00 nop
- 10000154: 38 63 10 00 addi r3,r3,4096
- 10000158: f9 43 80 08 std r10,-32760\(r3\)
- 1000015c: 3d 23 00 00 addis r9,r3,0
- 10000160: 91 49 80 10 stw r10,-32752\(r9\)
- 10000164: e9 22 80 08 ld r9,-32760\(r2\)
- 10000168: 7d 49 19 2a stdx r10,r9,r3
- 1000016c: 3d 2d 00 00 addis r9,r13,0
- 10000170: b1 49 90 60 sth r10,-28576\(r9\)
- 10000174: e9 4d 90 2a lwa r10,-28632\(r13\)
- 10000178: 3d 2d 00 00 addis r9,r13,0
- 1000017c: a9 49 90 30 lha r10,-28624\(r9\)
+ 10000154: 38 63 10 00 addi r3,r3,4096
+ 10000158: f9 43 80 08 std r10,-32760\(r3\)
+ 1000015c: 3d 23 00 00 addis r9,r3,0
+ 10000160: 91 49 80 10 stw r10,-32752\(r9\)
+ 10000164: e9 22 80 08 ld r9,-32760\(r2\)
+ 10000168: 7d 49 19 2a stdx r10,r9,r3
+ 1000016c: 3d 2d 00 00 addis r9,r13,0
+ 10000170: b1 49 90 60 sth r10,-28576\(r9\)
+ 10000174: e9 4d 90 2a lwa r10,-28632\(r13\)
+ 10000178: 3d 2d 00 00 addis r9,r13,0
+ 1000017c: a9 49 90 30 lha r10,-28624\(r9\)
0+10000180 <\.__tls_get_addr>:
10000180: 4e 80 00 20 blr
diff --git a/ld/testsuite/ld-powerpc/tls32.d b/ld/testsuite/ld-powerpc/tls32.d
index b2e384d..86fe04a 100644
--- a/ld/testsuite/ld-powerpc/tls32.d
+++ b/ld/testsuite/ld-powerpc/tls32.d
@@ -10,34 +10,34 @@
Disassembly of section \.text:
0+1800094 <_start>:
- 1800094: 3c 62 00 00 addis r3,r2,0
- 1800098: 38 63 90 3c addi r3,r3,-28612
- 180009c: 3c 62 00 00 addis r3,r2,0
- 18000a0: 38 63 10 00 addi r3,r3,4096
- 18000a4: 3c 62 00 00 addis r3,r2,0
- 18000a8: 38 63 90 20 addi r3,r3,-28640
- 18000ac: 3c 62 00 00 addis r3,r2,0
- 18000b0: 38 63 10 00 addi r3,r3,4096
- 18000b4: 39 23 80 24 addi r9,r3,-32732
- 18000b8: 3d 23 00 00 addis r9,r3,0
- 18000bc: 81 49 80 28 lwz r10,-32728\(r9\)
- 18000c0: 3d 22 00 00 addis r9,r2,0
- 18000c4: a1 49 90 30 lhz r10,-28624\(r9\)
- 18000c8: 89 42 90 34 lbz r10,-28620\(r2\)
- 18000cc: 3d 22 00 00 addis r9,r2,0
- 18000d0: 99 49 90 38 stb r10,-28616\(r9\)
- 18000d4: 3c 62 00 00 addis r3,r2,0
- 18000d8: 38 63 90 00 addi r3,r3,-28672
- 18000dc: 3c 62 00 00 addis r3,r2,0
- 18000e0: 38 63 10 00 addi r3,r3,4096
- 18000e4: 91 43 80 04 stw r10,-32764\(r3\)
- 18000e8: 3d 23 00 00 addis r9,r3,0
- 18000ec: 91 49 80 08 stw r10,-32760\(r9\)
- 18000f0: 3d 22 00 00 addis r9,r2,0
- 18000f4: b1 49 90 30 sth r10,-28624\(r9\)
- 18000f8: a1 42 90 14 lhz r10,-28652\(r2\)
- 18000fc: 3d 22 00 00 addis r9,r2,0
- 1800100: a9 49 90 18 lha r10,-28648\(r9\)
+ 1800094: 3c 62 00 00 addis r3,r2,0
+ 1800098: 38 63 90 3c addi r3,r3,-28612
+ 180009c: 3c 62 00 00 addis r3,r2,0
+ 18000a0: 38 63 10 00 addi r3,r3,4096
+ 18000a4: 3c 62 00 00 addis r3,r2,0
+ 18000a8: 38 63 90 20 addi r3,r3,-28640
+ 18000ac: 3c 62 00 00 addis r3,r2,0
+ 18000b0: 38 63 10 00 addi r3,r3,4096
+ 18000b4: 39 23 80 24 addi r9,r3,-32732
+ 18000b8: 3d 23 00 00 addis r9,r3,0
+ 18000bc: 81 49 80 28 lwz r10,-32728\(r9\)
+ 18000c0: 3d 22 00 00 addis r9,r2,0
+ 18000c4: a1 49 90 30 lhz r10,-28624\(r9\)
+ 18000c8: 89 42 90 34 lbz r10,-28620\(r2\)
+ 18000cc: 3d 22 00 00 addis r9,r2,0
+ 18000d0: 99 49 90 38 stb r10,-28616\(r9\)
+ 18000d4: 3c 62 00 00 addis r3,r2,0
+ 18000d8: 38 63 90 00 addi r3,r3,-28672
+ 18000dc: 3c 62 00 00 addis r3,r2,0
+ 18000e0: 38 63 10 00 addi r3,r3,4096
+ 18000e4: 91 43 80 04 stw r10,-32764\(r3\)
+ 18000e8: 3d 23 00 00 addis r9,r3,0
+ 18000ec: 91 49 80 08 stw r10,-32760\(r9\)
+ 18000f0: 3d 22 00 00 addis r9,r2,0
+ 18000f4: b1 49 90 30 sth r10,-28624\(r9\)
+ 18000f8: a1 42 90 14 lhz r10,-28652\(r2\)
+ 18000fc: 3d 22 00 00 addis r9,r2,0
+ 1800100: a9 49 90 18 lha r10,-28648\(r9\)
0+1800104 <__tls_get_addr>:
1800104: 4e 80 00 20 blr
diff --git a/ld/testsuite/ld-powerpc/tlsexe.d b/ld/testsuite/ld-powerpc/tlsexe.d
index 6dac928..546daf3 100644
--- a/ld/testsuite/ld-powerpc/tlsexe.d
+++ b/ld/testsuite/ld-powerpc/tlsexe.d
@@ -9,68 +9,68 @@
Disassembly of section \.text:
.* <_start-0x1c>:
-.* 3d 82 00 00 addis r12,r2,0
-.* f8 41 00 28 std r2,40\(r1\)
-.* e9 6c 80 48 ld r11,-32696\(r12\)
-.* e8 4c 80 50 ld r2,-32688\(r12\)
-.* 7d 69 03 a6 mtctr r11
-.* e9 6c 80 58 ld r11,-32680\(r12\)
+.* 3d 82 00 00 addis r12,r2,0
+.* f8 41 00 28 std r2,40\(r1\)
+.* e9 6c 80 48 ld r11,-32696\(r12\)
+.* e8 4c 80 50 ld r2,-32688\(r12\)
+.* 7d 69 03 a6 mtctr r11
+.* e9 6c 80 58 ld r11,-32680\(r12\)
.* 4e 80 04 20 bctr
.* <_start>:
-.* e8 62 80 10 ld r3,-32752\(r2\)
+.* e8 62 80 10 ld r3,-32752\(r2\)
.* 60 00 00 00 nop
-.* 7c 63 6a 14 add r3,r3,r13
-.* 38 62 80 18 addi r3,r2,-32744
-.* 4b ff ff d5 bl .*
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 3c 6d 00 00 addis r3,r13,0
+.* 7c 63 6a 14 add r3,r3,r13
+.* 38 62 80 18 addi r3,r2,-32744
+.* 4b ff ff d5 bl .*
+.* e8 41 00 28 ld r2,40\(r1\)
+.* 3c 6d 00 00 addis r3,r13,0
.* 60 00 00 00 nop
-.* 38 63 90 38 addi r3,r3,-28616
-.* 3c 6d 00 00 addis r3,r13,0
+.* 38 63 90 38 addi r3,r3,-28616
+.* 3c 6d 00 00 addis r3,r13,0
.* 60 00 00 00 nop
-.* 38 63 10 00 addi r3,r3,4096
-.* 39 23 80 40 addi r9,r3,-32704
-.* 3d 23 00 00 addis r9,r3,0
-.* 81 49 80 48 lwz r10,-32696\(r9\)
-.* e9 22 80 28 ld r9,-32728\(r2\)
-.* 7d 49 18 2a ldx r10,r9,r3
-.* 3d 2d 00 00 addis r9,r13,0
-.* a1 49 90 58 lhz r10,-28584\(r9\)
-.* 89 4d 90 60 lbz r10,-28576\(r13\)
-.* 3d 2d 00 00 addis r9,r13,0
-.* 99 49 90 68 stb r10,-28568\(r9\)
-.* 3c 6d 00 00 addis r3,r13,0
+.* 38 63 10 00 addi r3,r3,4096
+.* 39 23 80 40 addi r9,r3,-32704
+.* 3d 23 00 00 addis r9,r3,0
+.* 81 49 80 48 lwz r10,-32696\(r9\)
+.* e9 22 80 28 ld r9,-32728\(r2\)
+.* 7d 49 18 2a ldx r10,r9,r3
+.* 3d 2d 00 00 addis r9,r13,0
+.* a1 49 90 58 lhz r10,-28584\(r9\)
+.* 89 4d 90 60 lbz r10,-28576\(r13\)
+.* 3d 2d 00 00 addis r9,r13,0
+.* 99 49 90 68 stb r10,-28568\(r9\)
+.* 3c 6d 00 00 addis r3,r13,0
.* 60 00 00 00 nop
-.* 38 63 90 00 addi r3,r3,-28672
-.* 3c 6d 00 00 addis r3,r13,0
+.* 38 63 90 00 addi r3,r3,-28672
+.* 3c 6d 00 00 addis r3,r13,0
.* 60 00 00 00 nop
-.* 38 63 10 00 addi r3,r3,4096
-.* f9 43 80 08 std r10,-32760\(r3\)
-.* 3d 23 00 00 addis r9,r3,0
-.* 91 49 80 10 stw r10,-32752\(r9\)
-.* e9 22 80 08 ld r9,-32760\(r2\)
-.* 7d 49 19 2a stdx r10,r9,r3
-.* 3d 2d 00 00 addis r9,r13,0
-.* b1 49 90 58 sth r10,-28584\(r9\)
-.* e9 4d 90 2a lwa r10,-28632\(r13\)
-.* 3d 2d 00 00 addis r9,r13,0
-.* a9 49 90 30 lha r10,-28624\(r9\)
-.* 7d 89 02 a6 mfctr r12
-.* 78 0b 1f 24 rldicr r11,r0,3,60
-.* 34 40 80 00 addic\. r2,r0,-32768
-.* 7d 8b 60 50 subf r12,r11,r12
-.* 7c 42 fe 76 sradi r2,r2,63
-.* 78 0b 17 64 rldicr r11,r0,2,61
-.* 7c 42 58 38 and r2,r2,r11
-.* 7d 8b 60 50 subf r12,r11,r12
-.* 7d 8c 12 14 add r12,r12,r2
-.* 3d 8c 00 01 addis r12,r12,1
-.* e9 6c 01 c4 ld r11,452\(r12\)
-.* 39 8c 01 c4 addi r12,r12,452
-.* e8 4c 00 08 ld r2,8\(r12\)
-.* 7d 69 03 a6 mtctr r11
-.* e9 6c 00 10 ld r11,16\(r12\)
+.* 38 63 10 00 addi r3,r3,4096
+.* f9 43 80 08 std r10,-32760\(r3\)
+.* 3d 23 00 00 addis r9,r3,0
+.* 91 49 80 10 stw r10,-32752\(r9\)
+.* e9 22 80 08 ld r9,-32760\(r2\)
+.* 7d 49 19 2a stdx r10,r9,r3
+.* 3d 2d 00 00 addis r9,r13,0
+.* b1 49 90 58 sth r10,-28584\(r9\)
+.* e9 4d 90 2a lwa r10,-28632\(r13\)
+.* 3d 2d 00 00 addis r9,r13,0
+.* a9 49 90 30 lha r10,-28624\(r9\)
+.* 7d 89 02 a6 mfctr r12
+.* 78 0b 1f 24 rldicr r11,r0,3,60
+.* 34 40 80 00 addic\. r2,r0,-32768
+.* 7d 8b 60 50 subf r12,r11,r12
+.* 7c 42 fe 76 sradi r2,r2,63
+.* 78 0b 17 64 rldicr r11,r0,2,61
+.* 7c 42 58 38 and r2,r2,r11
+.* 7d 8b 60 50 subf r12,r11,r12
+.* 7d 8c 12 14 add r12,r12,r2
+.* 3d 8c 00 01 addis r12,r12,1
+.* e9 6c 01 c4 ld r11,452\(r12\)
+.* 39 8c 01 c4 addi r12,r12,452
+.* e8 4c 00 08 ld r2,8\(r12\)
+.* 7d 69 03 a6 mtctr r11
+.* e9 6c 00 10 ld r11,16\(r12\)
.* 4e 80 04 20 bctr
-.* 38 00 00 00 li r0,0
-.* 4b ff ff bc b .*
+.* 38 00 00 00 li r0,0
+.* 4b ff ff bc b .*
diff --git a/ld/testsuite/ld-powerpc/tlsexe32.d b/ld/testsuite/ld-powerpc/tlsexe32.d
index 9bd8221..4aea8f0 100644
--- a/ld/testsuite/ld-powerpc/tlsexe32.d
+++ b/ld/testsuite/ld-powerpc/tlsexe32.d
@@ -9,34 +9,34 @@
Disassembly of section \.text:
0180028c <_start>:
- 180028c: 80 7f 00 0c lwz r3,12\(r31\)
- 1800290: 7c 63 12 14 add r3,r3,r2
- 1800294: 38 7f 00 10 addi r3,r31,16
- 1800298: 48 01 01 85 bl 181041c .*
- 180029c: 3c 62 00 00 addis r3,r2,0
- 18002a0: 38 63 90 1c addi r3,r3,-28644
- 18002a4: 3c 62 00 00 addis r3,r2,0
- 18002a8: 38 63 10 00 addi r3,r3,4096
- 18002ac: 39 23 80 20 addi r9,r3,-32736
- 18002b0: 3d 23 00 00 addis r9,r3,0
- 18002b4: 81 49 80 24 lwz r10,-32732\(r9\)
- 18002b8: 3d 22 00 00 addis r9,r2,0
- 18002bc: a1 49 90 2c lhz r10,-28628\(r9\)
- 18002c0: 89 42 90 30 lbz r10,-28624\(r2\)
- 18002c4: 3d 22 00 00 addis r9,r2,0
- 18002c8: 99 49 90 34 stb r10,-28620\(r9\)
- 18002cc: 3c 62 00 00 addis r3,r2,0
- 18002d0: 38 63 90 00 addi r3,r3,-28672
- 18002d4: 3c 62 00 00 addis r3,r2,0
- 18002d8: 38 63 10 00 addi r3,r3,4096
- 18002dc: 91 43 80 04 stw r10,-32764\(r3\)
- 18002e0: 3d 23 00 00 addis r9,r3,0
- 18002e4: 91 49 80 08 stw r10,-32760\(r9\)
- 18002e8: 3d 22 00 00 addis r9,r2,0
- 18002ec: b1 49 90 2c sth r10,-28628\(r9\)
- 18002f0: a1 42 90 14 lhz r10,-28652\(r2\)
- 18002f4: 3d 22 00 00 addis r9,r2,0
- 18002f8: a9 49 90 18 lha r10,-28648\(r9\)
+ 180028c: 80 7f 00 0c lwz r3,12\(r31\)
+ 1800290: 7c 63 12 14 add r3,r3,r2
+ 1800294: 38 7f 00 10 addi r3,r31,16
+ 1800298: 48 01 01 85 bl 181041c .*
+ 180029c: 3c 62 00 00 addis r3,r2,0
+ 18002a0: 38 63 90 1c addi r3,r3,-28644
+ 18002a4: 3c 62 00 00 addis r3,r2,0
+ 18002a8: 38 63 10 00 addi r3,r3,4096
+ 18002ac: 39 23 80 20 addi r9,r3,-32736
+ 18002b0: 3d 23 00 00 addis r9,r3,0
+ 18002b4: 81 49 80 24 lwz r10,-32732\(r9\)
+ 18002b8: 3d 22 00 00 addis r9,r2,0
+ 18002bc: a1 49 90 2c lhz r10,-28628\(r9\)
+ 18002c0: 89 42 90 30 lbz r10,-28624\(r2\)
+ 18002c4: 3d 22 00 00 addis r9,r2,0
+ 18002c8: 99 49 90 34 stb r10,-28620\(r9\)
+ 18002cc: 3c 62 00 00 addis r3,r2,0
+ 18002d0: 38 63 90 00 addi r3,r3,-28672
+ 18002d4: 3c 62 00 00 addis r3,r2,0
+ 18002d8: 38 63 10 00 addi r3,r3,4096
+ 18002dc: 91 43 80 04 stw r10,-32764\(r3\)
+ 18002e0: 3d 23 00 00 addis r9,r3,0
+ 18002e4: 91 49 80 08 stw r10,-32760\(r9\)
+ 18002e8: 3d 22 00 00 addis r9,r2,0
+ 18002ec: b1 49 90 2c sth r10,-28628\(r9\)
+ 18002f0: a1 42 90 14 lhz r10,-28652\(r2\)
+ 18002f4: 3d 22 00 00 addis r9,r2,0
+ 18002f8: a9 49 90 18 lha r10,-28648\(r9\)
Disassembly of section \.got:
018103b8 <\.got>:
diff --git a/ld/testsuite/ld-powerpc/tlsexetoc.d b/ld/testsuite/ld-powerpc/tlsexetoc.d
index 7947149..7ec07d2 100644
--- a/ld/testsuite/ld-powerpc/tlsexetoc.d
+++ b/ld/testsuite/ld-powerpc/tlsexetoc.d
@@ -9,52 +9,52 @@
Disassembly of section \.text:
.* <_start-0x1c>:
-.* 3d 82 00 00 addis r12,r2,0
-.* f8 41 00 28 std r2,40\(r1\)
-.* e9 6c 80 70 ld r11,-32656\(r12\)
-.* e8 4c 80 78 ld r2,-32648\(r12\)
-.* 7d 69 03 a6 mtctr r11
-.* e9 6c 80 80 ld r11,-32640\(r12\)
+.* 3d 82 00 00 addis r12,r2,0
+.* f8 41 00 28 std r2,40\(r1\)
+.* e9 6c 80 70 ld r11,-32656\(r12\)
+.* e8 4c 80 78 ld r2,-32648\(r12\)
+.* 7d 69 03 a6 mtctr r11
+.* e9 6c 80 80 ld r11,-32640\(r12\)
.* 4e 80 04 20 bctr
.* <_start>:
-.* 38 62 80 08 addi r3,r2,-32760
-.* 4b ff ff e1 bl .*
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 38 62 80 18 addi r3,r2,-32744
-.* 4b ff ff d5 bl .*
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 3c 6d 00 00 addis r3,r13,0
+.* 38 62 80 08 addi r3,r2,-32760
+.* 4b ff ff e1 bl .*
+.* e8 41 00 28 ld r2,40\(r1\)
+.* 38 62 80 18 addi r3,r2,-32744
+.* 4b ff ff d5 bl .*
+.* e8 41 00 28 ld r2,40\(r1\)
+.* 3c 6d 00 00 addis r3,r13,0
.* 60 00 00 00 nop
-.* 38 63 90 38 addi r3,r3,-28616
-.* 3c 6d 00 00 addis r3,r13,0
+.* 38 63 90 38 addi r3,r3,-28616
+.* 3c 6d 00 00 addis r3,r13,0
.* 60 00 00 00 nop
-.* 38 63 10 00 addi r3,r3,4096
-.* 39 23 80 40 addi r9,r3,-32704
-.* 3d 23 00 00 addis r9,r3,0
-.* 81 49 80 48 lwz r10,-32696\(r9\)
-.* e9 22 80 48 ld r9,-32696\(r2\)
-.* 7d 49 18 2a ldx r10,r9,r3
-.* 3d 2d 00 00 addis r9,r13,0
-.* a1 49 90 58 lhz r10,-28584\(r9\)
-.* 89 4d 90 60 lbz r10,-28576\(r13\)
-.* 3d 2d 00 00 addis r9,r13,0
-.* 99 49 90 68 stb r10,-28568\(r9\)
-.* 7d 89 02 a6 mfctr r12
-.* 78 0b 1f 24 rldicr r11,r0,3,60
-.* 34 40 80 00 addic\. r2,r0,-32768
-.* 7d 8b 60 50 subf r12,r11,r12
-.* 7c 42 fe 76 sradi r2,r2,63
-.* 78 0b 17 64 rldicr r11,r0,2,61
-.* 7c 42 58 38 and r2,r2,r11
-.* 7d 8b 60 50 subf r12,r11,r12
-.* 7d 8c 12 14 add r12,r12,r2
-.* 3d 8c 00 01 addis r12,r12,1
-.* e9 6c 01 ec ld r11,492\(r12\)
-.* 39 8c 01 ec addi r12,r12,492
-.* e8 4c 00 08 ld r2,8\(r12\)
-.* 7d 69 03 a6 mtctr r11
-.* e9 6c 00 10 ld r11,16\(r12\)
+.* 38 63 10 00 addi r3,r3,4096
+.* 39 23 80 40 addi r9,r3,-32704
+.* 3d 23 00 00 addis r9,r3,0
+.* 81 49 80 48 lwz r10,-32696\(r9\)
+.* e9 22 80 48 ld r9,-32696\(r2\)
+.* 7d 49 18 2a ldx r10,r9,r3
+.* 3d 2d 00 00 addis r9,r13,0
+.* a1 49 90 58 lhz r10,-28584\(r9\)
+.* 89 4d 90 60 lbz r10,-28576\(r13\)
+.* 3d 2d 00 00 addis r9,r13,0
+.* 99 49 90 68 stb r10,-28568\(r9\)
+.* 7d 89 02 a6 mfctr r12
+.* 78 0b 1f 24 rldicr r11,r0,3,60
+.* 34 40 80 00 addic\. r2,r0,-32768
+.* 7d 8b 60 50 subf r12,r11,r12
+.* 7c 42 fe 76 sradi r2,r2,63
+.* 78 0b 17 64 rldicr r11,r0,2,61
+.* 7c 42 58 38 and r2,r2,r11
+.* 7d 8b 60 50 subf r12,r11,r12
+.* 7d 8c 12 14 add r12,r12,r2
+.* 3d 8c 00 01 addis r12,r12,1
+.* e9 6c 01 ec ld r11,492\(r12\)
+.* 39 8c 01 ec addi r12,r12,492
+.* e8 4c 00 08 ld r2,8\(r12\)
+.* 7d 69 03 a6 mtctr r11
+.* e9 6c 00 10 ld r11,16\(r12\)
.* 4e 80 04 20 bctr
-.* 38 00 00 00 li r0,0
-.* 4b ff ff bc b .*
+.* 38 00 00 00 li r0,0
+.* 4b ff ff bc b .*
diff --git a/ld/testsuite/ld-powerpc/tlsso.d b/ld/testsuite/ld-powerpc/tlsso.d
index 5f13b04..dc4ae18 100644
--- a/ld/testsuite/ld-powerpc/tlsso.d
+++ b/ld/testsuite/ld-powerpc/tlsso.d
@@ -9,68 +9,68 @@
Disassembly of section \.text:
.* <\.__tls_get_addr>:
-.* 3d 82 00 00 addis r12,r2,0
-.* f8 41 00 28 std r2,40\(r1\)
-.* e9 6c 80 78 ld r11,-32648\(r12\)
-.* e8 4c 80 80 ld r2,-32640\(r12\)
-.* 7d 69 03 a6 mtctr r11
-.* e9 6c 80 88 ld r11,-32632\(r12\)
+.* 3d 82 00 00 addis r12,r2,0
+.* f8 41 00 28 std r2,40\(r1\)
+.* e9 6c 80 78 ld r11,-32648\(r12\)
+.* e8 4c 80 80 ld r2,-32640\(r12\)
+.* 7d 69 03 a6 mtctr r11
+.* e9 6c 80 88 ld r11,-32632\(r12\)
.* 4e 80 04 20 bctr
.* <_start>:
-.* 38 62 80 30 addi r3,r2,-32720
-.* 4b ff ff e1 bl .* <\.__tls_get_addr>
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 38 62 80 08 addi r3,r2,-32760
-.* 4b ff ff d5 bl .* <\.__tls_get_addr>
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 38 62 80 48 addi r3,r2,-32696
-.* 4b ff ff c9 bl .* <\.__tls_get_addr>
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 38 62 80 08 addi r3,r2,-32760
-.* 4b ff ff bd bl .* <\.__tls_get_addr>
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 39 23 80 40 addi r9,r3,-32704
-.* 3d 23 00 00 addis r9,r3,0
-.* 81 49 80 48 lwz r10,-32696\(r9\)
-.* e9 22 80 40 ld r9,-32704\(r2\)
-.* 7d 49 18 2a ldx r10,r9,r3
-.* e9 22 80 58 ld r9,-32680\(r2\)
-.* 7d 49 6a 2e lhzx r10,r9,r13
-.* 89 4d 00 00 lbz r10,0\(r13\)
-.* 3d 2d 00 00 addis r9,r13,0
-.* 99 49 00 00 stb r10,0\(r9\)
-.* 38 62 80 18 addi r3,r2,-32744
-.* 4b ff ff 89 bl .* <\.__tls_get_addr>
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 38 62 80 08 addi r3,r2,-32760
-.* 4b ff ff 7d bl .* <\.__tls_get_addr>
-.* e8 41 00 28 ld r2,40\(r1\)
-.* f9 43 80 08 std r10,-32760\(r3\)
-.* 3d 23 00 00 addis r9,r3,0
-.* 91 49 80 10 stw r10,-32752\(r9\)
-.* e9 22 80 28 ld r9,-32728\(r2\)
-.* 7d 49 19 2a stdx r10,r9,r3
-.* e9 22 80 58 ld r9,-32680\(r2\)
-.* 7d 49 6b 2e sthx r10,r9,r13
-.* e9 4d 00 02 lwa r10,0\(r13\)
-.* 3d 2d 00 00 addis r9,r13,0
-.* a9 49 00 00 lha r10,0\(r9\)
-.* 7d 89 02 a6 mfctr r12
-.* 78 0b 1f 24 rldicr r11,r0,3,60
-.* 34 40 80 00 addic\. r2,r0,-32768
-.* 7d 8b 60 50 subf r12,r11,r12
-.* 7c 42 fe 76 sradi r2,r2,63
-.* 78 0b 17 64 rldicr r11,r0,2,61
-.* 7c 42 58 38 and r2,r2,r11
-.* 7d 8b 60 50 subf r12,r11,r12
-.* 7d 8c 12 14 add r12,r12,r2
-.* 3d 8c 00 01 addis r12,r12,1
-.* e9 6c 01 f4 ld r11,500\(r12\)
-.* 39 8c 01 f4 addi r12,r12,500
-.* e8 4c 00 08 ld r2,8\(r12\)
-.* 7d 69 03 a6 mtctr r11
-.* e9 6c 00 10 ld r11,16\(r12\)
+.* 38 62 80 30 addi r3,r2,-32720
+.* 4b ff ff e1 bl .* <\.__tls_get_addr>
+.* e8 41 00 28 ld r2,40\(r1\)
+.* 38 62 80 08 addi r3,r2,-32760
+.* 4b ff ff d5 bl .* <\.__tls_get_addr>
+.* e8 41 00 28 ld r2,40\(r1\)
+.* 38 62 80 48 addi r3,r2,-32696
+.* 4b ff ff c9 bl .* <\.__tls_get_addr>
+.* e8 41 00 28 ld r2,40\(r1\)
+.* 38 62 80 08 addi r3,r2,-32760
+.* 4b ff ff bd bl .* <\.__tls_get_addr>
+.* e8 41 00 28 ld r2,40\(r1\)
+.* 39 23 80 40 addi r9,r3,-32704
+.* 3d 23 00 00 addis r9,r3,0
+.* 81 49 80 48 lwz r10,-32696\(r9\)
+.* e9 22 80 40 ld r9,-32704\(r2\)
+.* 7d 49 18 2a ldx r10,r9,r3
+.* e9 22 80 58 ld r9,-32680\(r2\)
+.* 7d 49 6a 2e lhzx r10,r9,r13
+.* 89 4d 00 00 lbz r10,0\(r13\)
+.* 3d 2d 00 00 addis r9,r13,0
+.* 99 49 00 00 stb r10,0\(r9\)
+.* 38 62 80 18 addi r3,r2,-32744
+.* 4b ff ff 89 bl .* <\.__tls_get_addr>
+.* e8 41 00 28 ld r2,40\(r1\)
+.* 38 62 80 08 addi r3,r2,-32760
+.* 4b ff ff 7d bl .* <\.__tls_get_addr>
+.* e8 41 00 28 ld r2,40\(r1\)
+.* f9 43 80 08 std r10,-32760\(r3\)
+.* 3d 23 00 00 addis r9,r3,0
+.* 91 49 80 10 stw r10,-32752\(r9\)
+.* e9 22 80 28 ld r9,-32728\(r2\)
+.* 7d 49 19 2a stdx r10,r9,r3
+.* e9 22 80 58 ld r9,-32680\(r2\)
+.* 7d 49 6b 2e sthx r10,r9,r13
+.* e9 4d 00 02 lwa r10,0\(r13\)
+.* 3d 2d 00 00 addis r9,r13,0
+.* a9 49 00 00 lha r10,0\(r9\)
+.* 7d 89 02 a6 mfctr r12
+.* 78 0b 1f 24 rldicr r11,r0,3,60
+.* 34 40 80 00 addic\. r2,r0,-32768
+.* 7d 8b 60 50 subf r12,r11,r12
+.* 7c 42 fe 76 sradi r2,r2,63
+.* 78 0b 17 64 rldicr r11,r0,2,61
+.* 7c 42 58 38 and r2,r2,r11
+.* 7d 8b 60 50 subf r12,r11,r12
+.* 7d 8c 12 14 add r12,r12,r2
+.* 3d 8c 00 01 addis r12,r12,1
+.* e9 6c 01 f4 ld r11,500\(r12\)
+.* 39 8c 01 f4 addi r12,r12,500
+.* e8 4c 00 08 ld r2,8\(r12\)
+.* 7d 69 03 a6 mtctr r11
+.* e9 6c 00 10 ld r11,16\(r12\)
.* 4e 80 04 20 bctr
-.* 38 00 00 00 li r0,0
-.* 4b ff ff bc b .*
+.* 38 00 00 00 li r0,0
+.* 4b ff ff bc b .*
diff --git a/ld/testsuite/ld-powerpc/tlsso32.d b/ld/testsuite/ld-powerpc/tlsso32.d
index 1e9ba31..3cf6a76 100644
--- a/ld/testsuite/ld-powerpc/tlsso32.d
+++ b/ld/testsuite/ld-powerpc/tlsso32.d
@@ -9,34 +9,34 @@
Disassembly of section \.text:
0+538 <_start>:
- 538: 38 7f 00 1c addi r3,r31,28
- 53c: 48 00 00 01 bl 53c .*
- 540: 38 7f 00 0c addi r3,r31,12
- 544: 48 00 00 01 bl 544 .*
- 548: 38 7f 00 24 addi r3,r31,36
- 54c: 48 01 01 95 bl 106e0 .*
- 550: 38 7f 00 0c addi r3,r31,12
- 554: 48 01 01 8d bl 106e0 .*
- 558: 39 23 80 20 addi r9,r3,-32736
- 55c: 3d 23 00 00 addis r9,r3,0
- 560: 81 49 80 24 lwz r10,-32732\(r9\)
- 564: 81 3f 00 2c lwz r9,44\(r31\)
- 568: 7d 49 12 2e lhzx r10,r9,r2
- 56c: 89 42 00 00 lbz r10,0\(r2\)
- 570: 3d 22 00 00 addis r9,r2,0
- 574: 99 49 00 00 stb r10,0\(r9\)
- 578: 38 7e 00 14 addi r3,r30,20
- 57c: 48 00 00 01 bl 57c .*
- 580: 38 7e 00 0c addi r3,r30,12
- 584: 48 00 00 01 bl 584 .*
- 588: 91 43 80 04 stw r10,-32764\(r3\)
- 58c: 3d 23 00 00 addis r9,r3,0
- 590: 91 49 80 08 stw r10,-32760\(r9\)
- 594: 81 3e 00 2c lwz r9,44\(r30\)
- 598: 7d 49 13 2e sthx r10,r9,r2
- 59c: a1 42 00 00 lhz r10,0\(r2\)
- 5a0: 3d 22 00 00 addis r9,r2,0
- 5a4: a9 49 00 00 lha r10,0\(r9\)
+ 538: 38 7f 00 1c addi r3,r31,28
+ 53c: 48 00 00 01 bl 53c .*
+ 540: 38 7f 00 0c addi r3,r31,12
+ 544: 48 00 00 01 bl 544 .*
+ 548: 38 7f 00 24 addi r3,r31,36
+ 54c: 48 01 01 95 bl 106e0 .*
+ 550: 38 7f 00 0c addi r3,r31,12
+ 554: 48 01 01 8d bl 106e0 .*
+ 558: 39 23 80 20 addi r9,r3,-32736
+ 55c: 3d 23 00 00 addis r9,r3,0
+ 560: 81 49 80 24 lwz r10,-32732\(r9\)
+ 564: 81 3f 00 2c lwz r9,44\(r31\)
+ 568: 7d 49 12 2e lhzx r10,r9,r2
+ 56c: 89 42 00 00 lbz r10,0\(r2\)
+ 570: 3d 22 00 00 addis r9,r2,0
+ 574: 99 49 00 00 stb r10,0\(r9\)
+ 578: 38 7e 00 14 addi r3,r30,20
+ 57c: 48 00 00 01 bl 57c .*
+ 580: 38 7e 00 0c addi r3,r30,12
+ 584: 48 00 00 01 bl 584 .*
+ 588: 91 43 80 04 stw r10,-32764\(r3\)
+ 58c: 3d 23 00 00 addis r9,r3,0
+ 590: 91 49 80 08 stw r10,-32760\(r9\)
+ 594: 81 3e 00 2c lwz r9,44\(r30\)
+ 598: 7d 49 13 2e sthx r10,r9,r2
+ 59c: a1 42 00 00 lhz r10,0\(r2\)
+ 5a0: 3d 22 00 00 addis r9,r2,0
+ 5a4: a9 49 00 00 lha r10,0\(r9\)
Disassembly of section \.got:
00010664 <\.got>:
diff --git a/ld/testsuite/ld-powerpc/tlstoc.d b/ld/testsuite/ld-powerpc/tlstoc.d
index c111a5d..cfa8aba 100644
--- a/ld/testsuite/ld-powerpc/tlstoc.d
+++ b/ld/testsuite/ld-powerpc/tlstoc.d
@@ -13,25 +13,25 @@ Disassembly of section \.text:
.* 4e 80 00 20 blr
.* <_start>:
-.* 3c 6d 00 00 addis r3,r13,0
+.* 3c 6d 00 00 addis r3,r13,0
.* 60 00 00 00 nop
-.* 38 63 90 40 addi r3,r3,-28608
-.* 3c 6d 00 00 addis r3,r13,0
+.* 38 63 90 40 addi r3,r3,-28608
+.* 3c 6d 00 00 addis r3,r13,0
.* 60 00 00 00 nop
-.* 38 63 10 00 addi r3,r3,4096
-.* 3c 6d 00 00 addis r3,r13,0
+.* 38 63 10 00 addi r3,r3,4096
+.* 3c 6d 00 00 addis r3,r13,0
.* 60 00 00 00 nop
-.* 38 63 90 48 addi r3,r3,-28600
-.* 3c 6d 00 00 addis r3,r13,0
+.* 38 63 90 48 addi r3,r3,-28600
+.* 3c 6d 00 00 addis r3,r13,0
.* 60 00 00 00 nop
-.* 38 63 10 00 addi r3,r3,4096
-.* 39 23 80 50 addi r9,r3,-32688
-.* 3d 23 00 00 addis r9,r3,0
-.* 81 49 80 58 lwz r10,-32680\(r9\)
-.* e9 22 80 40 ld r9,-32704\(r2\)
-.* 7d 49 18 2a ldx r10,r9,r3
-.* 3d 2d 00 00 addis r9,r13,0
-.* a1 49 90 68 lhz r10,-28568\(r9\)
-.* 89 4d 90 70 lbz r10,-28560\(r13\)
-.* 3d 2d 00 00 addis r9,r13,0
-.* 99 49 90 78 stb r10,-28552\(r9\)
+.* 38 63 10 00 addi r3,r3,4096
+.* 39 23 80 50 addi r9,r3,-32688
+.* 3d 23 00 00 addis r9,r3,0
+.* 81 49 80 58 lwz r10,-32680\(r9\)
+.* e9 22 80 40 ld r9,-32704\(r2\)
+.* 7d 49 18 2a ldx r10,r9,r3
+.* 3d 2d 00 00 addis r9,r13,0
+.* a1 49 90 68 lhz r10,-28568\(r9\)
+.* 89 4d 90 70 lbz r10,-28560\(r13\)
+.* 3d 2d 00 00 addis r9,r13,0
+.* 99 49 90 78 stb r10,-28552\(r9\)
diff --git a/ld/testsuite/ld-powerpc/tlstocso.d b/ld/testsuite/ld-powerpc/tlstocso.d
index 8ea7627..0534b3b 100644
--- a/ld/testsuite/ld-powerpc/tlstocso.d
+++ b/ld/testsuite/ld-powerpc/tlstocso.d
@@ -9,52 +9,52 @@
Disassembly of section \.text:
.* <\.__tls_get_addr>:
-.* 3d 82 00 00 addis r12,r2,0
-.* f8 41 00 28 std r2,40\(r1\)
-.* e9 6c 80 70 ld r11,-32656\(r12\)
-.* e8 4c 80 78 ld r2,-32648\(r12\)
-.* 7d 69 03 a6 mtctr r11
-.* e9 6c 80 80 ld r11,-32640\(r12\)
+.* 3d 82 00 00 addis r12,r2,0
+.* f8 41 00 28 std r2,40\(r1\)
+.* e9 6c 80 70 ld r11,-32656\(r12\)
+.* e8 4c 80 78 ld r2,-32648\(r12\)
+.* 7d 69 03 a6 mtctr r11
+.* e9 6c 80 80 ld r11,-32640\(r12\)
.* 4e 80 04 20 bctr
.* <_start>:
-.* 38 62 80 08 addi r3,r2,-32760
-.* 4b ff ff e1 bl .* <\.__tls_get_addr>
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 38 62 80 18 addi r3,r2,-32744
-.* 4b ff ff d5 bl .* <\.__tls_get_addr>
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 38 62 80 28 addi r3,r2,-32728
-.* 4b ff ff c9 bl .* <\.__tls_get_addr>
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 38 62 80 38 addi r3,r2,-32712
-.* 4b ff ff bd bl .* <\.__tls_get_addr>
-.* e8 41 00 28 ld r2,40\(r1\)
-.* 39 23 80 40 addi r9,r3,-32704
-.* 3d 23 00 00 addis r9,r3,0
-.* 81 49 80 48 lwz r10,-32696\(r9\)
-.* e9 22 80 48 ld r9,-32696\(r2\)
-.* 7d 49 18 2a ldx r10,r9,r3
-.* e9 22 80 50 ld r9,-32688\(r2\)
-.* 7d 49 6a 2e lhzx r10,r9,r13
-.* 89 4d 00 00 lbz r10,0\(r13\)
-.* 3d 2d 00 00 addis r9,r13,0
-.* 99 49 00 00 stb r10,0\(r9\)
-.* 7d 89 02 a6 mfctr r12
-.* 78 0b 1f 24 rldicr r11,r0,3,60
-.* 34 40 80 00 addic\. r2,r0,-32768
-.* 7d 8b 60 50 subf r12,r11,r12
-.* 7c 42 fe 76 sradi r2,r2,63
-.* 78 0b 17 64 rldicr r11,r0,2,61
-.* 7c 42 58 38 and r2,r2,r11
-.* 7d 8b 60 50 subf r12,r11,r12
-.* 7d 8c 12 14 add r12,r12,r2
-.* 3d 8c 00 01 addis r12,r12,1
-.* e9 6c 01 ec ld r11,492\(r12\)
-.* 39 8c 01 ec addi r12,r12,492
-.* e8 4c 00 08 ld r2,8\(r12\)
-.* 7d 69 03 a6 mtctr r11
-.* e9 6c 00 10 ld r11,16\(r12\)
+.* 38 62 80 08 addi r3,r2,-32760
+.* 4b ff ff e1 bl .* <\.__tls_get_addr>
+.* e8 41 00 28 ld r2,40\(r1\)
+.* 38 62 80 18 addi r3,r2,-32744
+.* 4b ff ff d5 bl .* <\.__tls_get_addr>
+.* e8 41 00 28 ld r2,40\(r1\)
+.* 38 62 80 28 addi r3,r2,-32728
+.* 4b ff ff c9 bl .* <\.__tls_get_addr>
+.* e8 41 00 28 ld r2,40\(r1\)
+.* 38 62 80 38 addi r3,r2,-32712
+.* 4b ff ff bd bl .* <\.__tls_get_addr>
+.* e8 41 00 28 ld r2,40\(r1\)
+.* 39 23 80 40 addi r9,r3,-32704
+.* 3d 23 00 00 addis r9,r3,0
+.* 81 49 80 48 lwz r10,-32696\(r9\)
+.* e9 22 80 48 ld r9,-32696\(r2\)
+.* 7d 49 18 2a ldx r10,r9,r3
+.* e9 22 80 50 ld r9,-32688\(r2\)
+.* 7d 49 6a 2e lhzx r10,r9,r13
+.* 89 4d 00 00 lbz r10,0\(r13\)
+.* 3d 2d 00 00 addis r9,r13,0
+.* 99 49 00 00 stb r10,0\(r9\)
+.* 7d 89 02 a6 mfctr r12
+.* 78 0b 1f 24 rldicr r11,r0,3,60
+.* 34 40 80 00 addic\. r2,r0,-32768
+.* 7d 8b 60 50 subf r12,r11,r12
+.* 7c 42 fe 76 sradi r2,r2,63
+.* 78 0b 17 64 rldicr r11,r0,2,61
+.* 7c 42 58 38 and r2,r2,r11
+.* 7d 8b 60 50 subf r12,r11,r12
+.* 7d 8c 12 14 add r12,r12,r2
+.* 3d 8c 00 01 addis r12,r12,1
+.* e9 6c 01 ec ld r11,492\(r12\)
+.* 39 8c 01 ec addi r12,r12,492
+.* e8 4c 00 08 ld r2,8\(r12\)
+.* 7d 69 03 a6 mtctr r11
+.* e9 6c 00 10 ld r11,16\(r12\)
.* 4e 80 04 20 bctr
-.* 38 00 00 00 li r0,0
-.* 4b ff ff bc b .*
+.* 38 00 00 00 li r0,0
+.* 4b ff ff bc b .*
generated by cgit v1.1 at 2024-12-04 20:47:57 +0000