diff options
Diffstat (limited to 'ld')
| -rw-r--r-- | ld/ChangeLog | 9 | ||||
| -rw-r--r-- | ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp | 3 | ||||
| -rw-r--r-- | ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d | 5 | ||||
| -rw-r--r-- | ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2a.d | 5 | ||||
| -rw-r--r-- | ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2a.s (renamed from ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.s) | 2 | ||||
| -rw-r--r-- | ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2b.d | 5 | ||||
| -rw-r--r-- | ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2b.s | 16 |
7 files changed, 38 insertions, 7 deletions
diff --git a/ld/ChangeLog b/ld/ChangeLog index e9aae88..3969b8c 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,12 @@ +2021-05-14 Nelson Chu <nelson.chu@sifive.com> + + * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated. + * testsuite/ld-riscv-elf/pcrel-lo-addend-2a.d: Renamed from + pcrel-lo-addend-2. + * testsuite/ld-riscv-elf/pcrel-lo-addend-2a.s: Likewise. + * testsuite/ld-riscv-elf/pcrel-lo-addend-2b.d: New testcase. + * testsuite/ld-riscv-elf/pcrel-lo-addend-2b.s: Likewise. + 2021-05-13 Fangrui Song <maskray@google.com> PR 27834 diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp index f3ff95c..319ac7e 100644 --- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp +++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp @@ -85,7 +85,8 @@ if [istarget "riscv*-*-*"] { run_dump_test "c-lui-2" run_dump_test "disas-jalr" run_dump_test "pcrel-lo-addend" - run_dump_test "pcrel-lo-addend-2" + run_dump_test "pcrel-lo-addend-2a" + run_dump_test "pcrel-lo-addend-2b" run_dump_test "restart-relax" run_dump_test "attr-merge-arch-01" run_dump_test "attr-merge-arch-02" diff --git a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d deleted file mode 100644 index 895c6cc..0000000 --- a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.d +++ /dev/null @@ -1,5 +0,0 @@ -#name: %pcrel_lo overflow with an addend -#source: pcrel-lo-addend-2.s -#as: -march=rv32ic -#ld: -m[riscv_choose_ilp32_emul] --no-relax -#error: .*dangerous relocation: %pcrel_lo overflow with an addend diff --git a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2a.d b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2a.d new file mode 100644 index 0000000..cd50cbf --- /dev/null +++ b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2a.d @@ -0,0 +1,5 @@ +#name: %pcrel_lo overflow with an addend (2a) +#source: pcrel-lo-addend-2a.s +#as: -march=rv32ic +#ld: -m[riscv_choose_ilp32_emul] --no-relax +#error: .*dangerous relocation: %pcrel_lo overflow with an addend, the value of %pcrel_hi is 0x1000 without any addend, but may be 0x2000 after adding the %pcrel_lo addend diff --git a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.s b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2a.s index b7f8212..1e36774 100644 --- a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2.s +++ b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2a.s @@ -5,7 +5,7 @@ _start: nop .LA0: auipc a5,%pcrel_hi(ll) lw a0,%pcrel_lo(.LA0)(a5) - lw a0,%pcrel_lo(.LA0+4)(a5) + lw a0,%pcrel_lo(.LA0+0x4)(a5) ret .globl ll .data diff --git a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2b.d b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2b.d new file mode 100644 index 0000000..d20f8c1 --- /dev/null +++ b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2b.d @@ -0,0 +1,5 @@ +#name: %pcrel_lo overflow with an addend (2b) +#source: pcrel-lo-addend-2b.s +#as: -march=rv32ic +#ld: -m[riscv_choose_ilp32_emul] --no-relax +#error: .*dangerous relocation: %pcrel_lo overflow with an addend, the value of %pcrel_hi is 0x1000 without any addend, but may be 0x2000 after adding the %pcrel_lo addend diff --git a/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2b.s b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2b.s new file mode 100644 index 0000000..9fd063f --- /dev/null +++ b/ld/testsuite/ld-riscv-elf/pcrel-lo-addend-2b.s @@ -0,0 +1,16 @@ + .text + .globl _start + .align 3 +_start: + nop + .LA0: auipc a5,%pcrel_hi(ll) + lw a0,%pcrel_lo(.LA0)(a5) + lw a0,%pcrel_lo(.LA0+0x1000)(a5) + ret + .globl ll + .data + .align 3 + .zero 2024 +ll: + .word 0 + .word 0 |