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-rw-r--r--ld/testsuite/ld-powerpc/elfv2exe.d11
-rw-r--r--ld/testsuite/ld-powerpc/notoc.d49
-rw-r--r--ld/testsuite/ld-powerpc/notoc.wf12
-rw-r--r--ld/testsuite/ld-powerpc/notoc3.d15
-rw-r--r--ld/testsuite/ld-powerpc/pr23937.d4
5 files changed, 44 insertions, 47 deletions
diff --git a/ld/testsuite/ld-powerpc/elfv2exe.d b/ld/testsuite/ld-powerpc/elfv2exe.d
index 586264d..330243c 100644
--- a/ld/testsuite/ld-powerpc/elfv2exe.d
+++ b/ld/testsuite/ld-powerpc/elfv2exe.d
@@ -12,18 +12,17 @@ Disassembly of section \.text:
.*: (e9 8c 7f f0|f0 7f 8c e9) ld r12,32752\(r12\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
-
-0+100000d0 <.*\.plt_branch\.f2>:
+#...
+0+100000e0 <.*\.plt_branch\.f2>:
.*: (3d 82 ff ff|ff ff 82 3d) addis r12,r2,-1
.*: (e9 8c 7f f8|f8 7f 8c e9) ld r12,32760\(r12\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
-0+100000e0 <.*\.long_branch\.f5>:
+0+100000f0 <.*\.long_branch\.f5>:
.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
-.*: (48 00 00 6c|6c 00 00 48) b .* <f5>
- \.\.\.
-
+.*: (48 00 00 5c|5c 00 00 48) b .* <f5>
+#...
0+10000100 <(f1|_start)>:
.*: (3c 40 10 02|02 10 40 3c) lis r2,4098
.*: (38 42 82 00|00 82 42 38) addi r2,r2,-32256
diff --git a/ld/testsuite/ld-powerpc/notoc.d b/ld/testsuite/ld-powerpc/notoc.d
index 69f1721..972f958 100644
--- a/ld/testsuite/ld-powerpc/notoc.d
+++ b/ld/testsuite/ld-powerpc/notoc.d
@@ -15,7 +15,7 @@ Disassembly of section \.text:
.* <.*\.long_branch\.g1>:
.*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\)
.*: (8c 00 00 48|48 00 00 8c) b .* <g1>
-
+#...
.* <.*\.plt_branch\.ext>:
.*: (a6 02 88 7d|7d 88 02 a6) mflr r12
.*: (05 00 9f 42|42 9f 00 05) bcl .*
@@ -25,7 +25,7 @@ Disassembly of section \.text:
.*: (ff ff 8c 61|61 8c ff ff) ori r12,r12,65535
.*: (c6 07 9c 79|79 9c 07 c6) sldi r28,r12,32
.*: (ff ef 8c 65|65 8c ef ff) oris r12,r12,61439
-.*: (28 ff 8c 61|61 8c ff 28) ori r12,r12,65320
+.*: (18 ff 8c 61|61 8c ff 18) ori r12,r12,65304
.*: (14 62 8b 7d|7d 8b 62 14) add r12,r11,r12
.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12
.*: (20 04 80 4e|4e 80 04 20) bctr
@@ -35,58 +35,57 @@ Disassembly of section \.text:
.*: (05 00 9f 42|42 9f 00 05) bcl .*
.*: (a6 02 68 7d|7d 68 02 a6) mflr r11
.*: (a6 03 88 7d|7d 88 03 a6) mtlr r12
-.*: (64 00 8b 39|39 8b 00 64) addi r12,r11,100
-.*: (58 00 00 48|48 00 00 58) b .* <f2>
+.*: (54 00 8b 39|39 8b 00 54) addi r12,r11,84
+.*: (.. .. 00 48|48 00 .. ..) b .* <f2>
.* <.*\.long_branch\.g2>:
.*: (a6 02 88 7d|7d 88 02 a6) mflr r12
.*: (05 00 9f 42|42 9f 00 05) bcl .*
.*: (a6 02 68 7d|7d 68 02 a6) mflr r11
.*: (a6 03 88 7d|7d 88 03 a6) mtlr r12
-.*: (80 00 8b 39|39 8b 00 80) addi r12,r11,128
-.*: (74 00 00 48|48 00 00 74) b .* <g2>
- \.\.\.
-
+.*: (70 00 8b 39|39 8b 00 70) addi r12,r11,112
+.*: (.. .. 00 48|48 00 .. ..) b .* <g2>
+#...
.* <f1>:
.*: (01 00 00 48|48 00 00 01) bl .* <f1>
-.*: (bd ff ff 4b|4b ff ff bd) bl .* <.*\.long_branch\.f2>
-.*: (11 00 00 48|48 00 00 11) bl .* <g1>
-.*: (cd ff ff 4b|4b ff ff cd) bl .* <.*\.long_branch\.g2>
-.*: (81 ff ff 4b|4b ff ff 81) bl .* <.*\.plt_branch\.ext>
+.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.long_branch\.f2>
+.*: (.. .. 00 48|48 00 .. ..) bl .* <g1>
+.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.long_branch\.g2>
+.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.plt_branch\.ext>
.*: (20 00 80 4e|4e 80 00 20) blr
.* <g1>:
-.*: (a9 ff ff 4b|4b ff ff a9) bl .* <.*\.long_branch\.f2>
-.*: (e5 ff ff 4b|4b ff ff e5) bl .* <f1>
-.*: (b9 ff ff 4b|4b ff ff b9) bl .* <.*\.long_branch\.g2>
-.*: (f5 ff ff 4b|4b ff ff f5) bl .* <g1>
+.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.long_branch\.f2>
+.*: (.. .. ff 4b|4b ff .. ..) bl .* <f1>
+.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.long_branch\.g2>
+.*: (.. .. ff 4b|4b ff .. ..) bl .* <g1>
.*: (20 00 80 4e|4e 80 00 20) blr
.* <f2>:
.*: (01 10 40 3c|3c 40 10 01) lis r2,4097
.*: (00 80 42 38|38 42 80 00) addi r2,r2,-32768
-.*: (4d ff ff 4b|4b ff ff 4d) bl .* <.*\.long_branch\.f1>
+.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.long_branch\.f1>
.*: (18 00 41 e8|e8 41 00 18) ld r2,24\(r1\)
-.*: (f9 ff ff 4b|4b ff ff f9) bl .* <f2\+0x8>
+.*: (.. .. ff 4b|4b ff .. ..) bl .* <f2\+0x8>
.*: (00 00 00 60|60 00 00 00) nop
-.*: (45 ff ff 4b|4b ff ff 45) bl .* <.*\.long_branch\.g1>
+.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.long_branch\.g1>
.*: (18 00 41 e8|e8 41 00 18) ld r2,24\(r1\)
-.*: (1d 00 00 48|48 00 00 1d) bl .* <g2\+0x8>
+.*: (.. .. 00 48|48 00 .. ..) bl .* <g2\+0x8>
.*: (00 00 00 60|60 00 00 00) nop
-.*: (3d ff ff 4b|4b ff ff 3d) bl .* <.*\.plt_branch\.ext>
+.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.plt_branch\.ext>
.*: (00 00 00 60|60 00 00 00) nop
.*: (20 00 80 4e|4e 80 00 20) blr
.* <g2>:
.*: (01 10 40 3c|3c 40 10 01) lis r2,4097
.*: (00 80 42 38|38 42 80 00) addi r2,r2,-32768
-.*: (cd ff ff 4b|4b ff ff cd) bl .* <f2\+0x8>
+.*: (.. .. ff 4b|4b ff .. ..) bl .* <f2\+0x8>
.*: (00 00 00 60|60 00 00 00) nop
-.*: (11 ff ff 4b|4b ff ff 11) bl .* <.*\.long_branch\.f1>
+.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.long_branch\.f1>
.*: (18 00 41 e8|e8 41 00 18) ld r2,24\(r1\)
-.*: (f1 ff ff 4b|4b ff ff f1) bl .* <g2\+0x8>
+.*: (.. .. ff 4b|4b ff .. ..) bl .* <g2\+0x8>
.*: (00 00 00 60|60 00 00 00) nop
-.*: (09 ff ff 4b|4b ff ff 09) bl .* <.*\.long_branch\.g1>
+.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.long_branch\.g1>
.*: (18 00 41 e8|e8 41 00 18) ld r2,24\(r1\)
.*: (20 00 80 4e|4e 80 00 20) blr
diff --git a/ld/testsuite/ld-powerpc/notoc.wf b/ld/testsuite/ld-powerpc/notoc.wf
index 208d676..00bef4c 100644
--- a/ld/testsuite/ld-powerpc/notoc.wf
+++ b/ld/testsuite/ld-powerpc/notoc.wf
@@ -11,17 +11,17 @@ Contents of the \.eh_frame section:
DW_CFA_def_cfa: r1 ofs 0
00000014 0000000000000024 00000018 FDE cie=00000000 pc=00000000100000c0\.\.0000000010000140
- DW_CFA_advance_loc: 24 to 00000000100000d8
+ DW_CFA_advance_loc: 40 to 00000000100000e8
DW_CFA_register: r65 in r12
- DW_CFA_advance_loc: 8 to 00000000100000e0
+ DW_CFA_advance_loc: 8 to 00000000100000f0
DW_CFA_restore_extended: r65
- DW_CFA_advance_loc: 40 to 0000000010000108
+ DW_CFA_advance_loc: 40 to 0000000010000118
DW_CFA_register: r65 in r12
- DW_CFA_advance_loc: 8 to 0000000010000110
+ DW_CFA_advance_loc: 8 to 0000000010000120
DW_CFA_restore_extended: r65
- DW_CFA_advance_loc: 16 to 0000000010000120
+ DW_CFA_advance_loc: 16 to 0000000010000130
DW_CFA_register: r65 in r12
- DW_CFA_advance_loc: 8 to 0000000010000128
+ DW_CFA_advance_loc: 8 to 0000000010000138
DW_CFA_restore_extended: r65
DW_CFA_nop
DW_CFA_nop
diff --git a/ld/testsuite/ld-powerpc/notoc3.d b/ld/testsuite/ld-powerpc/notoc3.d
index 24cf9bb..dfb10ef 100644
--- a/ld/testsuite/ld-powerpc/notoc3.d
+++ b/ld/testsuite/ld-powerpc/notoc3.d
@@ -14,12 +14,12 @@ Disassembly of section \.text:
.* <.*\.long_branch\.g1>:
.*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\)
.*: (.. .. 00 48|48 00 .. ..) b .* <g1>
-
+#...
.* <.*\.plt_branch\.ext>:
.*: (00 20 60 3d|3d 60 20 00) lis r11,8192
.*: (00 00 6b 61|61 6b 00 00) ori r11,r11,0
-.*: (ff ef 13 06|06 13 ef ff) pla r12,-268435736 # 0
-.*: (e8 fe 80 39|39 80 fe e8)
+.*: (ff ef 13 06|06 13 ef ff) pla r12,-268435752 # 0
+.*: (d8 fe 80 39|39 80 fe d8)
.*: (46 17 6b 79|79 6b 17 46) sldi r11,r11,34
.*: (14 62 8b 7d|7d 8b 62 14) add r12,r11,r12
.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12
@@ -30,17 +30,16 @@ Disassembly of section \.text:
.* <.*\.long_branch\.f2>:
.*: (00 00 00 60|60 00 00 00) nop
-.*: (00 00 10 06|06 10 00 00) pla r12,108 # .* <f2>
-.*: (6c 00 80 39|39 80 00 6c)
+.*: (00 00 10 06|06 10 00 00) pla r12,92 # .* <f2>
+.*: (5c 00 80 39|39 80 00 5c)
.*: (.. .. 00 48|48 00 .. ..) b .* <f2>
.* <.*\.long_branch\.g2>:
.*: (00 00 00 60|60 00 00 00) nop
-.*: (00 00 10 06|06 10 00 00) pla r12,144 # .* <g2>
-.*: (90 00 80 39|39 80 00 90)
+.*: (00 00 10 06|06 10 00 00) pla r12,128 # .* <g2>
+.*: (80 00 80 39|39 80 00 80)
.*: (.. .. 00 48|48 00 .. ..) b .* <g2>
#...
-
.* <f1>:
.*: (01 00 00 48|48 00 00 01) bl .* <f1>
.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.long_branch\.f2>
diff --git a/ld/testsuite/ld-powerpc/pr23937.d b/ld/testsuite/ld-powerpc/pr23937.d
index 6ef79e8..4610c28 100644
--- a/ld/testsuite/ld-powerpc/pr23937.d
+++ b/ld/testsuite/ld-powerpc/pr23937.d
@@ -4,7 +4,7 @@
# Check that the IRELATIVE addend is magic+0, not magic+8
#...
-.* R_PPC64_IRELATIVE +10000180
+.* R_PPC64_IRELATIVE +100001a0
#...
-.*: 0+10000180 +20 IFUNC +LOCAL +DEFAULT .* magic
+.*: 0+100001a0 +20 IFUNC +LOCAL +DEFAULT .* magic
#pass
generated by cgit v1.1 at 2024-11-29 05:18:48 +0000