diff options
Diffstat (limited to 'ld/testsuite/ld-spu')
| -rw-r--r-- | ld/testsuite/ld-spu/ovl.d | 41 | ||||
| -rw-r--r-- | ld/testsuite/ld-spu/ovl.s | 2 |
2 files changed, 31 insertions, 12 deletions
diff --git a/ld/testsuite/ld-spu/ovl.d b/ld/testsuite/ld-spu/ovl.d index 2edf985..ae9e33a 100644 --- a/ld/testsuite/ld-spu/ovl.d +++ b/ld/testsuite/ld-spu/ovl.d @@ -1,6 +1,6 @@ #source: ovl.s -#ld: -N -T ovl.lnk -#objdump: -D +#ld: -N -T ovl.lnk --emit-relocs +#objdump: -D -r .*elf32-spu @@ -11,28 +11,39 @@ Disassembly of section \.text: 104: 48 20 00 00 xor \$0,\$0,\$0 108: 24 00 00 80 stqd \$0,0\(\$1\) 10c: 24 00 40 80 stqd \$0,16\(\$1\) - 110: 33 00 04 00 brsl \$0,130 <f0\+0x4> # 130 - 114: 33 00 04 80 brsl \$0,138 <f0\+0xc> # 138 - 118: 33 00 07 00 brsl \$0,150 <f0\+0x24> # 150 + 110: 33 00 04 00 brsl \$0,130 <00000000\.ovl_call\.f1_a1> # 130 + 110: SPU_REL16 f1_a1 + 114: 33 00 04 80 brsl \$0,138 <00000000\.ovl_call\.f2_a1> # 138 + 114: SPU_REL16 f2_a1 + 118: 33 00 07 00 brsl \$0,150 <00000000\.ovl_call\.f1_a2> # 150 + 118: SPU_REL16 f1_a2 11c: 42 00 ac 09 ila \$9,344 # 158 + 11c: SPU_ADDR18 f2_a2 120: 35 20 04 80 bisl \$0,\$9 124: 1c 08 00 81 ai \$1,\$1,32 # 20 128: 32 7f fb 00 br 100 <_start> # 100 + 128: SPU_REL16 _start 0000012c <f0>: 12c: 35 00 00 00 bi \$0 +00000130 <00000000\.ovl_call\.f1_a1>: 130: 42 02 00 4f ila \$79,1024 # 400 - 134: 32 00 02 80 br 148 <f0\+0x1c> # 148 + 134: 32 00 02 80 br 148 .* +00000138 <00000000\.ovl_call\.f2_a1>: 138: 42 02 02 4f ila \$79,1028 # 404 - 13c: 32 00 01 80 br 148 <f0\+0x1c> # 148 + 13c: 32 00 01 80 br 148 .* +00000140 <00000000\.ovl_call\.f4_a1>: 140: 42 02 08 4f ila \$79,1040 # 410 144: 40 20 00 00 nop \$0 148: 42 00 00 ce ila \$78,1 14c: 32 00 0a 80 br 1a0 <__ovly_load> # 1a0 +00000150 <00000000\.ovl_call\.f1_a2>: 150: 42 02 00 4f ila \$79,1024 # 400 - 154: 32 00 02 80 br 168 <f0\+0x3c> # 168 + 154: 32 00 02 80 br 168 .* +00000158 <00000000\.ovl_call\.f2_a2>: 158: 42 02 12 4f ila \$79,1060 # 424 - 15c: 32 00 01 80 br 168 <f0\+0x3c> # 168 + 15c: 32 00 01 80 br 168 .* +00000160 <00000000\.ovl_call\.14:8>: 160: 42 02 1a 4f ila \$79,1076 # 434 164: 40 20 00 00 nop \$0 168: 42 00 01 4e ila \$78,2 @@ -51,9 +62,11 @@ Disassembly of section \.ov_a1: 00000400 <f1_a1>: 400: 32 00 01 80 br 40c <f3_a1> # 40c + 400: SPU_REL16 f3_a1 00000404 <f2_a1>: 404: 42 00 a0 03 ila \$3,320 # 140 + 404: SPU_ADDR18 f4_a1 408: 35 00 00 00 bi \$0 0000040c <f3_a1>: @@ -69,22 +82,28 @@ Disassembly of section \.ov_a2: 404: 24 ff 80 81 stqd \$1,-32\(\$1\) 408: 1c f8 00 81 ai \$1,\$1,-32 40c: 33 7f a4 00 brsl \$0,12c <f0> # 12c - 410: 33 7f a4 00 brsl \$0,130 <f0\+0x4> # 130 + 40c: SPU_REL16 f0 + 410: 33 7f a4 00 brsl \$0,130 <00000000\.ovl_call\.f1_a1> # 130 + 410: SPU_REL16 f1_a1 414: 33 00 03 80 brsl \$0,430 <f3_a2> # 430 + 414: SPU_REL16 f3_a2 418: 34 00 c0 80 lqd \$0,48\(\$1\) # 30 41c: 1c 08 00 81 ai \$1,\$1,32 # 20 420: 35 00 00 00 bi \$0 00000424 <f2_a2>: 424: 41 00 00 03 ilhu \$3,0 + 424: SPU_ADDR16_HI f4_a2 428: 60 80 b0 03 iohl \$3,352 # 160 + 428: SPU_ADDR16_LO f4_a2 42c: 35 00 00 00 bi \$0 00000430 <f3_a2>: 430: 35 00 00 00 bi \$0 00000434 <f4_a2>: - 434: 35 00 00 00 bi \$0 + 434: 32 7f ff 80 br 430 <f3_a2> # 430 + 434: SPU_REL16 f3_a2 \.\.\. Disassembly of section .data: diff --git a/ld/testsuite/ld-spu/ovl.s b/ld/testsuite/ld-spu/ovl.s index c4bc68c..2ca380a 100644 --- a/ld/testsuite/ld-spu/ovl.s +++ b/ld/testsuite/ld-spu/ovl.s @@ -78,5 +78,5 @@ f3_a2: .type f4_a2,@function f4_a2: - bi lr + br f3_a2 .size f4_a2,.-f4_a2 |