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path: root/ld/testsuite/ld-powerpc/elfv2so.d
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Diffstat (limited to 'ld/testsuite/ld-powerpc/elfv2so.d')
-rw-r--r--ld/testsuite/ld-powerpc/elfv2so.d12
1 files changed, 8 insertions, 4 deletions
diff --git a/ld/testsuite/ld-powerpc/elfv2so.d b/ld/testsuite/ld-powerpc/elfv2so.d
index 2c1fa32..a577b2a 100644
--- a/ld/testsuite/ld-powerpc/elfv2so.d
+++ b/ld/testsuite/ld-powerpc/elfv2so.d
@@ -12,24 +12,28 @@ Disassembly of section \.text:
.*: (e9 82 80 38|38 80 82 e9) ld r12,-32712\(r2\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
+ \.\.\.
.* <.*\.plt_call\.f3>:
.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
.*: (e9 82 80 28|28 80 82 e9) ld r12,-32728\(r2\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
+ \.\.\.
.* <.*\.plt_call\.f2>:
.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
.*: (e9 82 80 30|30 80 82 e9) ld r12,-32720\(r2\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
+ \.\.\.
.* <.*\.plt_call\.f1>:
.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
.*: (e9 82 80 40|40 80 82 e9) ld r12,-32704\(r2\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
+ \.\.\.
.* <f1>:
.*: (3c 4c 00 02|02 00 4c 3c) addis r2,r12,2
@@ -37,14 +41,14 @@ Disassembly of section \.text:
.*: (7c 08 02 a6|a6 02 08 7c) mflr r0
.*: (f8 21 ff e1|e1 ff 21 f8) stdu r1,-32\(r1\)
.*: (f8 01 00 30|30 00 01 f8) std r0,48\(r1\)
-.*: (4b ff ff dd|dd ff ff 4b) bl .*\.plt_call\.f1>
+.*: (4b ff ff cd|cd ff ff 4b) bl .*\.plt_call\.f1>
.*: (e8 62 80 08|08 80 62 e8) ld r3,-32760\(r2\)
-.*: (4b ff ff c5|c5 ff ff 4b) bl .*\.plt_call\.f2>
+.*: (4b ff ff a5|a5 ff ff 4b) bl .*\.plt_call\.f2>
.*: (e8 41 00 18|18 00 41 e8) ld r2,24\(r1\)
.*: (e8 62 80 10|10 80 62 e8) ld r3,-32752\(r2\)
-.*: (4b ff ff a9|a9 ff ff 4b) bl .*\.plt_call\.f3>
+.*: (4b ff ff 79|79 ff ff 4b) bl .*\.plt_call\.f3>
.*: (e8 41 00 18|18 00 41 e8) ld r2,24\(r1\)
-.*: (4b ff ff 91|91 ff ff 4b) bl .*\.plt_call\.f4>
+.*: (4b ff ff 51|51 ff ff 4b) bl .*\.plt_call\.f4>
.*: (e8 41 00 18|18 00 41 e8) ld r2,24\(r1\)
.*: (e8 01 00 30|30 00 01 e8) ld r0,48\(r1\)
.*: (38 21 00 20|20 00 21 38) addi r1,r1,32