diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 7 | ||||
| -rw-r--r-- | include/elf/mips.h | 4 | ||||
| -rw-r--r-- | include/opcode/mips.h | 7 |
3 files changed, 16 insertions, 2 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 0b57d2a..fe1d6c9 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,10 @@ +2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com> + + * elf/mips.h (AFL_ASE_GINV, AFL_ASE_RESERVED1): New macros. + (AFL_ASE_MASK): Update to include AFL_ASE_GINV. + * opcode/mips.h: Document "+\" operand format. + (ASE_GINV): New macro. + 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> diff --git a/include/elf/mips.h b/include/elf/mips.h index d11b99f..4e2cde3 100644 --- a/include/elf/mips.h +++ b/include/elf/mips.h @@ -1236,7 +1236,9 @@ extern void bfd_mips_elf_swap_abiflags_v0_out #define AFL_ASE_DSPR3 0x00002000 /* DSP R3 ASE. */ #define AFL_ASE_MIPS16E2 0x00004000 /* MIPS16e2 ASE. */ #define AFL_ASE_CRC 0x00008000 /* CRC ASE. */ -#define AFL_ASE_MASK 0x0000ffff /* All ASEs. */ +#define AFL_ASE_RESERVED1 0x00010000 /* Reserved by MIPS Tech for WIP. */ +#define AFL_ASE_GINV 0x00020000 /* GINV ASE. */ +#define AFL_ASE_MASK 0x0002ffff /* All ASEs. */ /* Values for the isa_ext word of an ABI flags structure. */ diff --git a/include/opcode/mips.h b/include/opcode/mips.h index fcc70d5..1ab1780 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -989,6 +989,9 @@ mips_opcode_32bit_p (const struct mips_opcode *mo) "-A" symbolic offset (-262144 .. 262143) << 2 at bit 0 "-B" symbolic offset (-131072 .. 131071) << 3 at bit 0 + GINV ASE usage: + "+\" 2 bit Global TLB invalidate type at bit 8 + Other: "()" parens surrounding optional value "," separates operands @@ -1003,7 +1006,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo) Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: "1234567890" - "~!@#$%^&*|:'";" + "~!@#$%^&*|:'";\" "ABCEFGHIJKLMNOPQRSTUVWXZ" "abcdefghijklmnopqrstuvwxyz" @@ -1297,6 +1300,8 @@ static const unsigned int mips_isa_table[] = { /* Cyclic redundancy check (CRC) ASE. */ #define ASE_CRC 0x00040000 #define ASE_CRC64 0x00080000 +/* Global INValidate Extension. */ +#define ASE_GINV 0x00100000 /* MIPS ISA defines, use instead of hardcoding ISA level. */ |