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-rw-r--r--include/opcode/ChangeLog7
-rw-r--r--include/opcode/mips.h13
2 files changed, 16 insertions, 4 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 9548338..f73a5a8 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,10 @@
+2002-03-15 Chris G. Demetriou <cgd@broadcom.com>
+
+ * mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D
+ instructions.
+ (OPCODE_IS_MEMBER): Adjust comments to indicate that ASE bit masks
+ may be passed along with the ISA bitmask.
+
2002-03-05 Paul Koning <pkoning@equallogic.com>
* pdp11.h: Add format codes for float instruction formats.
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 1469e10..96c7a57 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -316,6 +316,11 @@ struct mips_opcode
#define INSN_ISA32 0x00000200
#define INSN_ISA64 0x00000400
+/* Masks used for MIPS-defined ASEs. */
+
+/* MIPS-3D ASE */
+#define INSN_MIPS3D 0x00004000
+
/* Chip specific instructions. These are bitmasks. */
/* MIPS R4650 instruction. */
@@ -367,10 +372,10 @@ struct mips_opcode
#define CPU_MIPS64 64
#define CPU_SB1 12310201 /* octal 'SB', 01. */
-/* Test for membership in an ISA including chip specific ISAs.
- INSN is pointer to an element of the opcode table; ISA is the
- specified ISA to test against; and CPU is the CPU specific ISA
- to test, or zero if no CPU specific ISA test is desired. */
+/* Test for membership in an ISA including chip specific ISAs. INSN
+ is pointer to an element of the opcode table; ISA is the specified
+ ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
+ test, or zero if no CPU specific ISA test is desired. */
#define OPCODE_IS_MEMBER(insn, isa, cpu) \
(((insn)->membership & isa) != 0 \