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-rw-r--r--include/ChangeLog7
-rw-r--r--include/opcode/arc.h26
2 files changed, 32 insertions, 1 deletions
diff --git a/include/ChangeLog b/include/ChangeLog
index 829ecc0..607eba0 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,10 @@
+2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
+ (struct arc_long_opcode): New structure.
+ (arc_long_opcodes): Declare.
+ (arc_num_long_opcodes): Declare.
+
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* elf/mips.h: Add extern "C".
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index 444341a..b71c2f5 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -25,7 +25,7 @@
#define OPCODE_ARC_H
#ifndef MAX_INSN_ARGS
-#define MAX_INSN_ARGS 8
+#define MAX_INSN_ARGS 16
#endif
#ifndef MAX_INSN_FLGS
@@ -136,6 +136,30 @@ struct arc_opcode
unsigned char flags[MAX_INSN_FLGS + 1];
};
+/* Structure used to describe 48 and 64 bit instructions. */
+struct arc_long_opcode
+{
+ /* The base instruction is either 16 or 32 bits, and is described like a
+ normal instruction. */
+ struct arc_opcode base_opcode;
+
+ /* The template value for the 32-bit LIMM extension. Used by the
+ assembler and disassembler in the same way as the 'opcode' field of
+ 'struct arc_opcode'. */
+ unsigned limm_template;
+
+ /* The mask value for the 32-bit LIMM extension. Used by the
+ disassembler just like the 'mask' field in 'struct arc_opcode'. */
+ unsigned limm_mask;
+
+ /* Array of operand codes similar to the 'operands' array in 'struct
+ arc_opcode'. These operands are used to fill in the LIMM value. */
+ unsigned char operands[MAX_INSN_ARGS + 1];
+};
+
+extern const struct arc_long_opcode arc_long_opcodes[];
+extern const unsigned arc_num_long_opcodes;
+
/* The table itself is sorted by major opcode number, and is otherwise
in the order in which the disassembler should consider
instructions. */