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-rw-r--r--include/ChangeLog6
-rw-r--r--include/opcode/aarch64.h4
2 files changed, 10 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog
index 6c9c919..80016dc 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,11 @@
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+ * opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd.
+ (AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO)
+ (AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
* opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
(AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
(AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 36e95b4..9e7f5b5 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -292,6 +292,10 @@ enum aarch64_opnd
AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
+ AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
+ AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
+ AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
+ AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */