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-rw-r--r--include/opcode/aarch64.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 6ddcaf9..7d484ad 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -51,6 +51,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */
#define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */
#define AARCH64_FEATURE_V8_7 (1ULL << 13) /* Armv8.7 processors. */
+#define AARCH64_FEATURE_CSRE (1ULL << 14) /* CSRE feature. */
#define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */
#define AARCH64_FEATURE_SIMD (1ULL << 18) /* SIMD instructions. */
#define AARCH64_FEATURE_CRC (1ULL << 19) /* CRC instructions. */
@@ -432,6 +433,7 @@ enum aarch64_opnd
AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
+ AARCH64_OPND_CSRE_CSR, /* CSRE CSR instruction Rt field. */
};
/* Qualifier constrains an operand. It either specifies a variant of an