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-rw-r--r--include/opcode/riscv-opc-extended.h11
-rw-r--r--include/opcode/riscv.h5
2 files changed, 16 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc-extended.h b/include/opcode/riscv-opc-extended.h
index de9741f..1010661 100644
--- a/include/opcode/riscv-opc-extended.h
+++ b/include/opcode/riscv-opc-extended.h
@@ -2078,3 +2078,14 @@ DECLARE_CSR(shpmcounter29, CSR_SHPMCOUNTER29, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_
DECLARE_CSR(shpmcounter30, CSR_SHPMCOUNTER30, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(shpmcounter31, CSR_SHPMCOUNTER31, CSR_CLASS_VENDOR_THEAD, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
#endif /* DECLARE_CSR */
+
+#ifndef __RISCV_OPC_SIFIVE_THEAD__
+#define __RISCV_OPC_SIFIVE_THEAD__
+/* SiFive cache control instructions. */
+#define MATCH_CFLUSH_D_L1 0xfc000073
+#define MASK_CFLUSH_D_L1 0xfff07fff
+#define MATCH_CDISCARD_D_L1 0xfc200073
+#define MASK_CDISCARD_D_L1 0xfff07fff
+#define MATCH_CFLUSH_I_L1 0xfc100073
+#define MASK_CFLUSH_I_L1 0xffffffff
+#endif /* __RISCV_OPC_SIFIVE_THEAD__ */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 8cef449..568e33b 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -529,6 +529,11 @@ enum riscv_extended_insn_class
INSN_CLASS_THEADC_OR_THEADE_OR_THEADSE,
INSN_CLASS_THEADE,
INSN_CLASS_THEADSE,
+
+ /* SiFive. */
+ INSN_CLASS_XSF_CDISCARDDLONE,
+ INSN_CLASS_XSF_CFLUSHDLONE,
+ INSN_CLASS_XSF_CFLUSHILONE,
};
/* This is a list of macro expanded instructions for extended