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-rw-r--r--include/opcode/ChangeLog5
-rw-r--r--include/opcode/rl78.h9
2 files changed, 13 insertions, 1 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 4a0534f..b5702c5 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+2015-04-30 DJ Delorie <dj@redhat.com>
+
+ * rl78.h (RL78_Dis_Isa): New.
+ (rl78_decode_opcode): Add ISA parameter.
+
2015-03-24 Terry Guo <terry.guo@arm.com>
* arm.h (arm_feature_set): Extended to provide more available bits.
diff --git a/include/opcode/rl78.h b/include/opcode/rl78.h
index 72adf14..7358d2d 100644
--- a/include/opcode/rl78.h
+++ b/include/opcode/rl78.h
@@ -30,6 +30,13 @@
extern "C" {
#endif
+typedef enum {
+ RL78_ISA_DEFAULT,
+ RL78_ISA_G10,
+ RL78_ISA_G13,
+ RL78_ISA_G14,
+} RL78_Dis_Isa;
+
/* For the purposes of these structures, the RL78 registers are as
follows, despite most of these being memory-mapped and
bank-switched: */
@@ -166,7 +173,7 @@ typedef struct
RL78_Opcode_Operand op[2];
} RL78_Opcode_Decoded;
-int rl78_decode_opcode (unsigned long, RL78_Opcode_Decoded *, int (*)(void *), void *);
+int rl78_decode_opcode (unsigned long, RL78_Opcode_Decoded *, int (*)(void *), void *, RL78_Dis_Isa);
#ifdef __cplusplus
}