diff options
Diffstat (limited to 'include/opcode/mips.h')
| -rw-r--r-- | include/opcode/mips.h | 101 |
1 files changed, 93 insertions, 8 deletions
diff --git a/include/opcode/mips.h b/include/opcode/mips.h index aa1528f..ef26167 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -417,7 +417,17 @@ enum mips_operand_type { OP_IMM_INDEX, /* An index selected by a register, e.g. [$2]. */ - OP_REG_INDEX + OP_REG_INDEX, + + /* The operand spans two 5-bit register fields, both of which must be set to + the source register. */ + OP_SAME_RS_RT, + + /* Described by mips_prev_operand. */ + OP_CHECK_PREV, + + /* A register operand that must not be zero. */ + OP_NON_ZERO_REG }; /* Enumerates the types of MIPS register. */ @@ -553,6 +563,18 @@ struct mips_reg_operand const unsigned char *reg_map; }; +/* Describes an operand that which must match a condition based on the + previous operand. */ +struct mips_check_prev_operand +{ + struct mips_operand root; + + bfd_boolean greater_than_ok; + bfd_boolean less_than_ok; + bfd_boolean equal_ok; + bfd_boolean zero_ok; +}; + /* Describes an operand that encodes a pair of registers. */ struct mips_reg_pair_operand { @@ -927,6 +949,28 @@ struct mips_opcode "+*" 5-bit register vector element index at bit 16 "+|" 8-bit mask at bit 16 + MIPS R6: + "+:" 11-bit mask at bit 0 + "+'" 26 bit PC relative branch target address + "+"" 21 bit PC relative branch target address + "+;" 5 bit same register in both OP_*_RS and OP_*_RT + "+I" 2bit unsigned bit position at bit 6 + "+O" 3bit unsigned bit position at bit 6 + "+R" must be program counter + "-a" (-262144 .. 262143) << 2 at bit 0 + "-b" (-131072 .. 131071) << 3 at bit 0 + "-d" Same as destination register GP + "-s" 5 bit source register specifier (OP_*_RS) not $0 + "-t" 5 bit source register specifier (OP_*_RT) not $0 + "-u" 5 bit source register specifier (OP_*_RT) greater than OP_*_RS + "-v" 5 bit source register specifier (OP_*_RT) not $0 not OP_*_RS + "-w" 5 bit source register specifier (OP_*_RT) less than or equal to OP_*_RS + "-x" 5 bit source register specifier (OP_*_RT) greater than or + equal to OP_*_RS + "-y" 5 bit source register specifier (OP_*_RT) not $0 less than OP_*_RS + "-A" symbolic offset (-262144 .. 262143) << 2 at bit 0 + "-B" symbolic offset (-131072 .. 131071) << 3 at bit 0 + Other: "()" parens surrounding optional value "," separates operands @@ -934,16 +978,21 @@ struct mips_opcode Characters used so far, for quick reference when adding more: "1234567890" - "%[]<>(),+:'@!#$*&\~" + "%[]<>(),+-:'@!#$*&\~" "ABCDEFGHIJKLMNOPQRSTUVWXYZ" "abcdefghijklopqrstuvwxz" Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: "1234567890" - "~!@#$%^&*|" - "ABCEFGHJKLMNPQSTUVWXZ" + "~!@#$%^&*|:'";" + "ABCEFGHIJKLMNOPQRSTUVWXZ" "abcdefghijklmnopqrstuvwxyz" + + Extension character sequences used so far ("-" followed by the + following), for quick reference when adding more: + "AB" + "abdstuvwxy" */ /* These are the bits which may be set in the pinfo field of an @@ -1051,6 +1100,8 @@ struct mips_opcode #define INSN2_READ_GPR_16 0x00002000 /* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask. */ #define INSN2_VU0_CHANNEL_SUFFIX 0x00004000 +/* Instruction has a forbidden slot. */ +#define INSN2_FORBIDDEN_SLOT 0x00008000 /* Masks used to mark instructions to indicate which MIPS ISA level they were introduced in. INSN_ISA_MASK masks an enumeration that @@ -1070,10 +1121,12 @@ struct mips_opcode #define INSN_ISA32R2 7 #define INSN_ISA32R3 8 #define INSN_ISA32R5 9 +#define INSN_ISA32R6 10 #define INSN_ISA64 11 #define INSN_ISA64R2 12 #define INSN_ISA64R3 13 #define INSN_ISA64R5 14 +#define INSN_ISA64R6 15 /* Below this point the INSN_* values correspond to combinations of ISAs. They are only for use in the opcodes table to indicate membership of a combination of ISAs that cannot be expressed using the usual inclusion @@ -1084,7 +1137,19 @@ struct mips_opcode #define INSN_ISA4_32R2 19 #define INSN_ISA5_32R2 20 +/* The R6 definitions shown below state that they support all previous ISAs. + This is not actually true as some instructions are removed in R6. + The problem is that the removed instructions in R6 come from different + ISAs. One approach to solve this would be to describe in the membership + field of the opcode table the different ISAs an instruction belongs to. + This would require us to create a large amount of different ISA + combinations which is hard to manage. A cleaner approach (which is + implemented here) is to say that R6 is an extension of R5 and then to + deal with the removed instructions by adding instruction exclusions + for R6 in the opcode table. */ + /* Bit INSN_ISA<X> - 1 of INSN_UPTO<Y> is set if ISA Y includes ISA X. */ + #define ISAF(X) (1 << (INSN_ISA##X - 1)) #define INSN_UPTO1 ISAF(1) #define INSN_UPTO2 INSN_UPTO1 | ISAF(2) @@ -1096,10 +1161,12 @@ struct mips_opcode | ISAF(3_32R2) | ISAF(4_32R2) | ISAF(5_32R2) #define INSN_UPTO32R3 INSN_UPTO32R2 | ISAF(32R3) #define INSN_UPTO32R5 INSN_UPTO32R3 | ISAF(32R5) +#define INSN_UPTO32R6 INSN_UPTO32R5 | ISAF(32R6) #define INSN_UPTO64 INSN_UPTO5 | ISAF(64) | ISAF(32) #define INSN_UPTO64R2 INSN_UPTO64 | ISAF(64R2) | ISAF(32R2) #define INSN_UPTO64R3 INSN_UPTO64R2 | ISAF(64R3) | ISAF(32R3) #define INSN_UPTO64R5 INSN_UPTO64R3 | ISAF(64R5) | ISAF(32R5) +#define INSN_UPTO64R6 INSN_UPTO64R5 | ISAF(64R6) | ISAF(32R6) /* The same information in table form: bit INSN_ISA<X> - 1 of index INSN_UPTO<Y> - 1 is set if ISA Y includes ISA X. */ @@ -1113,11 +1180,12 @@ static const unsigned int mips_isa_table[] = { INSN_UPTO32R2, INSN_UPTO32R3, INSN_UPTO32R5, - 0, + INSN_UPTO32R6, INSN_UPTO64, INSN_UPTO64R2, INSN_UPTO64R3, - INSN_UPTO64R5 + INSN_UPTO64R5, + INSN_UPTO64R6 }; #undef ISAF @@ -1207,6 +1275,8 @@ static const unsigned int mips_isa_table[] = { #define ISA_MIPS64R3 INSN_ISA64R3 #define ISA_MIPS64R5 INSN_ISA64R5 +#define ISA_MIPS32R6 INSN_ISA32R6 +#define ISA_MIPS64R6 INSN_ISA64R6 /* CPU defines, use instead of hardcoding processor number. Keep this in sync with bfd/archures.c in order for machine selection to work. */ @@ -1239,11 +1309,13 @@ static const unsigned int mips_isa_table[] = { #define CPU_MIPS32R2 33 #define CPU_MIPS32R3 34 #define CPU_MIPS32R5 36 +#define CPU_MIPS32R6 37 #define CPU_MIPS5 5 #define CPU_MIPS64 64 #define CPU_MIPS64R2 65 #define CPU_MIPS64R3 66 #define CPU_MIPS64R5 68 +#define CPU_MIPS64R6 69 #define CPU_SB1 12310201 /* octal 'SB', 01. */ #define CPU_LOONGSON_2E 3001 #define CPU_LOONGSON_2F 3002 @@ -1319,6 +1391,13 @@ cpu_is_member (int cpu, unsigned int mask) case CPU_XLR: return (mask & INSN_XLR) != 0; + case CPU_MIPS32R6: + return (mask & INSN_ISA_MASK) == INSN_ISA32R6; + + case CPU_MIPS64R6: + return ((mask & INSN_ISA_MASK) == INSN_ISA32R6) + || ((mask & INSN_ISA_MASK) == INSN_ISA64R6); + default: return FALSE; } @@ -2160,8 +2239,8 @@ extern const int bfd_mips16_num_opcodes; Characters used so far, for quick reference when adding more: "12345678 0" - "<>(),+.@\^|~" - "A CDEFGHI KLMN RST V " + "<>(),+-.@\^|~" + "ABCDEFGHI KLMN RST V " "abcd f hijklmnopqrstuvw yz" Extension character sequences used so far ("+" followed by the @@ -2177,6 +2256,12 @@ extern const int bfd_mips16_num_opcodes; "" " BCDEFGHIJ LMNOPQ U WXYZ" " bcdefghij lmn pq st xyz" + + Extension character sequences used so far ("-" followed by the + following), for quick reference when adding more: + "" + "" + <none so far> */ extern const struct mips_operand *decode_micromips_operand (const char *); |