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-rw-r--r--gold/ChangeLog5
-rw-r--r--gold/powerpc.cc2
2 files changed, 6 insertions, 1 deletions
diff --git a/gold/ChangeLog b/gold/ChangeLog
index 9e45c0f..8ec7014 100644
--- a/gold/ChangeLog
+++ b/gold/ChangeLog
@@ -1,3 +1,8 @@
+2019-09-20 Alan Modra <amodra@gmail.com>
+
+ * powerpc.cc (Target_powerpc::Scan::check_non_pic): Move REL24
+ to 32-bit supported.
+
2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
* testsuite/Makefile.in: Re-generate.
diff --git a/gold/powerpc.cc b/gold/powerpc.cc
index e69ce19..ad35095 100644
--- a/gold/powerpc.cc
+++ b/gold/powerpc.cc
@@ -7355,7 +7355,6 @@ Target_powerpc<size, big_endian>::Scan::check_non_pic(Relobj* object,
case elfcpp::R_POWERPC_ADDR14_BRTAKEN:
case elfcpp::R_POWERPC_ADDR14_BRNTAKEN:
case elfcpp::R_POWERPC_REL32:
- case elfcpp::R_POWERPC_REL24:
case elfcpp::R_POWERPC_TPREL16:
case elfcpp::R_POWERPC_TPREL16_LO:
case elfcpp::R_POWERPC_TPREL16_HI:
@@ -7404,6 +7403,7 @@ Target_powerpc<size, big_endian>::Scan::check_non_pic(Relobj* object,
{
// These are the relocation types supported only on 32-bit.
// ??? glibc ld.so doesn't need to support these.
+ case elfcpp::R_POWERPC_REL24:
case elfcpp::R_POWERPC_DTPREL16:
case elfcpp::R_POWERPC_DTPREL16_LO:
case elfcpp::R_POWERPC_DTPREL16_HI: