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-rw-r--r--gdb/testsuite/gdb.arch/riscv-tdesc-loading-01.xml83
-rw-r--r--gdb/testsuite/gdb.arch/riscv-tdesc-loading-02.xml81
-rw-r--r--gdb/testsuite/gdb.arch/riscv-tdesc-loading-03.xml79
-rw-r--r--gdb/testsuite/gdb.arch/riscv-tdesc-loading-04.xml77
-rw-r--r--gdb/testsuite/gdb.arch/riscv-tdesc-loading.exp39
5 files changed, 359 insertions, 0 deletions
diff --git a/gdb/testsuite/gdb.arch/riscv-tdesc-loading-01.xml b/gdb/testsuite/gdb.arch/riscv-tdesc-loading-01.xml
new file mode 100644
index 0000000..39bde20
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-tdesc-loading-01.xml
@@ -0,0 +1,83 @@
+<?xml version="1.0"?>
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>riscv</architecture>
+ <feature name="org.gnu.gdb.riscv.cpu">
+ <reg name="zero" bitsize="64" type="int"/>
+ <reg name="ra" bitsize="64" type="code_ptr"/>
+ <reg name="sp" bitsize="64" type="data_ptr"/>
+ <reg name="gp" bitsize="64" type="data_ptr"/>
+ <reg name="tp" bitsize="64" type="data_ptr"/>
+ <reg name="t0" bitsize="64" type="int"/>
+ <reg name="t1" bitsize="64" type="int"/>
+ <reg name="t2" bitsize="64" type="int"/>
+ <reg name="fp" bitsize="64" type="data_ptr"/>
+ <reg name="s1" bitsize="64" type="int"/>
+ <reg name="a0" bitsize="64" type="int"/>
+ <reg name="a1" bitsize="64" type="int"/>
+ <reg name="a2" bitsize="64" type="int"/>
+ <reg name="a3" bitsize="64" type="int"/>
+ <reg name="a4" bitsize="64" type="int"/>
+ <reg name="a5" bitsize="64" type="int"/>
+ <reg name="a6" bitsize="64" type="int"/>
+ <reg name="a7" bitsize="64" type="int"/>
+ <reg name="s2" bitsize="64" type="int"/>
+ <reg name="s3" bitsize="64" type="int"/>
+ <reg name="s4" bitsize="64" type="int"/>
+ <reg name="s5" bitsize="64" type="int"/>
+ <reg name="s6" bitsize="64" type="int"/>
+ <reg name="s7" bitsize="64" type="int"/>
+ <reg name="s8" bitsize="64" type="int"/>
+ <reg name="s9" bitsize="64" type="int"/>
+ <reg name="s10" bitsize="64" type="int"/>
+ <reg name="s11" bitsize="64" type="int"/>
+ <reg name="t3" bitsize="64" type="int"/>
+ <reg name="t4" bitsize="64" type="int"/>
+ <reg name="t5" bitsize="64" type="int"/>
+ <reg name="t6" bitsize="64" type="int"/>
+ <reg name="pc" bitsize="64" type="code_ptr"/>
+ </feature>
+ <feature name="org.gnu.gdb.riscv.fpu">
+ <union id="riscv_double">
+ <field name="float" type="ieee_single"/>
+ <field name="double" type="ieee_double"/>
+ </union>
+ <reg name="ft0" bitsize="64" type="riscv_double"/>
+ <reg name="ft1" bitsize="64" type="riscv_double"/>
+ <reg name="ft2" bitsize="64" type="riscv_double"/>
+ <reg name="ft3" bitsize="64" type="riscv_double"/>
+ <reg name="ft4" bitsize="64" type="riscv_double"/>
+ <reg name="ft5" bitsize="64" type="riscv_double"/>
+ <reg name="ft6" bitsize="64" type="riscv_double"/>
+ <reg name="ft7" bitsize="64" type="riscv_double"/>
+ <reg name="fs0" bitsize="64" type="riscv_double"/>
+ <reg name="fs1" bitsize="64" type="riscv_double"/>
+ <reg name="fa0" bitsize="64" type="riscv_double"/>
+ <reg name="fa1" bitsize="64" type="riscv_double"/>
+ <reg name="fa2" bitsize="64" type="riscv_double"/>
+ <reg name="fa3" bitsize="64" type="riscv_double"/>
+ <reg name="fa4" bitsize="64" type="riscv_double"/>
+ <reg name="fa5" bitsize="64" type="riscv_double"/>
+ <reg name="fa6" bitsize="64" type="riscv_double"/>
+ <reg name="fa7" bitsize="64" type="riscv_double"/>
+ <reg name="fs2" bitsize="64" type="riscv_double"/>
+ <reg name="fs3" bitsize="64" type="riscv_double"/>
+ <reg name="fs4" bitsize="64" type="riscv_double"/>
+ <reg name="fs5" bitsize="64" type="riscv_double"/>
+ <reg name="fs6" bitsize="64" type="riscv_double"/>
+ <reg name="fs7" bitsize="64" type="riscv_double"/>
+ <reg name="fs8" bitsize="64" type="riscv_double"/>
+ <reg name="fs9" bitsize="64" type="riscv_double"/>
+ <reg name="fs10" bitsize="64" type="riscv_double"/>
+ <reg name="fs11" bitsize="64" type="riscv_double"/>
+ <reg name="ft8" bitsize="64" type="riscv_double"/>
+ <reg name="ft9" bitsize="64" type="riscv_double"/>
+ <reg name="ft10" bitsize="64" type="riscv_double"/>
+ <reg name="ft11" bitsize="64" type="riscv_double"/>
+ </feature>
+ <feature name="org.gnu.gdb.riscv.csr">
+ <reg name="fflags" bitsize="32" type="int"/>
+ <reg name="frm" bitsize="32" type="int"/>
+ <reg name="fcsr" bitsize="32" type="int"/>
+ </feature>
+</target>
diff --git a/gdb/testsuite/gdb.arch/riscv-tdesc-loading-02.xml b/gdb/testsuite/gdb.arch/riscv-tdesc-loading-02.xml
new file mode 100644
index 0000000..db0771b
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-tdesc-loading-02.xml
@@ -0,0 +1,81 @@
+<?xml version="1.0"?>
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>riscv</architecture>
+ <feature name="org.gnu.gdb.riscv.cpu">
+ <reg name="zero" bitsize="64" type="int"/>
+ <reg name="ra" bitsize="64" type="code_ptr"/>
+ <reg name="sp" bitsize="64" type="data_ptr"/>
+ <reg name="gp" bitsize="64" type="data_ptr"/>
+ <reg name="tp" bitsize="64" type="data_ptr"/>
+ <reg name="t0" bitsize="64" type="int"/>
+ <reg name="t1" bitsize="64" type="int"/>
+ <reg name="t2" bitsize="64" type="int"/>
+ <reg name="fp" bitsize="64" type="data_ptr"/>
+ <reg name="s1" bitsize="64" type="int"/>
+ <reg name="a0" bitsize="64" type="int"/>
+ <reg name="a1" bitsize="64" type="int"/>
+ <reg name="a2" bitsize="64" type="int"/>
+ <reg name="a3" bitsize="64" type="int"/>
+ <reg name="a4" bitsize="64" type="int"/>
+ <reg name="a5" bitsize="64" type="int"/>
+ <reg name="a6" bitsize="64" type="int"/>
+ <reg name="a7" bitsize="64" type="int"/>
+ <reg name="s2" bitsize="64" type="int"/>
+ <reg name="s3" bitsize="64" type="int"/>
+ <reg name="s4" bitsize="64" type="int"/>
+ <reg name="s5" bitsize="64" type="int"/>
+ <reg name="s6" bitsize="64" type="int"/>
+ <reg name="s7" bitsize="64" type="int"/>
+ <reg name="s8" bitsize="64" type="int"/>
+ <reg name="s9" bitsize="64" type="int"/>
+ <reg name="s10" bitsize="64" type="int"/>
+ <reg name="s11" bitsize="64" type="int"/>
+ <reg name="t3" bitsize="64" type="int"/>
+ <reg name="t4" bitsize="64" type="int"/>
+ <reg name="t5" bitsize="64" type="int"/>
+ <reg name="t6" bitsize="64" type="int"/>
+ <reg name="pc" bitsize="64" type="code_ptr"/>
+ </feature>
+ <feature name="org.gnu.gdb.riscv.fpu">
+ <union id="riscv_double">
+ <field name="float" type="ieee_single"/>
+ <field name="double" type="ieee_double"/>
+ </union>
+ <reg name="ft0" bitsize="64" type="riscv_double"/>
+ <reg name="ft1" bitsize="64" type="riscv_double"/>
+ <reg name="ft2" bitsize="64" type="riscv_double"/>
+ <reg name="ft3" bitsize="64" type="riscv_double"/>
+ <reg name="ft4" bitsize="64" type="riscv_double"/>
+ <reg name="ft5" bitsize="64" type="riscv_double"/>
+ <reg name="ft6" bitsize="64" type="riscv_double"/>
+ <reg name="ft7" bitsize="64" type="riscv_double"/>
+ <reg name="fs0" bitsize="64" type="riscv_double"/>
+ <reg name="fs1" bitsize="64" type="riscv_double"/>
+ <reg name="fa0" bitsize="64" type="riscv_double"/>
+ <reg name="fa1" bitsize="64" type="riscv_double"/>
+ <reg name="fa2" bitsize="64" type="riscv_double"/>
+ <reg name="fa3" bitsize="64" type="riscv_double"/>
+ <reg name="fa4" bitsize="64" type="riscv_double"/>
+ <reg name="fa5" bitsize="64" type="riscv_double"/>
+ <reg name="fa6" bitsize="64" type="riscv_double"/>
+ <reg name="fa7" bitsize="64" type="riscv_double"/>
+ <reg name="fs2" bitsize="64" type="riscv_double"/>
+ <reg name="fs3" bitsize="64" type="riscv_double"/>
+ <reg name="fs4" bitsize="64" type="riscv_double"/>
+ <reg name="fs5" bitsize="64" type="riscv_double"/>
+ <reg name="fs6" bitsize="64" type="riscv_double"/>
+ <reg name="fs7" bitsize="64" type="riscv_double"/>
+ <reg name="fs8" bitsize="64" type="riscv_double"/>
+ <reg name="fs9" bitsize="64" type="riscv_double"/>
+ <reg name="fs10" bitsize="64" type="riscv_double"/>
+ <reg name="fs11" bitsize="64" type="riscv_double"/>
+ <reg name="ft8" bitsize="64" type="riscv_double"/>
+ <reg name="ft9" bitsize="64" type="riscv_double"/>
+ <reg name="ft10" bitsize="64" type="riscv_double"/>
+ <reg name="ft11" bitsize="64" type="riscv_double"/>
+ <reg name="fflags" bitsize="32" type="int"/>
+ <reg name="frm" bitsize="32" type="int"/>
+ <reg name="fcsr" bitsize="32" type="int"/>
+ </feature>
+</target>
diff --git a/gdb/testsuite/gdb.arch/riscv-tdesc-loading-03.xml b/gdb/testsuite/gdb.arch/riscv-tdesc-loading-03.xml
new file mode 100644
index 0000000..b4af362
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-tdesc-loading-03.xml
@@ -0,0 +1,79 @@
+<?xml version="1.0"?>
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>riscv</architecture>
+ <feature name="org.gnu.gdb.riscv.cpu">
+ <reg name="zero" bitsize="32" type="int"/>
+ <reg name="ra" bitsize="32" type="code_ptr"/>
+ <reg name="sp" bitsize="32" type="data_ptr"/>
+ <reg name="gp" bitsize="32" type="data_ptr"/>
+ <reg name="tp" bitsize="32" type="data_ptr"/>
+ <reg name="t0" bitsize="32" type="int"/>
+ <reg name="t1" bitsize="32" type="int"/>
+ <reg name="t2" bitsize="32" type="int"/>
+ <reg name="fp" bitsize="32" type="data_ptr"/>
+ <reg name="s1" bitsize="32" type="int"/>
+ <reg name="a0" bitsize="32" type="int"/>
+ <reg name="a1" bitsize="32" type="int"/>
+ <reg name="a2" bitsize="32" type="int"/>
+ <reg name="a3" bitsize="32" type="int"/>
+ <reg name="a4" bitsize="32" type="int"/>
+ <reg name="a5" bitsize="32" type="int"/>
+ <reg name="a6" bitsize="32" type="int"/>
+ <reg name="a7" bitsize="32" type="int"/>
+ <reg name="s2" bitsize="32" type="int"/>
+ <reg name="s3" bitsize="32" type="int"/>
+ <reg name="s4" bitsize="32" type="int"/>
+ <reg name="s5" bitsize="32" type="int"/>
+ <reg name="s6" bitsize="32" type="int"/>
+ <reg name="s7" bitsize="32" type="int"/>
+ <reg name="s8" bitsize="32" type="int"/>
+ <reg name="s9" bitsize="32" type="int"/>
+ <reg name="s10" bitsize="32" type="int"/>
+ <reg name="s11" bitsize="32" type="int"/>
+ <reg name="t3" bitsize="32" type="int"/>
+ <reg name="t4" bitsize="32" type="int"/>
+ <reg name="t5" bitsize="32" type="int"/>
+ <reg name="t6" bitsize="32" type="int"/>
+ <reg name="pc" bitsize="32" type="code_ptr"/>
+ </feature>
+ <feature name="org.gnu.gdb.riscv.fpu">
+ <reg name="ft0" bitsize="32" type="float"/>
+ <reg name="ft1" bitsize="32" type="float"/>
+ <reg name="ft2" bitsize="32" type="float"/>
+ <reg name="ft3" bitsize="32" type="float"/>
+ <reg name="ft4" bitsize="32" type="float"/>
+ <reg name="ft5" bitsize="32" type="float"/>
+ <reg name="ft6" bitsize="32" type="float"/>
+ <reg name="ft7" bitsize="32" type="float"/>
+ <reg name="fs0" bitsize="32" type="float"/>
+ <reg name="fs1" bitsize="32" type="float"/>
+ <reg name="fa0" bitsize="32" type="float"/>
+ <reg name="fa1" bitsize="32" type="float"/>
+ <reg name="fa2" bitsize="32" type="float"/>
+ <reg name="fa3" bitsize="32" type="float"/>
+ <reg name="fa4" bitsize="32" type="float"/>
+ <reg name="fa5" bitsize="32" type="float"/>
+ <reg name="fa6" bitsize="32" type="float"/>
+ <reg name="fa7" bitsize="32" type="float"/>
+ <reg name="fs2" bitsize="32" type="float"/>
+ <reg name="fs3" bitsize="32" type="float"/>
+ <reg name="fs4" bitsize="32" type="float"/>
+ <reg name="fs5" bitsize="32" type="float"/>
+ <reg name="fs6" bitsize="32" type="float"/>
+ <reg name="fs7" bitsize="32" type="float"/>
+ <reg name="fs8" bitsize="32" type="float"/>
+ <reg name="fs9" bitsize="32" type="float"/>
+ <reg name="fs10" bitsize="32" type="float"/>
+ <reg name="fs11" bitsize="32" type="float"/>
+ <reg name="ft8" bitsize="32" type="float"/>
+ <reg name="ft9" bitsize="32" type="float"/>
+ <reg name="ft10" bitsize="32" type="float"/>
+ <reg name="ft11" bitsize="32" type="float"/>
+ </feature>
+ <feature name="org.gnu.gdb.riscv.csr">
+ <reg name="fflags" bitsize="32" type="int"/>
+ <reg name="frm" bitsize="32" type="int"/>
+ <reg name="fcsr" bitsize="32" type="int"/>
+ </feature>
+</target>
diff --git a/gdb/testsuite/gdb.arch/riscv-tdesc-loading-04.xml b/gdb/testsuite/gdb.arch/riscv-tdesc-loading-04.xml
new file mode 100644
index 0000000..d44d7e2
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-tdesc-loading-04.xml
@@ -0,0 +1,77 @@
+<?xml version="1.0"?>
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>riscv</architecture>
+ <feature name="org.gnu.gdb.riscv.cpu">
+ <reg name="zero" bitsize="32" type="int"/>
+ <reg name="ra" bitsize="32" type="code_ptr"/>
+ <reg name="sp" bitsize="32" type="data_ptr"/>
+ <reg name="gp" bitsize="32" type="data_ptr"/>
+ <reg name="tp" bitsize="32" type="data_ptr"/>
+ <reg name="t0" bitsize="32" type="int"/>
+ <reg name="t1" bitsize="32" type="int"/>
+ <reg name="t2" bitsize="32" type="int"/>
+ <reg name="fp" bitsize="32" type="data_ptr"/>
+ <reg name="s1" bitsize="32" type="int"/>
+ <reg name="a0" bitsize="32" type="int"/>
+ <reg name="a1" bitsize="32" type="int"/>
+ <reg name="a2" bitsize="32" type="int"/>
+ <reg name="a3" bitsize="32" type="int"/>
+ <reg name="a4" bitsize="32" type="int"/>
+ <reg name="a5" bitsize="32" type="int"/>
+ <reg name="a6" bitsize="32" type="int"/>
+ <reg name="a7" bitsize="32" type="int"/>
+ <reg name="s2" bitsize="32" type="int"/>
+ <reg name="s3" bitsize="32" type="int"/>
+ <reg name="s4" bitsize="32" type="int"/>
+ <reg name="s5" bitsize="32" type="int"/>
+ <reg name="s6" bitsize="32" type="int"/>
+ <reg name="s7" bitsize="32" type="int"/>
+ <reg name="s8" bitsize="32" type="int"/>
+ <reg name="s9" bitsize="32" type="int"/>
+ <reg name="s10" bitsize="32" type="int"/>
+ <reg name="s11" bitsize="32" type="int"/>
+ <reg name="t3" bitsize="32" type="int"/>
+ <reg name="t4" bitsize="32" type="int"/>
+ <reg name="t5" bitsize="32" type="int"/>
+ <reg name="t6" bitsize="32" type="int"/>
+ <reg name="pc" bitsize="32" type="code_ptr"/>
+ </feature>
+ <feature name="org.gnu.gdb.riscv.fpu">
+ <reg name="ft0" bitsize="32" type="float"/>
+ <reg name="ft1" bitsize="32" type="float"/>
+ <reg name="ft2" bitsize="32" type="float"/>
+ <reg name="ft3" bitsize="32" type="float"/>
+ <reg name="ft4" bitsize="32" type="float"/>
+ <reg name="ft5" bitsize="32" type="float"/>
+ <reg name="ft6" bitsize="32" type="float"/>
+ <reg name="ft7" bitsize="32" type="float"/>
+ <reg name="fs0" bitsize="32" type="float"/>
+ <reg name="fs1" bitsize="32" type="float"/>
+ <reg name="fa0" bitsize="32" type="float"/>
+ <reg name="fa1" bitsize="32" type="float"/>
+ <reg name="fa2" bitsize="32" type="float"/>
+ <reg name="fa3" bitsize="32" type="float"/>
+ <reg name="fa4" bitsize="32" type="float"/>
+ <reg name="fa5" bitsize="32" type="float"/>
+ <reg name="fa6" bitsize="32" type="float"/>
+ <reg name="fa7" bitsize="32" type="float"/>
+ <reg name="fs2" bitsize="32" type="float"/>
+ <reg name="fs3" bitsize="32" type="float"/>
+ <reg name="fs4" bitsize="32" type="float"/>
+ <reg name="fs5" bitsize="32" type="float"/>
+ <reg name="fs6" bitsize="32" type="float"/>
+ <reg name="fs7" bitsize="32" type="float"/>
+ <reg name="fs8" bitsize="32" type="float"/>
+ <reg name="fs9" bitsize="32" type="float"/>
+ <reg name="fs10" bitsize="32" type="float"/>
+ <reg name="fs11" bitsize="32" type="float"/>
+ <reg name="ft8" bitsize="32" type="float"/>
+ <reg name="ft9" bitsize="32" type="float"/>
+ <reg name="ft10" bitsize="32" type="float"/>
+ <reg name="ft11" bitsize="32" type="float"/>
+ <reg name="fflags" bitsize="32" type="int"/>
+ <reg name="frm" bitsize="32" type="int"/>
+ <reg name="fcsr" bitsize="32" type="int"/>
+ </feature>
+</target>
diff --git a/gdb/testsuite/gdb.arch/riscv-tdesc-loading.exp b/gdb/testsuite/gdb.arch/riscv-tdesc-loading.exp
new file mode 100644
index 0000000..e111172
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-tdesc-loading.exp
@@ -0,0 +1,39 @@
+# Copyright 2020 Free Software Foundation, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+# Check that we can load different RISC-V target descriptions.
+
+if {![istarget "riscv*-*-*"]} {
+ verbose "Skipping ${gdb_test_file_name}."
+ return
+}
+
+clean_restart
+
+# Run over every test XML file and check the target description can be
+# loaded.
+foreach filename [lsort [glob $srcdir/$subdir/riscv-tdesc-loading-*.xml]] {
+ if {[is_remote host]} {
+ set test_path [remote_download host $filename]
+ } else {
+ set test_path $filename
+ }
+
+ # Currently it is expected that all of the target descriptions in
+ # this test will load successfully, so we expect no additonal
+ # output from GDB.
+ gdb_test_no_output "set tdesc filename $test_path" \
+ "check [file tail $filename]"
+}
generated by cgit v1.1 at 2025-01-21 12:20:09 +0000