diff options
Diffstat (limited to 'gdb/arm-tdep.c')
| -rw-r--r-- | gdb/arm-tdep.c | 1004 |
1 files changed, 555 insertions, 449 deletions
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 99139ac..71a000a 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -1,5 +1,5 @@ -/* Target-dependent code for the Acorn Risc Machine (ARM). - Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995-1999 +/* Common target dependent code for GDB on ARM systems. + Copyright 1988, 1989, 1991, 1992, 1993, 1995-1999 Free Software Foundation, Inc. This file is part of GDB. @@ -28,6 +28,8 @@ #include "gdb_string.h" #include "coff/internal.h" /* Internal format of COFF symbols in BFD */ +extern void _initialize_arm_tdep (void); + /* The following macros are actually wrong. Neither arm nor thumb can or should set the lsb on addr. @@ -42,67 +44,162 @@ #define MAKE_THUMB_ADDR(addr) ((addr) | 1) #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) -/* Macros to round N up or down to the next A boundary; A must be - a power of two. */ -#define ROUND_DOWN(n,a) ((n) & ~((a) - 1)) -#define ROUND_UP(n,a) (((n) + (a) - 1) & ~((a) - 1)) - +/* Default register names as specified by APCS. */ static char *apcs_register_names[] = -{ "a1", "a2", "a3", "a4", /* 0 1 2 3 */ - "v1", "v2", "v3", "v4", /* 4 5 6 7 */ - "v5", "v6", "sl", "fp", /* 8 9 10 11 */ - "ip", "sp", "lr", "pc", /* 12 13 14 15 */ - "f0", "f1", "f2", "f3", /* 16 17 18 19 */ - "f4", "f5", "f6", "f7", /* 20 21 22 23 */ - "fps","ps" } /* 24 25 */; - -/* These names are the ones which gcc emits, and - I find them less confusing. Toggle between them - using the `othernames' command. */ +{"a1", "a2", "a3", "a4", /* 0 1 2 3 */ + "v1", "v2", "v3", "v4", /* 4 5 6 7 */ + "v5", "v6", "sl", "fp", /* 8 9 10 11 */ + "ip", "sp", "lr", "pc", /* 12 13 14 15 */ + "f0", "f1", "f2", "f3", /* 16 17 18 19 */ + "f4", "f5", "f6", "f7", /* 20 21 22 23 */ + "fps", "ps"} /* 24 25 */ ; + +/* Alternate set of registers names used by GCC. */ static char *additional_register_names[] = -{ "r0", "r1", "r2", "r3", /* 0 1 2 3 */ - "r4", "r5", "r6", "r7", /* 4 5 6 7 */ - "r8", "r9", "r10", "r11", /* 8 9 10 11 */ - "r12", "r13", "r14", "pc", /* 12 13 14 15 */ - "f0", "f1", "f2", "f3", /* 16 17 18 19 */ - "f4", "f5", "f6", "f7", /* 20 21 22 23 */ - "fps","ps" } /* 24 25 */; - -/* By default use the APCS registers names */ - +{"r0", "r1", "r2", "r3", /* 0 1 2 3 */ + "r4", "r5", "r6", "r7", /* 4 5 6 7 */ + "r8", "r9", "r10", "r11", /* 8 9 10 11 */ + "r12", "r13", "r14", "pc", /* 12 13 14 15 */ + "f0", "f1", "f2", "f3", /* 16 17 18 19 */ + "f4", "f5", "f6", "f7", /* 20 21 22 23 */ + "fps", "ps"} /* 24 25 */ ; + +/* This is the variable that is set with "set disassembly-flavor". + By default use the APCS registers names. */ char **arm_register_names = apcs_register_names; -/* This is the variable the is set with "set disassembly-flavor", - and its legitimate values. */ + +/* Valid register name flavours. */ static char apcs_flavor[] = "apcs"; static char r_prefix_flavor[] = "r-prefix"; -static char *valid_flavors[] = { +static char *valid_flavors[] = +{ apcs_flavor, r_prefix_flavor, NULL }; + +/* Disassembly flavor to use. */ static char *disassembly_flavor = apcs_flavor; -/* This is used to keep the bfd arch_info in sync with the disassembly flavor. */ -static void set_disassembly_flavor_sfunc PARAMS ((char *, int, \ - struct cmd_list_element *)); -static void set_disassembly_flavor (); +/* This is used to keep the bfd arch_info in sync with the disassembly + flavor. */ +static void set_disassembly_flavor_sfunc(char *, int, + struct cmd_list_element *); +static void set_disassembly_flavor (void); + +static void convert_from_extended (void *ptr, void *dbl); + +/* Define other aspects of the stack frame. We keep the offsets of + all saved registers, 'cause we need 'em a lot! We also keep the + current size of the stack frame, and the offset of the frame + pointer from the stack pointer (for frameless functions, and when + we're still in the prologue of a function with a frame) */ + +struct frame_extra_info + { + struct frame_saved_regs fsr; + int framesize; + int frameoffset; + int framereg; + }; + +/* Will a function return an aggregate type in memory or in a + register? Return 0 if an aggregate type can be returned in a + register, 1 if it must be returned in memory. */ -/* Should call_function allocate stack space for a struct return? */ -/* The system C compiler uses a similar structure return convention to gcc */ int -arm_use_struct_convention (gcc_p, type) - int gcc_p; - struct type *type; +arm_use_struct_convention (int gcc_p, struct type *type) { - return (TYPE_LENGTH (type) > 4); + int nRc; + register enum type_code code; + + /* In the ARM ABI, "integer" like aggregate types are returned in + registers. For an aggregate type to be integer like, its size + must be less than or equal to REGISTER_SIZE and the offset of + each addressable subfield must be zero. Note that bit fields are + not addressable, and all addressable subfields of unions always + start at offset zero. + + This function is based on the behaviour of GCC 2.95.1. + See: gcc/arm.c: arm_return_in_memory() for details. + + Note: All versions of GCC before GCC 2.95.2 do not set up the + parameters correctly for a function returning the following + structure: struct { float f;}; This should be returned in memory, + not a register. Richard Earnshaw sent me a patch, but I do not + know of any way to detect if a function like the above has been + compiled with the correct calling convention. */ + + /* All aggregate types that won't fit in a register must be returned + in memory. */ + if (TYPE_LENGTH (type) > REGISTER_SIZE) + { + return 1; + } + + /* The only aggregate types that can be returned in a register are + structs and unions. Arrays must be returned in memory. */ + code = TYPE_CODE (type); + if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) + { + return 1; + } + + /* Assume all other aggregate types can be returned in a register. + Run a check for structures, unions and arrays. */ + nRc = 0; + + if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) + { + int i; + /* Need to check if this struct/union is "integer" like. For + this to be true, its size must be less than or equal to + REGISTER_SIZE and the offset of each addressable subfield + must be zero. Note that bit fields are not addressable, and + unions always start at offset zero. If any of the subfields + is a floating point type, the struct/union cannot be an + integer type. */ + + /* For each field in the object, check: + 1) Is it FP? --> yes, nRc = 1; + 2) Is it addressable (bitpos != 0) and + not packed (bitsize == 0)? + --> yes, nRc = 1 + */ + + for (i = 0; i < TYPE_NFIELDS (type); i++) + { + enum type_code field_type_code; + field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i)); + + /* Is it a floating point type field? */ + if (field_type_code == TYPE_CODE_FLT) + { + nRc = 1; + break; + } + + /* If bitpos != 0, then we have to care about it. */ + if (TYPE_FIELD_BITPOS (type, i) != 0) + { + /* Bitfields are not addressable. If the field bitsize is + zero, then the field is not packed. Hence it cannot be + a bitfield or any other packed type. */ + if (TYPE_FIELD_BITSIZE (type, i) == 0) + { + nRc = 1; + break; + } + } + } + } + + return nRc; } int -arm_frame_chain_valid (chain, thisframe) - CORE_ADDR chain; - struct frame_info *thisframe; +arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe) { -#define LOWEST_PC 0x20 /* the first 0x20 bytes are the trap vectors. */ return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC)); } @@ -110,48 +207,49 @@ arm_frame_chain_valid (chain, thisframe) int arm_apcs_32 = 1; -/* Flag set by arm_fix_call_dummy that tells whether the target function - is a Thumb function. This flag is checked by arm_push_arguments. - FIXME: Change the PUSH_ARGUMENTS macro (and its use in valops.c) to - pass the function address as an additional parameter. */ +/* Flag set by arm_fix_call_dummy that tells whether the target + function is a Thumb function. This flag is checked by + arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and + its use in valops.c) to pass the function address as an additional + parameter. */ static int target_is_thumb; -/* Flag set by arm_fix_call_dummy that tells whether the calling function - is a Thumb function. This flag is checked by arm_pc_is_thumb - and arm_call_dummy_breakpoint_offset. */ +/* Flag set by arm_fix_call_dummy that tells whether the calling + function is a Thumb function. This flag is checked by + arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */ static int caller_is_thumb; -/* Tell if the program counter value in MEMADDR is in a Thumb function. */ +/* Determine if the program counter specified in MEMADDR is in a Thumb + function. */ int -arm_pc_is_thumb (memaddr) - bfd_vma memaddr; +arm_pc_is_thumb (bfd_vma memaddr) { struct minimal_symbol *sym; - CORE_ADDR sp; - /* If bit 0 of the address is set, assume this is a Thumb address. */ + /* If bit 0 of the address is set, assume this is a Thumb address. */ if (IS_THUMB_ADDR (memaddr)) return 1; - /* Thumb function have a "special" bit set in minimal symbols */ + /* Thumb functions have a "special" bit set in minimal symbols. */ sym = lookup_minimal_symbol_by_pc (memaddr); if (sym) { return (MSYMBOL_IS_SPECIAL (sym)); } else - return 0; + { + return 0; + } } -/* Tell if the program counter value in MEMADDR is in a call dummy that - is being called from a Thumb function. */ +/* Determine if the program counter specified in MEMADDR is in a call + dummy being called from a Thumb function. */ int -arm_pc_is_thumb_dummy (memaddr) - bfd_vma memaddr; +arm_pc_is_thumb_dummy (bfd_vma memaddr) { CORE_ADDR sp = read_sp (); @@ -162,8 +260,7 @@ arm_pc_is_thumb_dummy (memaddr) } CORE_ADDR -arm_addr_bits_remove (val) - CORE_ADDR val; +arm_addr_bits_remove (CORE_ADDR val) { if (arm_pc_is_thumb (val)) return (val & (arm_apcs_32 ? 0xfffffffe : 0x03fffffe)); @@ -172,26 +269,24 @@ arm_addr_bits_remove (val) } CORE_ADDR -arm_saved_pc_after_call (frame) - struct frame_info *frame; +arm_saved_pc_after_call (struct frame_info *frame) { return ADDR_BITS_REMOVE (read_register (LR_REGNUM)); } int -arm_frameless_function_invocation (fi) - struct frame_info *fi; +arm_frameless_function_invocation (struct frame_info *fi) { CORE_ADDR func_start, after_prologue; int frameless; - + func_start = (get_pc_function_start ((fi)->pc) + FUNCTION_START_OFFSET); after_prologue = SKIP_PROLOGUE (func_start); - + /* There are some frameless functions whose first two instructions - follow the standard APCS form, in which case after_prologue - will be func_start + 8. */ - + follow the standard APCS form, in which case after_prologue will + be func_start + 8. */ + frameless = (after_prologue < func_start + 12); return frameless; } @@ -202,11 +297,10 @@ arm_frameless_function_invocation (fi) add r7, sp, #12 Sometimes the latter instruction may be replaced by: mov r7, sp - */ + */ static CORE_ADDR -thumb_skip_prologue (pc) - CORE_ADDR pc; +thumb_skip_prologue (CORE_ADDR pc) { CORE_ADDR current_pc; @@ -214,32 +308,31 @@ thumb_skip_prologue (pc) { unsigned short insn = read_memory_unsigned_integer (current_pc, 2); - if ((insn & 0xfe00) != 0xb400 /* push {..., r7, lr} */ - && (insn & 0xff00) != 0xb000 /* add sp, #simm */ - && (insn & 0xff00) != 0xaf00 /* add r7, sp, #imm */ - && insn != 0x466f /* mov r7, sp */ - && (insn & 0xffc0) != 0x4640) /* mov r0-r7, r8-r15 */ + if ((insn & 0xfe00) != 0xb400 /* push {..., r7, lr} */ + && (insn & 0xff00) != 0xb000 /* add sp, #simm */ + && (insn & 0xff00) != 0xaf00 /* add r7, sp, #imm */ + && insn != 0x466f /* mov r7, sp */ + && (insn & 0xffc0) != 0x4640) /* mov r0-r7, r8-r15 */ break; } return current_pc; } -/* APCS (ARM procedure call standard) defines the following prologue: +/* The APCS (ARM Procedure Call Standard) defines the following + prologue: mov ip, sp [stmfd sp!, {a1,a2,a3,a4}] stmfd sp!, {...,fp,ip,lr,pc} - [stfe f7, [sp, #-12]!] - [stfe f6, [sp, #-12]!] - [stfe f5, [sp, #-12]!] - [stfe f4, [sp, #-12]!] - sub fp, ip, #nn // nn == 20 or 4 depending on second ins - */ + [stfe f7, [sp, #-12]!] + [stfe f6, [sp, #-12]!] + [stfe f5, [sp, #-12]!] + [stfe f4, [sp, #-12]!] + sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ CORE_ADDR -arm_skip_prologue (pc) - CORE_ADDR pc; +arm_skip_prologue (CORE_ADDR pc) { unsigned long inst; CORE_ADDR skip_pc; @@ -247,7 +340,7 @@ arm_skip_prologue (pc) struct symtab_and_line sal; /* See what the symbol table says. */ - + if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) { sal = find_pc_line (func_addr, 0); @@ -281,11 +374,12 @@ arm_skip_prologue (pc) inst = read_memory_integer (skip_pc, 4); /* Any insns after this point may float into the code, if it makes - for better instruction scheduling, so we skip them only if - we find them, but still consdier the function to be frame-ful */ + for better instruction scheduling, so we skip them only if we + find them, but still consdier the function to be frame-ful. */ - /* We may have either one sfmfd instruction here, or several stfe insns, - depending on the version of floating point code we support. */ + /* We may have either one sfmfd instruction here, or several stfe + insns, depending on the version of floating point code we + support. */ if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ { skip_pc += 4; @@ -328,12 +422,8 @@ arm_skip_prologue (pc) 12 bytes. The frame register is R7. */ /* *INDENT-ON* */ - - - static void -thumb_scan_prologue (fi) - struct frame_info *fi; +thumb_scan_prologue (struct frame_info *fi) { CORE_ADDR prologue_start; CORE_ADDR prologue_end; @@ -417,9 +507,8 @@ thumb_scan_prologue (fi) } } -/* Function: check_prologue_cache - Check if prologue for this frame's PC has already been scanned. - If it has, copy the relevant information about that prologue and +/* Check if prologue for this frame's PC has already been scanned. If + it has, copy the relevant information about that prologue and return non-zero. Otherwise do not copy anything and return zero. The information saved in the cache includes: @@ -428,18 +517,16 @@ thumb_scan_prologue (fi) * the offsets of saved regs (relative to the old SP); and * the offset from the stack pointer to the frame pointer - The cache contains only one entry, since this is adequate - for the typical sequence of prologue scan requests we get. - When performing a backtrace, GDB will usually ask to scan - the same function twice in a row (once to get the frame chain, - and once to fill in the extra frame information). - */ + The cache contains only one entry, since this is adequate for the + typical sequence of prologue scan requests we get. When performing + a backtrace, GDB will usually ask to scan the same function twice + in a row (once to get the frame chain, and once to fill in the + extra frame information). */ static struct frame_info prologue_cache; static int -check_prologue_cache (fi) - struct frame_info *fi; +check_prologue_cache (struct frame_info *fi) { int i; @@ -457,13 +544,10 @@ check_prologue_cache (fi) } -/* Function: save_prologue_cache - Copy the prologue information from fi to the prologue cache. - */ +/* Copy the prologue information from fi to the prologue cache. */ static void -save_prologue_cache (fi) - struct frame_info *fi; +save_prologue_cache (struct frame_info *fi) { int i; @@ -477,8 +561,7 @@ save_prologue_cache (fi) } -/* Function: arm_scan_prologue - This function decodes an ARM function prologue to determine: +/* This function decodes an ARM function prologue to determine: 1) the size of the stack frame 2) which registers are saved on it 3) the offsets of saved regs @@ -487,20 +570,20 @@ save_prologue_cache (fi) There are two basic forms for the ARM prologue. The fixed argument function call will look like: - - mov ip, sp - stmfd sp!, {fp, ip, lr, pc} - sub fp, ip, #4 - [sub sp, sp, #4] + + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + [sub sp, sp, #4] Which would create this stack frame (offsets relative to FP): - IP -> 4 (caller's stack) - FP -> 0 PC (points to address of stmfd instruction + 8 in callee) - -4 LR (return address in caller) - -8 IP (copy of caller's SP) - -12 FP (caller's FP) - SP -> -28 Local variables - + IP -> 4 (caller's stack) + FP -> 0 PC (points to address of stmfd instruction + 8 in callee) + -4 LR (return address in caller) + -8 IP (copy of caller's SP) + -12 FP (caller's FP) + SP -> -28 Local variables + The frame size would thus be 32 bytes, and the frame offset would be 28 bytes. The stmfd call can also save any of the vN registers it plans to use, which increases the frame size accordingly. @@ -508,25 +591,25 @@ save_prologue_cache (fi) Note: The stored PC is 8 off of the STMFD instruction that stored it because the ARM Store instructions always store PC + 8 when you read the PC register. - + A variable argument function call will look like: - mov ip, sp - stmfd sp!, {a1, a2, a3, a4} - stmfd sp!, {fp, ip, lr, pc} - sub fp, ip, #20 - + mov ip, sp + stmfd sp!, {a1, a2, a3, a4} + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #20 + Which would create this stack frame (offsets relative to FP): - IP -> 20 (caller's stack) - 16 A4 - 12 A3 - 8 A2 - 4 A1 - FP -> 0 PC (points to address of stmfd instruction + 8 in callee) - -4 LR (return address in caller) - -8 IP (copy of caller's SP) - -12 FP (caller's FP) - SP -> -28 Local variables + IP -> 20 (caller's stack) + 16 A4 + 12 A3 + 8 A2 + 4 A1 + FP -> 0 PC (points to address of stmfd instruction + 8 in callee) + -4 LR (return address in caller) + -8 IP (copy of caller's SP) + -12 FP (caller's FP) + SP -> -28 Local variables The frame size would thus be 48 bytes, and the frame offset would be 28 bytes. @@ -542,12 +625,11 @@ save_prologue_cache (fi) instruction at the end of the prologue. I have never seen GCC produce this, and the ARM docs don't mention it. We still test for it below in case it happens... - -*/ + + */ static void -arm_scan_prologue (fi) - struct frame_info *fi; +arm_scan_prologue (struct frame_info *fi) { int regno, sp_offset, fp_offset; CORE_ADDR prologue_start, prologue_end, current_pc; @@ -586,17 +668,17 @@ arm_scan_prologue (fi) { /* Get address of the stmfd in the prologue of the callee; the saved PC is the address of the stmfd + 8. */ - prologue_start = ADDR_BITS_REMOVE(read_memory_integer (fi->frame, 4)) + prologue_start = ADDR_BITS_REMOVE (read_memory_integer (fi->frame, 4)) - 8; - prologue_end = prologue_start + 64; /* This is all the insn's - that could be in the prologue, - plus room for 5 insn's inserted - by the scheduler. */ + prologue_end = prologue_start + 64; /* This is all the insn's + that could be in the prologue, + plus room for 5 insn's inserted + by the scheduler. */ } /* Now search the prologue looking for instructions that set up the frame pointer, adjust the stack pointer, and save registers. - + Be careful, however, and if it doesn't look like a prologue, don't try to scan it. If, for instance, a frameless function begins with stmfd sp!, then we will tell ourselves there is @@ -609,21 +691,21 @@ arm_scan_prologue (fi) sp_offset = fp_offset = 0; - if (read_memory_unsigned_integer (prologue_start, 4) - == 0xe1a0c00d) /* mov ip, sp */ + if (read_memory_unsigned_integer (prologue_start, 4) + == 0xe1a0c00d) /* mov ip, sp */ { - for (current_pc = prologue_start +4; current_pc < prologue_end; + for (current_pc = prologue_start + 4; current_pc < prologue_end; current_pc += 4) { unsigned int insn = read_memory_unsigned_integer (current_pc, 4); - + if ((insn & 0xffff0000) == 0xe92d0000) /* stmfd sp!, {..., fp, ip, lr, pc} or stmfd sp!, {a1, a2, a3, a4} */ { int mask = insn & 0xffff; - + /* Calculate offsets of saved registers. */ for (regno = PC_REGNUM; regno >= 0; regno--) if (mask & (1 << regno)) @@ -632,47 +714,47 @@ arm_scan_prologue (fi) fi->fsr.regs[regno] = sp_offset; } } - else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ + else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ { - unsigned imm = insn & 0xff; /* immediate value */ - unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ - imm = (imm >> rot) | (imm << (32-rot)); + unsigned imm = insn & 0xff; /* immediate value */ + unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ + imm = (imm >> rot) | (imm << (32 - rot)); fp_offset = -imm; fi->framereg = FP_REGNUM; } - else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ + else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ { - unsigned imm = insn & 0xff; /* immediate value */ - unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ - imm = (imm >> rot) | (imm << (32-rot)); + unsigned imm = insn & 0xff; /* immediate value */ + unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ + imm = (imm >> rot) | (imm << (32 - rot)); sp_offset -= imm; } - else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ + else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ { sp_offset -= 12; regno = F0_REGNUM + ((insn >> 12) & 0x07); fi->fsr.regs[regno] = sp_offset; } - else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ + else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ { - int n_saved_fp_regs, i; + int n_saved_fp_regs; unsigned int fp_start_reg, fp_bound_reg; - - if ((insn & 0x800) == 0x800) /* N0 is set */ - { - if ((insn & 0x40000) == 0x40000) /* N1 is set */ + + if ((insn & 0x800) == 0x800) /* N0 is set */ + { + if ((insn & 0x40000) == 0x40000) /* N1 is set */ n_saved_fp_regs = 3; else n_saved_fp_regs = 1; } else - { - if ((insn & 0x40000) == 0x40000) /* N1 is set */ + { + if ((insn & 0x40000) == 0x40000) /* N1 is set */ n_saved_fp_regs = 2; else n_saved_fp_regs = 4; } - + fp_start_reg = F0_REGNUM + ((insn >> 12) & 0x7); fp_bound_reg = fp_start_reg + n_saved_fp_regs; for (; fp_start_reg < fp_bound_reg; fp_start_reg++) @@ -682,8 +764,9 @@ arm_scan_prologue (fi) } } else - continue; /* The optimizer might shove anything into the - prologue, so we just skip what we don't recognize. */ + /* The optimizer might shove anything into the prologue, + so we just skip what we don't recognize. */ + continue; } } @@ -692,22 +775,19 @@ arm_scan_prologue (fi) [new FP] - [new SP]. */ fi->framesize = -sp_offset; fi->frameoffset = fp_offset - sp_offset; - + save_prologue_cache (fi); } - -/* Function: find_callers_reg - Find REGNUM on the stack. Otherwise, it's in an active register. One thing - we might want to do here is to check REGNUM against the clobber mask, and - somehow flag it as invalid if it isn't saved on the stack somewhere. This - would provide a graceful failure mode when trying to get the value of - caller-saves registers for an inner frame. */ +/* Find REGNUM on the stack. Otherwise, it's in an active register. + One thing we might want to do here is to check REGNUM against the + clobber mask, and somehow flag it as invalid if it isn't saved on + the stack somewhere. This would provide a graceful failure mode + when trying to get the value of caller-saves registers for an inner + frame. */ static CORE_ADDR -arm_find_callers_reg (fi, regnum) - struct frame_info *fi; - int regnum; +arm_find_callers_reg (struct frame_info *fi, int regnum) { for (; fi; fi = fi->next) @@ -739,12 +819,8 @@ arm_find_callers_reg (fi, regnum) */ /* *INDENT-ON* */ - - - CORE_ADDR -arm_frame_chain (fi) - struct frame_info *fi; +arm_frame_chain (struct frame_info *fi) { #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ CORE_ADDR fn_start, callers_pc, fp; @@ -796,20 +872,17 @@ arm_frame_chain (fi) return fi->frame + fi->framesize; } -/* Function: init_extra_frame_info - This function actually figures out the frame address for a given pc and - sp. This is tricky because we sometimes don't use an explicit - frame pointer, and the previous stack pointer isn't necessarily recorded - on the stack. The only reliable way to get this info is to - examine the prologue. - FROMLEAF is a little confusing, it means this is the next frame up - the chain AFTER a frameless function. If this is true, then the - frame value for this frame is still in the fp register. */ +/* This function actually figures out the frame address for a given pc + and sp. This is tricky because we sometimes don't use an explicit + frame pointer, and the previous stack pointer isn't necessarily + recorded on the stack. The only reliable way to get this info is + to examine the prologue. FROMLEAF is a little confusing, it means + this is the next frame up the chain AFTER a frameless function. If + this is true, then the frame value for this frame is still in the + fp register. */ void -arm_init_extra_frame_info (fromleaf, fi) - int fromleaf; - struct frame_info * fi; +arm_init_extra_frame_info (int fromleaf, struct frame_info *fi) { int reg; @@ -836,23 +909,21 @@ arm_init_extra_frame_info (fromleaf, fi) if (!fi->next) /* this is the innermost frame? */ fi->frame = read_register (fi->framereg); - else - /* not the innermost frame */ - /* If we have an FP, the callee saved it. */ - if (fi->framereg == FP_REGNUM || fi->framereg == THUMB_FP_REGNUM) - { - if (fi->next->fsr.regs[fi->framereg] != 0) - fi->frame = - read_memory_integer (fi->next->fsr.regs[fi->framereg], 4); - else if (fromleaf) - /* If we were called by a frameless fn. then our frame - is still in the frame pointer register on the - board... */ - fi->frame = read_fp (); - } + else if (fi->framereg == FP_REGNUM || fi->framereg == THUMB_FP_REGNUM) + { + /* not the innermost frame */ + /* If we have an FP, the callee saved it. */ + if (fi->next->fsr.regs[fi->framereg] != 0) + fi->frame = + read_memory_integer (fi->next->fsr.regs[fi->framereg], 4); + else if (fromleaf) + /* If we were called by a frameless fn. then our frame is + still in the frame pointer register on the board... */ + fi->frame = read_fp (); + } - /* Calculate actual addresses of saved registers using offsets determined - by arm_scan_prologue. */ + /* Calculate actual addresses of saved registers using offsets + determined by arm_scan_prologue. */ for (reg = 0; reg < NUM_REGS; reg++) if (fi->fsr.regs[reg] != 0) fi->fsr.regs[reg] += fi->frame + fi->framesize - fi->frameoffset; @@ -860,18 +931,16 @@ arm_init_extra_frame_info (fromleaf, fi) } -/* Function: frame_saved_pc - Find the caller of this frame. We do this by seeing if LR_REGNUM is saved - in the stack anywhere, otherwise we get it from the registers. +/* Find the caller of this frame. We do this by seeing if LR_REGNUM + is saved in the stack anywhere, otherwise we get it from the + registers. The old definition of this function was a macro: #define FRAME_SAVED_PC(FRAME) \ - ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) - */ + ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */ CORE_ADDR -arm_frame_saved_pc (fi) - struct frame_info *fi; +arm_frame_saved_pc (struct frame_info *fi) { #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) @@ -884,12 +953,11 @@ arm_frame_saved_pc (fi) } } - /* Return the frame address. On ARM, it is R11; on Thumb it is R7. Examine the Program Status Register to decide which state we're in. */ CORE_ADDR -arm_target_read_fp () +arm_target_read_fp (void) { if (read_register (PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */ return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */ @@ -897,19 +965,17 @@ arm_target_read_fp () return read_register (FP_REGNUM); /* R11 if ARM */ } +/* Calculate the frame offsets of the saved registers (ARM version). */ -/* Calculate the frame offsets of the saved registers (ARM version). */ void -arm_frame_find_saved_regs (fi, regaddr) - struct frame_info *fi; - struct frame_saved_regs *regaddr; +arm_frame_find_saved_regs (struct frame_info *fi, + struct frame_saved_regs *regaddr) { memcpy (regaddr, &fi->fsr, sizeof (struct frame_saved_regs)); } - void -arm_push_dummy_frame () +arm_push_dummy_frame (void) { CORE_ADDR old_sp = read_register (SP_REGNUM); CORE_ADDR sp = old_sp; @@ -923,8 +989,8 @@ arm_push_dummy_frame () /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */ prologue_start = sp = push_word (sp, 0xe92ddfff); - /* push a pointer to the dummy prologue + 12, because when - stm instruction stores the PC, it stores the address of the stm + /* Push a pointer to the dummy prologue + 12, because when stm + instruction stores the PC, it stores the address of the stm instruction itself plus 12. */ fp = sp = push_word (sp, prologue_start + 12); sp = push_word (sp, read_register (PC_REGNUM)); /* FIXME: was PS_REGNUM */ @@ -940,8 +1006,8 @@ arm_push_dummy_frame () } /* Fix up the call dummy, based on whether the processor is currently - in Thumb or ARM mode, and whether the target function is Thumb - or ARM. There are three different situations requiring three + in Thumb or ARM mode, and whether the target function is Thumb or + ARM. There are three different situations requiring three different dummies: * ARM calling ARM: uses the call dummy in tm-arm.h, which has already @@ -951,19 +1017,12 @@ arm_push_dummy_frame () * Thumb calling anything: uses the Thumb dummy defined below, which works for calling both ARM and Thumb functions. - All three call dummies expect to receive the target function address - in R4, with the low bit set if it's a Thumb function. - */ + All three call dummies expect to receive the target function + address in R4, with the low bit set if it's a Thumb function. */ void -arm_fix_call_dummy (dummy, pc, fun, nargs, args, type, gcc_p) - char *dummy; - CORE_ADDR pc; - CORE_ADDR fun; - int nargs; - value_ptr *args; - struct type *type; - int gcc_p; +arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, + value_ptr *args, struct type *type, int gcc_p) { static short thumb_dummy[4] = { @@ -976,9 +1035,10 @@ arm_fix_call_dummy (dummy, pc, fun, nargs, args, type, gcc_p) /* Set flag indicating whether the current PC is in a Thumb function. */ caller_is_thumb = arm_pc_is_thumb (read_pc ()); - /* If the target function is Thumb, set the low bit of the function address. - And if the CPU is currently in ARM mode, patch the second instruction - of call dummy to use a BX instruction to switch to Thumb mode. */ + /* If the target function is Thumb, set the low bit of the function + address. And if the CPU is currently in ARM mode, patch the + second instruction of call dummy to use a BX instruction to + switch to Thumb mode. */ target_is_thumb = arm_pc_is_thumb (fun); if (target_is_thumb) { @@ -1003,21 +1063,20 @@ arm_fix_call_dummy (dummy, pc, fun, nargs, args, type, gcc_p) } } - /* Put the target address in r4; the call dummy will copy this to the PC. */ + /* Put the target address in r4; the call dummy will copy this to + the PC. */ write_register (4, fun); } - /* Return the offset in the call dummy of the instruction that needs - to have a breakpoint placed on it. This is the offset of the 'swi 24' - instruction, which is no longer actually used, but simply acts + to have a breakpoint placed on it. This is the offset of the 'swi + 24' instruction, which is no longer actually used, but simply acts as a place-holder now. - This implements the CALL_DUMMY_BREAK_OFFSET macro. - */ + This implements the CALL_DUMMY_BREAK_OFFSET macro. */ int -arm_call_dummy_breakpoint_offset () +arm_call_dummy_breakpoint_offset (void) { if (caller_is_thumb) return 4; @@ -1025,126 +1084,135 @@ arm_call_dummy_breakpoint_offset () return 8; } +/* Note: ScottB + + This function does not support passing parameters using the FPA + variant of the APCS. It passes any floating point arguments in the + general registers and/or on the stack. */ CORE_ADDR -arm_push_arguments (nargs, args, sp, struct_return, struct_addr) - int nargs; - value_ptr *args; - CORE_ADDR sp; - int struct_return; - CORE_ADDR struct_addr; +arm_push_arguments (int nargs, value_ptr * args, CORE_ADDR sp, + int struct_return, CORE_ADDR struct_addr) { - int argreg; - int float_argreg; - int argnum; - int stack_offset; - struct stack_arg + char *fp; + int argnum, argreg, nstack_size; + + /* Walk through the list of args and determine how large a temporary + stack is required. Need to take care here as structs may be + passed on the stack, and we have to to push them. */ + nstack_size = -4 * REGISTER_SIZE; /* Some arguments go into A1-A4. */ + if (struct_return) /* The struct address goes in A1. */ + nstack_size += REGISTER_SIZE; + + /* Walk through the arguments and add their size to nstack_size. */ + for (argnum = 0; argnum < nargs; argnum++) { - char *val; int len; - int offset; - }; - struct stack_arg *stack_args = - (struct stack_arg *) alloca (nargs * sizeof (struct stack_arg)); - int nstack_args = 0; + struct type *arg_type; + + arg_type = check_typedef (VALUE_TYPE (args[argnum])); + len = TYPE_LENGTH (arg_type); + /* ANSI C code passes float arguments as integers, K&R code + passes float arguments as doubles. Correct for this here. */ + if (TYPE_CODE_FLT == TYPE_CODE (arg_type) && REGISTER_SIZE == len) + nstack_size += FP_REGISTER_VIRTUAL_SIZE; + else + nstack_size += len; + } - /* Initialize the integer and float register pointers. */ + /* Allocate room on the stack, and initialize our stack frame + pointer. */ + fp = NULL; + if (nstack_size > 0) + { + sp -= nstack_size; + fp = (char *) sp; + } + + /* Initialize the integer argument register pointer. */ argreg = A1_REGNUM; - float_argreg = F0_REGNUM; - /* the struct_return pointer occupies the first parameter-passing reg */ + /* The struct_return pointer occupies the first parameter passing + register. */ if (struct_return) write_register (argreg++, struct_addr); - /* The offset onto the stack at which we will start copying parameters - (after the registers are used up) begins at 16 in the old ABI. - This leaves room for the "home" area for register parameters. */ - stack_offset = REGISTER_SIZE * 4; - - /* Process args from left to right. Store as many as allowed in - registers, save the rest to be pushed on the stack */ + /* Process arguments from left to right. Store as many as allowed + in the parameter passing registers (A1-A4), and save the rest on + the temporary stack. */ for (argnum = 0; argnum < nargs; argnum++) { + int len; char *val; - value_ptr arg = args[argnum]; - struct type *arg_type = check_typedef (VALUE_TYPE (arg)); - struct type *target_type = TYPE_TARGET_TYPE (arg_type); - int len = TYPE_LENGTH (arg_type); - enum type_code typecode = TYPE_CODE (arg_type); + double dbl_arg; CORE_ADDR regval; - int newarg; - - val = (char *) VALUE_CONTENTS (arg); - - /* If the argument is a pointer to a function, and it's a Thumb + enum type_code typecode; + struct type *arg_type, *target_type; + + arg_type = check_typedef (VALUE_TYPE (args[argnum])); + target_type = TYPE_TARGET_TYPE (arg_type); + len = TYPE_LENGTH (arg_type); + typecode = TYPE_CODE (arg_type); + val = (char *) VALUE_CONTENTS (args[argnum]); + + /* ANSI C code passes float arguments as integers, K&R code + passes float arguments as doubles. The .stabs record for + for ANSI prototype floating point arguments records the + type as FP_INTEGER, while a K&R style (no prototype) + .stabs records the type as FP_FLOAT. In this latter case + the compiler converts the float arguments to double before + calling the function. */ + if (TYPE_CODE_FLT == typecode && REGISTER_SIZE == len) + { + float f = *(float *) val; + dbl_arg = f; + val = (char *) &dbl_arg; + len = sizeof (double); + } +#if 0 + /* If the argument is a pointer to a function, and it is a Thumb function, set the low bit of the pointer. */ - if (typecode == TYPE_CODE_PTR - && target_type != NULL - && TYPE_CODE (target_type) == TYPE_CODE_FUNC) + if (TYPE_CODE_PTR == typecode + && NULL != target_type + && TYPE_CODE_FUNC == TYPE_CODE (target_type)) { - regval = extract_address (val, len); + CORE_ADDR regval = extract_address (val, len); if (arm_pc_is_thumb (regval)) store_address (val, len, MAKE_THUMB_ADDR (regval)); } - -#define MAPCS_FLOAT 0 /* --mapcs-float not implemented by the compiler yet */ -#if MAPCS_FLOAT - /* Up to four floating point arguments can be passed in floating - point registers on ARM (not on Thumb). */ - if (typecode == TYPE_CODE_FLT - && float_argreg <= ARM_LAST_FP_ARG_REGNUM - && !target_is_thumb) - { - /* This is a floating point value that fits entirely - in a single register. */ - regval = extract_address (val, len); - write_register (float_argreg++, regval); - } - else #endif + /* Copy the argument to general registers or the stack in + register-sized pieces. Large arguments are split between + registers and stack. */ + while (len > 0) { - /* Copy the argument to general registers or the stack in - register-sized pieces. Large arguments are split between - registers and stack. */ - while (len > 0) + int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE; + + if (argreg <= ARM_LAST_ARG_REGNUM) { - if (argreg <= ARM_LAST_ARG_REGNUM) - { - int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE; - regval = extract_address (val, partial_len); - - /* It's a simple argument being passed in a general - register. */ - write_register (argreg, regval); - argreg++; - len -= partial_len; - val += partial_len; - } - else - { - /* keep for later pushing */ - stack_args[nstack_args].val = val; - stack_args[nstack_args++].len = len; - break; - } + /* It's an argument being passed in a general register. */ + regval = extract_address (val, partial_len); + write_register (argreg++, regval); } + else + { + /* Push the arguments onto the stack. */ + write_memory ((CORE_ADDR) fp, val, REGISTER_SIZE); + fp += REGISTER_SIZE; + } + + len -= partial_len; + val += partial_len; } } - /* now do the real stack pushing, process args right to left */ - while (nstack_args--) - { - sp -= stack_args[nstack_args].len; - write_memory (sp, stack_args[nstack_args].val, - stack_args[nstack_args].len); - } /* Return adjusted stack pointer. */ return sp; } void -arm_pop_frame () +arm_pop_frame (void) { struct frame_info *frame = get_current_frame (); int regnum; @@ -1163,8 +1231,7 @@ arm_pop_frame () } static void -print_fpu_flags (flags) - int flags; +print_fpu_flags (int flags) { if (flags & (1 << 0)) fputs ("IVO ", stdout); @@ -1180,14 +1247,14 @@ print_fpu_flags (flags) } void -arm_float_info () +arm_float_info (void) { register unsigned long status = read_register (FPS_REGNUM); int type; type = (status >> 24) & 127; printf ("%s FPU type %d\n", - (status & (1<<31)) ? "Hardware" : "Software", + (status & (1 << 31)) ? "Hardware" : "Software", type); fputs ("mask: ", stdout); print_fpu_flags (status >> 16); @@ -1200,16 +1267,14 @@ arm_float_info () command, and does that. */ static void -set_disassembly_flavor_sfunc (args, from_tty, c) - char *args; - int from_tty; - struct cmd_list_element *c; +set_disassembly_flavor_sfunc (char *args, int from_tty, + struct cmd_list_element *c) { set_disassembly_flavor (); } static void -set_disassembly_flavor () +set_disassembly_flavor (void) { if (disassembly_flavor == apcs_flavor) { @@ -1221,17 +1286,17 @@ set_disassembly_flavor () { if (arm_toggle_regnames () == 1) arm_toggle_regnames (); - arm_register_names = additional_register_names; - } + arm_register_names = additional_register_names; + } } -/* arm_othernames implements the "othernames" command. This is kind of - hacky, and I prefer the set-show disassembly-flavor which is also used - for the x86 gdb. I will keep this around, however, in case anyone is - actually using it. */ +/* arm_othernames implements the "othernames" command. This is kind + of hacky, and I prefer the set-show disassembly-flavor which is + also used for the x86 gdb. I will keep this around, however, in + case anyone is actually using it. */ static void -arm_othernames () +arm_othernames (char *names, int n) { if (disassembly_flavor == r_prefix_flavor) { @@ -1245,29 +1310,80 @@ arm_othernames () } } -/* FIXME: Fill in with the 'right thing', see asm - template in arm-convert.s */ +#if 0 +/* FIXME: The generated assembler works but sucks. Instead of using + r0, r1 it pushes them on the stack, then loads them into r3, r4 and + uses those registers. I must be missing something. ScottB */ void -convert_from_extended (ptr, dbl) - void *ptr; - void *dbl; +convert_from_extended (void *ptr, void *dbl) +{ + __asm__ (" + ldfe f0,[%0] + stfd f0,[%1] " +: /* no output */ +: "r" (ptr), "r" (dbl)); +} + +void +convert_to_extended (void *dbl, void *ptr) +{ + __asm__ (" + ldfd f0,[%0] + stfe f0,[%1] " +: /* no output */ +: "r" (dbl), "r" (ptr)); +} +#else +static void +convert_from_extended (void *ptr, void *dbl) { *(double *) dbl = *(double *) ptr; } void -convert_to_extended (dbl, ptr) - void *ptr; - void *dbl; +convert_to_extended (void *dbl, void *ptr) { *(double *) ptr = *(double *) dbl; } +#endif + +/* Nonzero if register N requires conversion from raw format to + virtual format. */ + +int +arm_register_convertible (unsigned int regnum) +{ + return ((regnum - F0_REGNUM) < 8); +} + +/* Convert data from raw format for register REGNUM in buffer FROM to + virtual format with type TYPE in buffer TO. */ + +void +arm_register_convert_to_virtual (unsigned int regnum, struct type *type, + void *from, void *to) +{ + double val; + + convert_from_extended (from, &val); + store_floating (to, TYPE_LENGTH (type), val); +} + +/* Convert data from virtual format with type TYPE in buffer FROM to + raw format for register REGNUM in buffer TO. */ + +void +arm_register_convert_to_raw (unsigned int regnum, struct type *type, + void *from, void *to) +{ + double val = extract_floating (from, TYPE_LENGTH (type)); + + convert_to_extended (&val, to); +} static int -condition_true (cond, status_reg) - unsigned long cond; - unsigned long status_reg; +condition_true (unsigned long cond, unsigned long status_reg) { if (cond == INST_AL || cond == INST_NV) return 1; @@ -1300,10 +1416,10 @@ condition_true (cond, status_reg) return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); case INST_GT: return (((status_reg & FLAG_Z) == 0) && - (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); + (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); case INST_LE: return (((status_reg & FLAG_Z) != 0) || - (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); + (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); } return 1; } @@ -1318,11 +1434,8 @@ condition_true (cond, status_reg) #define ARM_PC_32 1 static unsigned long -shifted_reg_val (inst, carry, pc_val, status_reg) - unsigned long inst; - int carry; - unsigned long pc_val; - unsigned long status_reg; +shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, + unsigned long status_reg) { unsigned long res, shift; int rm = bits (inst, 0, 3); @@ -1370,12 +1483,10 @@ shifted_reg_val (inst, carry, pc_val, status_reg) return res & 0xffffffff; } - /* Return number of 1-bits in VAL. */ static int -bitcount (val) - unsigned long val; +bitcount (unsigned long val) { int nbits; for (nbits = 0; val != 0; nbits++) @@ -1383,10 +1494,8 @@ bitcount (val) return nbits; } - static CORE_ADDR -thumb_get_next_pc (pc) - CORE_ADDR pc; +thumb_get_next_pc (CORE_ADDR pc) { unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ unsigned short inst1 = read_memory_integer (pc, 2); @@ -1427,10 +1536,8 @@ thumb_get_next_pc (pc) return nextpc; } - CORE_ADDR -arm_get_next_pc (pc) - CORE_ADDR pc; +arm_get_next_pc (CORE_ADDR pc) { unsigned long pc_val; unsigned long this_instr; @@ -1570,7 +1677,7 @@ arm_get_next_pc (pc) int c = (status & FLAG_C) ? 1 : 0; unsigned long offset = (bit (this_instr, 25) - ? shifted_reg_val (this_instr, c, pc_val) + ? shifted_reg_val (this_instr, c, pc_val, status) : bits (this_instr, 0, 11)); if (bit (this_instr, 23)) @@ -1655,9 +1762,7 @@ arm_get_next_pc (pc) #include "libcoff.h" static int -gdb_print_insn_arm (memaddr, info) - bfd_vma memaddr; - disassemble_info *info; +gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) { if (arm_pc_is_thumb (memaddr)) { @@ -1695,28 +1800,16 @@ gdb_print_insn_arm (memaddr, info) return print_insn_little_arm (memaddr, info); } -/* Sequence of bytes for breakpoint instruction. */ -#define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} /* Recognized illegal opcodes */ -#define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} -#define THUMB_LE_BREAKPOINT {0xbe,0xbe} -#define THUMB_BE_BREAKPOINT {0xbe,0xbe} - -/* The following has been superseded by BREAKPOINT_FOR_PC, but - is defined merely to keep mem-break.c happy. */ -#define LITTLE_BREAKPOINT ARM_LE_BREAKPOINT -#define BIG_BREAKPOINT ARM_BE_BREAKPOINT - -/* This function implements the BREAKPOINT_FROM_PC macro. It uses the program - counter value to determine whether a 16- or 32-bit breakpoint should be - used. It returns a pointer to a string of bytes that encode a breakpoint - instruction, stores the length of the string to *lenptr, and adjusts pc - (if necessary) to point to the actual memory location where the +/* This function implements the BREAKPOINT_FROM_PC macro. It uses the + program counter value to determine whether a 16-bit or 32-bit + breakpoint should be used. It returns a pointer to a string of + bytes that encode a breakpoint instruction, stores the length of + the string to *lenptr, and adjusts the program counter (if + necessary) to point to the actual memory location where the breakpoint should be inserted. */ unsigned char * -arm_breakpoint_from_pc (pcptr, lenptr) - CORE_ADDR *pcptr; - int *lenptr; +arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) { if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr)) { @@ -1751,33 +1844,44 @@ arm_breakpoint_from_pc (pcptr, lenptr) } } } -/* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). - This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ + +/* Extract from an array REGBUF containing the (raw) register state a + function return value of type TYPE, and copy that, in virtual + format, into VALBUF. */ + +void +arm_extract_return_value (struct type *type, + char regbuf[REGISTER_BYTES], + char *valbuf) +{ + if (TYPE_CODE_FLT == TYPE_CODE (type)) + convert_from_extended (®buf[REGISTER_BYTE (F0_REGNUM)], valbuf); + else + memcpy (valbuf, ®buf[REGISTER_BYTE (A1_REGNUM)], TYPE_LENGTH (type)); +} + +/* Return non-zero if the PC is inside a thumb call thunk. */ int -arm_in_call_stub (pc, name) - CORE_ADDR pc; - char *name; +arm_in_call_stub (CORE_ADDR pc, char *name) { CORE_ADDR start_addr; - /* Find the starting address of the function containing the PC. If the - caller didn't give us a name, look it up at the same time. */ + /* Find the starting address of the function containing the PC. If + the caller didn't give us a name, look it up at the same time. */ if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) return 0; return strncmp (name, "_call_via_r", 11) == 0; } - -/* If PC is in a Thumb call or return stub, return the address of the target - PC, which is in a register. The thunk functions are called _called_via_xx, - where x is the register name. The possible names are r0-r9, sl, fp, ip, - sp, and lr. */ +/* If PC is in a Thumb call or return stub, return the address of the + target PC, which is in a register. The thunk functions are called + _called_via_xx, where x is the register name. The possible names + are r0-r9, sl, fp, ip, sp, and lr. */ CORE_ADDR -arm_skip_stub (pc) - CORE_ADDR pc; +arm_skip_stub (CORE_ADDR pc) { char *name; CORE_ADDR start_addr; @@ -1789,8 +1893,8 @@ arm_skip_stub (pc) /* Call thunks always start with "_call_via_". */ if (strncmp (name, "_call_via_", 10) == 0) { - /* Use the name suffix to determine which register contains - the target PC. */ + /* Use the name suffix to determine which register contains the + target PC. */ static char *table[15] = {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr" @@ -1801,48 +1905,50 @@ arm_skip_stub (pc) if (strcmp (&name[10], table[regno]) == 0) return read_register (regno); } + return 0; /* not a stub */ } - void -_initialize_arm_tdep () +_initialize_arm_tdep (void) { struct cmd_list_element *new_cmd; tm_print_insn = gdb_print_insn_arm; - + /* Sync the opcode insn printer with our register viewer: */ if (arm_toggle_regnames () != 1) arm_toggle_regnames (); /* Add the deprecated "othernames" command */ - + add_com ("othernames", class_obscure, arm_othernames, "Switch to the other set of register names."); /* Add the disassembly-flavor command */ - + new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class, - valid_flavors, - (char *) &disassembly_flavor, - "Set the disassembly flavor, \ + valid_flavors, + (char *) &disassembly_flavor, + "Set the disassembly flavor, \ the valid values are \"apcs\" and \"r-prefix\", \ and the default value is \"apcs\".", - &setlist); + &setlist); new_cmd->function.sfunc = set_disassembly_flavor_sfunc; - add_show_from_set(new_cmd, &showlist); - + add_show_from_set (new_cmd, &showlist); + /* ??? Maybe this should be a boolean. */ add_show_from_set (add_set_cmd ("apcs32", no_class, - var_zinteger, (char *)&arm_apcs_32, + var_zinteger, (char *) &arm_apcs_32, "Set usage of ARM 32-bit mode.\n", &setlist), - & showlist); + &showlist); } -/* Test whether the coff symbol specific value corresponds to a Thumb function */ +/* Test whether the coff symbol specific value corresponds to a Thumb + function. */ + int coff_sym_is_thumb (int val) { |