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Diffstat (limited to 'gdb/aarch64-tdep.c')
-rw-r--r--gdb/aarch64-tdep.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 1298302..b5a88cc 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -2224,11 +2224,10 @@ value_of_aarch64_user_reg (struct frame_info *frame, const void *baton)
/* Implement the "software_single_step" gdbarch method, needed to
single step through atomic sequences on AArch64. */
-static int
+static VEC (CORE_ADDR) *
aarch64_software_single_step (struct frame_info *frame)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
- struct address_space *aspace = get_frame_address_space (frame);
enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
const int insn_size = 4;
const int atomic_sequence_length = 16; /* Instruction sequence length. */
@@ -2243,13 +2242,14 @@ aarch64_software_single_step (struct frame_info *frame)
int bc_insn_count = 0; /* Conditional branch instruction count. */
int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
aarch64_inst inst;
+ VEC (CORE_ADDR) *next_pcs = NULL;
if (aarch64_decode_insn (insn, &inst, 1) != 0)
- return 0;
+ return NULL;
/* Look for a Load Exclusive instruction which begins the sequence. */
if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
- return 0;
+ return NULL;
for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
{
@@ -2258,14 +2258,14 @@ aarch64_software_single_step (struct frame_info *frame)
byte_order_for_code);
if (aarch64_decode_insn (insn, &inst, 1) != 0)
- return 0;
+ return NULL;
/* Check if the instruction is a conditional branch. */
if (inst.opcode->iclass == condbranch)
{
gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
if (bc_insn_count >= 1)
- return 0;
+ return NULL;
/* It is, so we'll try to set a breakpoint at the destination. */
breaks[1] = loc + inst.operands[0].imm.value;
@@ -2284,7 +2284,7 @@ aarch64_software_single_step (struct frame_info *frame)
/* We didn't find a closing Store Exclusive instruction, fall back. */
if (!closing_insn)
- return 0;
+ return NULL;
/* Insert breakpoint after the end of the atomic sequence. */
breaks[0] = loc + insn_size;
@@ -2299,9 +2299,9 @@ aarch64_software_single_step (struct frame_info *frame)
/* Insert the breakpoint at the end of the sequence, and one at the
destination of the conditional branch, if it exists. */
for (index = 0; index <= last_breakpoint; index++)
- insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
+ VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]);
- return 1;
+ return next_pcs;
}
struct displaced_step_closure