aboutsummaryrefslogtreecommitdiff
path: root/gas
diff options
context:
space:
mode:
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog5
-rw-r--r--gas/config/tc-arm.c8
2 files changed, 9 insertions, 4 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index e2e340c..7def377 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
+
+ * config/tc-arm.c (encode_arm_shift): Rename `index' local
+ variable to `op_index'.
+
2016-12-08 Alan Modra <amodra@gmail.com>
* configure: Regenerate.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 41ab13e..c15f3db 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -7436,14 +7436,14 @@ encode_arm_shift (int i)
/* register-shifted register. */
if (inst.operands[i].immisreg)
{
- int index;
- for (index = 0; index <= i; ++index)
+ int op_index;
+ for (op_index = 0; op_index <= i; ++op_index)
{
/* Check the operand only when it's presented. In pre-UAL syntax,
if the destination register is the same as the first operand, two
register form of the instruction can be used. */
- if (inst.operands[index].present && inst.operands[index].isreg
- && inst.operands[index].reg == REG_PC)
+ if (inst.operands[op_index].present && inst.operands[op_index].isreg
+ && inst.operands[op_index].reg == REG_PC)
as_warn (UNPRED_REG ("r15"));
}