diff options
Diffstat (limited to 'gas')
72 files changed, 949 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index aa684f7..c065699 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,79 @@ 2018-10-03 Tamar Christina <tamar.christina@arm.com> + * testsuite/gas/aarch64/sve-movprfx_1.d: New test. + * testsuite/gas/aarch64/sve-movprfx_1.s: New test. + * testsuite/gas/aarch64/sve-movprfx_10.d: New test. + * testsuite/gas/aarch64/sve-movprfx_10.l: New test. + * testsuite/gas/aarch64/sve-movprfx_10.s: New test. + * testsuite/gas/aarch64/sve-movprfx_11.d: New test. + * testsuite/gas/aarch64/sve-movprfx_11.s: New test. + * testsuite/gas/aarch64/sve-movprfx_12.d: New test. + * testsuite/gas/aarch64/sve-movprfx_12.s: New test. + * testsuite/gas/aarch64/sve-movprfx_13.d: New test. + * testsuite/gas/aarch64/sve-movprfx_13.l: New test. + * testsuite/gas/aarch64/sve-movprfx_13.s: New test. + * testsuite/gas/aarch64/sve-movprfx_14.d: New test. + * testsuite/gas/aarch64/sve-movprfx_14.l: New test. + * testsuite/gas/aarch64/sve-movprfx_14.s: New test. + * testsuite/gas/aarch64/sve-movprfx_15.d: New test. + * testsuite/gas/aarch64/sve-movprfx_15.l: New test. + * testsuite/gas/aarch64/sve-movprfx_15.s: New test. + * testsuite/gas/aarch64/sve-movprfx_16.d: New test. + * testsuite/gas/aarch64/sve-movprfx_16.s: New test. + * testsuite/gas/aarch64/sve-movprfx_17.d: New test. + * testsuite/gas/aarch64/sve-movprfx_17.l: New test. + * testsuite/gas/aarch64/sve-movprfx_17.s: New test. + * testsuite/gas/aarch64/sve-movprfx_18.d: New test. + * testsuite/gas/aarch64/sve-movprfx_18.l: New test. + * testsuite/gas/aarch64/sve-movprfx_18.s: New test. + * testsuite/gas/aarch64/sve-movprfx_19.d: New test. + * testsuite/gas/aarch64/sve-movprfx_19.s: New test. + * testsuite/gas/aarch64/sve-movprfx_2.d: New test. + * testsuite/gas/aarch64/sve-movprfx_2.l: New test. + * testsuite/gas/aarch64/sve-movprfx_2.s: New test. + * testsuite/gas/aarch64/sve-movprfx_20.d: New test. + * testsuite/gas/aarch64/sve-movprfx_20.l: New test. + * testsuite/gas/aarch64/sve-movprfx_20.s: New test. + * testsuite/gas/aarch64/sve-movprfx_21.d: New test. + * testsuite/gas/aarch64/sve-movprfx_21.s: New test. + * testsuite/gas/aarch64/sve-movprfx_22.d: New test. + * testsuite/gas/aarch64/sve-movprfx_22.l: New test. + * testsuite/gas/aarch64/sve-movprfx_22.s: New test. + * testsuite/gas/aarch64/sve-movprfx_23.d: New test. + * testsuite/gas/aarch64/sve-movprfx_23.l: New test. + * testsuite/gas/aarch64/sve-movprfx_23.s: New test. + * testsuite/gas/aarch64/sve-movprfx_24.d: New test. + * testsuite/gas/aarch64/sve-movprfx_24.l: New test. + * testsuite/gas/aarch64/sve-movprfx_24.s: New test. + * testsuite/gas/aarch64/sve-movprfx_25.d: New test. + * testsuite/gas/aarch64/sve-movprfx_25.l: New test. + * testsuite/gas/aarch64/sve-movprfx_25.s: New test. + * testsuite/gas/aarch64/sve-movprfx_26.d: New test. + * testsuite/gas/aarch64/sve-movprfx_26.l: New test. + * testsuite/gas/aarch64/sve-movprfx_26.s: New test. + * testsuite/gas/aarch64/sve-movprfx_3.d: New test. + * testsuite/gas/aarch64/sve-movprfx_3.l: New test. + * testsuite/gas/aarch64/sve-movprfx_3.s: New test. + * testsuite/gas/aarch64/sve-movprfx_4.d: New test. + * testsuite/gas/aarch64/sve-movprfx_4.l: New test. + * testsuite/gas/aarch64/sve-movprfx_4.s: New test. + * testsuite/gas/aarch64/sve-movprfx_5.d: New test. + * testsuite/gas/aarch64/sve-movprfx_5.s: New test. + * testsuite/gas/aarch64/sve-movprfx_6.d: New test. + * testsuite/gas/aarch64/sve-movprfx_6.l: New test. + * testsuite/gas/aarch64/sve-movprfx_6.s: New test. + * testsuite/gas/aarch64/sve-movprfx_7.d: New test. + * testsuite/gas/aarch64/sve-movprfx_7.l: New test. + * testsuite/gas/aarch64/sve-movprfx_7.s: New test. + * testsuite/gas/aarch64/sve-movprfx_8.d: New test. + * testsuite/gas/aarch64/sve-movprfx_8.l: New test. + * testsuite/gas/aarch64/sve-movprfx_8.s: New test. + * testsuite/gas/aarch64/sve-movprfx_9.d: New test. + * testsuite/gas/aarch64/sve-movprfx_9.l: New test. + * testsuite/gas/aarch64/sve-movprfx_9.s: New test. + +2018-10-03 Tamar Christina <tamar.christina@arm.com> + * testsuite/gas/aarch64/sve-movprfx.d: New test. * testsuite/gas/aarch64/sve-movprfx.s: New test. * testsuite/gas/aarch64/sve.d: Refactor. diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_1.d b/gas/testsuite/gas/aarch64/sve-movprfx_1.d new file mode 100644 index 0000000..6bf892f --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_1.d @@ -0,0 +1,13 @@ +#source: sve-movprfx_1.s +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 04912461 movprfx z1.s, p1/m, z3.s +[^:]+: 0497a441 neg z1.s, p1/m, z2.s +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_1.s b/gas/testsuite/gas/aarch64/sve-movprfx_1.s new file mode 100644 index 0000000..17e49bb --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_1.s @@ -0,0 +1,9 @@ +/* correct usage of movprfx. No diagnosis. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1.s, p1/m, z3.s + neg z1.s, p1/m, z2.s + ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_10.d b/gas/testsuite/gas/aarch64/sve-movprfx_10.d new file mode 100644 index 0000000..8458738 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_10.d @@ -0,0 +1,14 @@ +#source: sve-movprfx_10.s +#warning_output: sve-movprfx_10.l +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 04912401 movprfx z1.s, p1/m, z0.s +[^:]+: 04d7a441 neg z1.d, p1/m, z2.d // note: register size not compatible with previous `movprfx' at operand 1 +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_10.l b/gas/testsuite/gas/aarch64/sve-movprfx_10.l new file mode 100644 index 0000000..95aa534 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_10.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `neg z1.d,p1/m,z2.d' diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_10.s b/gas/testsuite/gas/aarch64/sve-movprfx_10.s new file mode 100644 index 0000000..2cf29bf --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_10.s @@ -0,0 +1,10 @@ +/* incorrect usage of movprfx, register size is different. + Diagnosis required. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1.s, p1/M, z0.s + neg z1.d, p1/m, z2.d + ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_11.d b/gas/testsuite/gas/aarch64/sve-movprfx_11.d new file mode 100644 index 0000000..91b5ebb --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_11.d @@ -0,0 +1,13 @@ +#source: sve-movprfx_11.s +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 0420bc01 movprfx z1, z0 +[^:]+: 04d7a041 neg z1.d, p0/m, z2.d +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_11.s b/gas/testsuite/gas/aarch64/sve-movprfx_11.s new file mode 100644 index 0000000..09b908e --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_11.s @@ -0,0 +1,10 @@ +/* Correct usage of movprfx, unpredicated movprfx, any register size allowed for + instruction at PC+4. No diagnosis required. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1, z0 + neg z1.d, p0/m, z2.d + ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_12.d b/gas/testsuite/gas/aarch64/sve-movprfx_12.d new file mode 100644 index 0000000..78d928b --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_12.d @@ -0,0 +1,13 @@ +#source: sve-movprfx_12.s +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 04902461 movprfx z1.s, p1/z, z3.s +[^:]+: 0497a441 neg z1.s, p1/m, z2.s +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_12.s b/gas/testsuite/gas/aarch64/sve-movprfx_12.s new file mode 100644 index 0000000..4e9c60b --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_12.s @@ -0,0 +1,9 @@ +/* correct usage of movprfx. No diagnosis. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1.s, p1/z, z3.s + neg z1.s, p1/m, z2.s + ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_13.d b/gas/testsuite/gas/aarch64/sve-movprfx_13.d new file mode 100644 index 0000000..a74aba2 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_13.d @@ -0,0 +1,17 @@ +#source: sve-movprfx_13.s +#warning_output: sve-movprfx_13.l +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 0420bc01 movprfx z1, z0 + +0+8 <.*>: +[^:]+: 0497a021 neg z1.s, p0/m, z1.s // note: output register of preceding `movprfx' used as input at operand 3 +[^:]+: d65f03c0 ret + diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_13.l b/gas/testsuite/gas/aarch64/sve-movprfx_13.l new file mode 100644 index 0000000..538d767 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_13.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +.*: Warning: output register of preceding `movprfx' used as input at operand 3 -- `neg z1.s,p0/m,z1.s' diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_13.s b/gas/testsuite/gas/aarch64/sve-movprfx_13.s new file mode 100644 index 0000000..f5868f3 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_13.s @@ -0,0 +1,11 @@ +/* Prefixed register used in valid sve instruction at PC+4. Label does not + change flow. Diagnostic required due to register used as input. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1, z0 +bar: + neg z1.s, p0/m, z1.s + ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_14.d b/gas/testsuite/gas/aarch64/sve-movprfx_14.d new file mode 100644 index 0000000..eaa9200 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_14.d @@ -0,0 +1,15 @@ +#source: sve-movprfx_14.s +#warning_output: sve-movprfx_14.l +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 04912461 movprfx z1.s, p1/m, z3.s +[^:]+: 0497a041 neg z1.s, p0/m, z2.s // note: predicate register differs from that in preceding `movprfx' at operand 2 +[^:]+: d65f03c0 ret + diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_14.l b/gas/testsuite/gas/aarch64/sve-movprfx_14.l new file mode 100644 index 0000000..d39228f --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_14.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +.*: Warning: predicate register differs from that in preceding `movprfx' at operand 2 -- `neg z1.s,p0/m,z2.s' diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_14.s b/gas/testsuite/gas/aarch64/sve-movprfx_14.s new file mode 100644 index 0000000..73b85c8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_14.s @@ -0,0 +1,10 @@ +/* incorrect usage of movprfx, predicate register not the same as movprfx. + Diagnosis required. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1.s, p1/m, z3.s + neg z1.s, p0/m, z2.s + ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_15.d b/gas/testsuite/gas/aarch64/sve-movprfx_15.d new file mode 100644 index 0000000..8020c7c --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_15.d @@ -0,0 +1,14 @@ +#source: sve-movprfx_15.s +#warning_output: sve-movprfx_15.l +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 04912461 movprfx z1.s, p1/m, z3.s +[^:]+: 04623061 orr z1.d, z3.d, z2.d // note: SVE `movprfx' compatible instruction expected +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_15.l b/gas/testsuite/gas/aarch64/sve-movprfx_15.l new file mode 100644 index 0000000..90fd677 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_15.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +.*: Warning: SVE `movprfx' compatible instruction expected -- `orr z1.d,z3.d,z2.d' diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_15.s b/gas/testsuite/gas/aarch64/sve-movprfx_15.s new file mode 100644 index 0000000..8a8b250 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_15.s @@ -0,0 +1,10 @@ +/* incorrect usage of movprfx, predicated instruction not followed by predicated + instruction at PC+4. Diagnosis required. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1.s, p1/m, z3.s + orr z1.d, z3.d, z2.d + ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_16.d b/gas/testsuite/gas/aarch64/sve-movprfx_16.d new file mode 100644 index 0000000..0c760cc --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_16.d @@ -0,0 +1,13 @@ +#source: sve-movprfx_16.s +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 04912461 movprfx z1.s, p1/m, z3.s +[^:]+: 6589a441 fcvt z1.s, p1/m, z2.h +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_16.s b/gas/testsuite/gas/aarch64/sve-movprfx_16.s new file mode 100644 index 0000000..0116260 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_16.s @@ -0,0 +1,10 @@ +/* movprfx's dest register must be the same width. Correct usage. No + diagnosis. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1.s, p1/m, z3.s + fcvt z1.s, p1/m, z2.h + ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_17.d b/gas/testsuite/gas/aarch64/sve-movprfx_17.d new file mode 100644 index 0000000..0101300 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_17.d @@ -0,0 +1,14 @@ +#source: sve-movprfx_17.s +#warning_output: sve-movprfx_17.l +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 04912461 movprfx z1.s, p1/m, z3.s +[^:]+: 65c9a441 fcvt z1.d, p1/m, z2.h // note: register size not compatible with previous `movprfx' at operand 1 +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_17.l b/gas/testsuite/gas/aarch64/sve-movprfx_17.l new file mode 100644 index 0000000..82dfaf0 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_17.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvt z1.d,p1/m,z2.h' diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_17.s b/gas/testsuite/gas/aarch64/sve-movprfx_17.s new file mode 100644 index 0000000..cd82c0b --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_17.s @@ -0,0 +1,10 @@ +/* movprfx's dest register must be the wider of the two. Incorrect usage. + Diagnosis required. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1.s, p1/m, z3.s + fcvt z1.d, p1/m, z2.h + ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_18.d b/gas/testsuite/gas/aarch64/sve-movprfx_18.d new file mode 100644 index 0000000..09d6fa6 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_18.d @@ -0,0 +1,14 @@ +#source: sve-movprfx_18.s +#warning_output: sve-movprfx_18.l +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 04912461 movprfx z1.s, p1/m, z3.s +[^:]+: 25a0c141 add z1.s, z1.s, #10 // note: predicated instruction expected after `movprfx' +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_18.l b/gas/testsuite/gas/aarch64/sve-movprfx_18.l new file mode 100644 index 0000000..b5ccd58 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_18.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +.*: Warning: predicated instruction expected after `movprfx' -- `add z1.s,z1.s,#10' diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_18.s b/gas/testsuite/gas/aarch64/sve-movprfx_18.s new file mode 100644 index 0000000..aac54cc --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_18.s @@ -0,0 +1,10 @@ +/* predicated movprfx must be used with a predicated SVE instruction at PC+4. + Diagnosis required. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1.s, p1/m, z3.s + add z1.s, z1.s, #10 + ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_19.d b/gas/testsuite/gas/aarch64/sve-movprfx_19.d new file mode 100644 index 0000000..8d13b46 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_19.d @@ -0,0 +1,13 @@ +#source: sve-movprfx_19.s +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 0420bc61 movprfx z1, z3 +[^:]+: 04800441 add z1.s, p1/m, z1.s, z2.s +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_19.s b/gas/testsuite/gas/aarch64/sve-movprfx_19.s new file mode 100644 index 0000000..d167d06 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_19.s @@ -0,0 +1,10 @@ +/* unpredicated movprfx can be used with a predicated SVE instruction at PC+4 + with a merging predicate. No diagnosis required. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1, z3 + add z1.s, p1/m, z1.s, z2.s + ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_2.d b/gas/testsuite/gas/aarch64/sve-movprfx_2.d new file mode 100644 index 0000000..7558a42 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_2.d @@ -0,0 +1,14 @@ +#source: sve-movprfx_2.s +#warning_output: sve-movprfx_2.l +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 0420bc01 movprfx z1, z0 +[^:]+: 0497a042 neg z2.s, p0/m, z2.s // note: output register of preceding `movprfx' not used in current instruction at operand 1 +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_2.l b/gas/testsuite/gas/aarch64/sve-movprfx_2.l new file mode 100644 index 0000000..9a194dc --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_2.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +.*: Warning: output register of preceding `movprfx' not used in current instruction at operand 1 -- `neg z2.s,p0/m,z2.s' diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_2.s b/gas/testsuite/gas/aarch64/sve-movprfx_2.s new file mode 100644 index 0000000..ad08b10 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_2.s @@ -0,0 +1,10 @@ +/* Prefixed register not used in valid sve instruction at PC+4. + Diagnostic required. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1, z0 + neg z2.s, p0/m, z2.s + ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_20.d b/gas/testsuite/gas/aarch64/sve-movprfx_20.d new file mode 100644 index 0000000..ae7dda6 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_20.d @@ -0,0 +1,14 @@ +#source: sve-movprfx_20.s +#warning_output: sve-movprfx_20.l +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 0420bc61 movprfx z1, z3 +[^:]+: 04a20041 add z1.s, z2.s, z2.s // note: SVE `movprfx' compatible instruction expected +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_20.l b/gas/testsuite/gas/aarch64/sve-movprfx_20.l new file mode 100644 index 0000000..6feb7ad5 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_20.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +.*: Warning: SVE `movprfx' compatible instruction expected -- `add z1.s,z2.s,z2.s' diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_20.s b/gas/testsuite/gas/aarch64/sve-movprfx_20.s new file mode 100644 index 0000000..3267034 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_20.s @@ -0,0 +1,11 @@ +/* unpredicated movprfx cannot be used with a unpredicated SVE instruction at + PC+4 that is not valid for use following a movprfx. + Diagnosis required. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1, z3 + add z1.s, z2.s, z2.s + ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_21.d b/gas/testsuite/gas/aarch64/sve-movprfx_21.d new file mode 100644 index 0000000..ea53dbe --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_21.d @@ -0,0 +1,13 @@ +#source: sve-movprfx_21.s +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 0420bc61 movprfx z1, z3 +[^:]+: 04800441 add z1.s, p1/m, z1.s, z2.s +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_21.s b/gas/testsuite/gas/aarch64/sve-movprfx_21.s new file mode 100644 index 0000000..ea61821 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_21.s @@ -0,0 +1,10 @@ +/* movprfx dest register can be used in destructive operations where required. + Valid usage. No diagnosis required. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1, z3 + add z1.s, p1/m, z1.s, z2.s + ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_22.d b/gas/testsuite/gas/aarch64/sve-movprfx_22.d new file mode 100644 index 0000000..431d5b6 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_22.d @@ -0,0 +1,14 @@ +#source: sve-movprfx_22.s +#warning_output: sve-movprfx_22.l +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 0420bc61 movprfx z1, z3 +[^:]+: 04800421 add z1.s, p1/m, z1.s, z1.s // note: output register of preceding `movprfx' used as input at operand 4 +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_22.l b/gas/testsuite/gas/aarch64/sve-movprfx_22.l new file mode 100644 index 0000000..8e3da22 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_22.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +.*: Warning: output register of preceding `movprfx' used as input at operand 4 -- `add z1.s,p1/m,z1.s,z1.s' diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_22.s b/gas/testsuite/gas/aarch64/sve-movprfx_22.s new file mode 100644 index 0000000..8ceced0 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_22.s @@ -0,0 +1,10 @@ +/* movprfx dest register can be used in destructive operations where required, + but no where else. Invalid usage. Diagnosis required. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1, z3 + add z1.s, p1/m, z1.s, z1.s + ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_23.d b/gas/testsuite/gas/aarch64/sve-movprfx_23.d new file mode 100644 index 0000000..af3c5ed --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_23.d @@ -0,0 +1,51 @@ +#source: sve-movprfx_23.s +#warning_output: sve-movprfx_23.l +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 04512461 movprfx z1.h, p1/m, z3.h +[^:]+: 256c8021 incp z1.h, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 04912461 movprfx z1.s, p1/m, z3.s +[^:]+: 25ac8021 incp z1.s, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d +[^:]+: 25ec8021 incp z1.d, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 04512461 movprfx z1.h, p1/m, z3.h +[^:]+: 256d8021 decp z1.h, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 04912461 movprfx z1.s, p1/m, z3.s +[^:]+: 25ad8021 decp z1.s, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d +[^:]+: 25ed8021 decp z1.d, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 04512461 movprfx z1.h, p1/m, z3.h +[^:]+: 25688021 sqincp z1.h, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 04912461 movprfx z1.s, p1/m, z3.s +[^:]+: 25a88021 sqincp z1.s, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d +[^:]+: 25e88021 sqincp z1.d, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 04512461 movprfx z1.h, p1/m, z3.h +[^:]+: 256a8021 sqdecp z1.h, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 04912461 movprfx z1.s, p1/m, z3.s +[^:]+: 25aa8021 sqdecp z1.s, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d +[^:]+: 25ea8021 sqdecp z1.d, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 04112461 movprfx z1.b, p1/m, z3.b +[^:]+: 05288421 clasta z1.b, p1, z1.b, z1.b // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 04512461 movprfx z1.h, p1/m, z3.h +[^:]+: 05688421 clasta z1.h, p1, z1.h, z1.h // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 04912461 movprfx z1.s, p1/m, z3.s +[^:]+: 05a88421 clasta z1.s, p1, z1.s, z1.s // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d +[^:]+: 05e88421 clasta z1.d, p1, z1.d, z1.d // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 04112461 movprfx z1.b, p1/m, z3.b +[^:]+: 05298421 clastb z1.b, p1, z1.b, z1.b // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 04512461 movprfx z1.h, p1/m, z3.h +[^:]+: 05698421 clastb z1.h, p1, z1.h, z1.h // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 04912461 movprfx z1.s, p1/m, z3.s +[^:]+: 05a98421 clastb z1.s, p1, z1.s, z1.s // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d +[^:]+: 05e98421 clastb z1.d, p1, z1.d, z1.d // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_23.l b/gas/testsuite/gas/aarch64/sve-movprfx_23.l new file mode 100644 index 0000000..ff25ee7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_23.l @@ -0,0 +1,21 @@ +[^:]*: Assembler messages: +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `incp z1.h,p1' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `incp z1.s,p1' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `incp z1.d,p1' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `decp z1.h,p1' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `decp z1.s,p1' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `decp z1.d,p1' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqincp z1.h,p1' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqincp z1.s,p1' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqincp z1.d,p1' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqdecp z1.h,p1' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqdecp z1.s,p1' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqdecp z1.d,p1' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clasta z1.b,p1,z1.b,z1.b' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clasta z1.h,p1,z1.h,z1.h' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clasta z1.s,p1,z1.s,z1.s' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clasta z1.d,p1,z1.d,z1.d' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clastb z1.b,p1,z1.b,z1.b' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clastb z1.h,p1,z1.h,z1.h' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clastb z1.s,p1,z1.s,z1.s' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clastb z1.d,p1,z1.d,z1.d' diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_23.s b/gas/testsuite/gas/aarch64/sve-movprfx_23.s new file mode 100644 index 0000000..709d81a --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_23.s @@ -0,0 +1,34 @@ +/* Instructions not allowed to be used with predicated movprfx. Invalid usage. + Diagnosis required. */ + .text + .arch armv8-a+sve + + /* All of these should be invalid because the predicated movprfx is used + with an unpredicated instruction. */ + + .macro test_sametwo inst + .irp sz, h,s,d + movprfx z1.\sz, p1/m, z3.\sz + \inst z1.\sz, p1 + .endr + .endm + + .macro test_samethree inst + .irp sz, b,h,s,d + movprfx z1.\sz, p1/m, z3.\sz + \inst z1.\sz, p1, z1.\sz, z1.\sz + .endr + .endm + + +f: + test_sametwo incp + test_sametwo decp + + test_sametwo sqincp + test_sametwo sqdecp + + test_samethree clasta + test_samethree clastb + ret + diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_24.d b/gas/testsuite/gas/aarch64/sve-movprfx_24.d new file mode 100644 index 0000000..b70d59e --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_24.d @@ -0,0 +1,25 @@ +#source: sve-movprfx_24.s +#warning_output: sve-movprfx_24.l +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d +[^:]+: 04db0441 bic z1.d, p1/m, z1.d, z2.d +[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d +[^:]+: 04e23021 bic z1.d, z1.d, z2.d // note: SVE `movprfx' compatible instruction expected +[^:]+: 0420bc61 movprfx z1, z3 +[^:]+: 04e23021 bic z1.d, z1.d, z2.d // note: SVE `movprfx' compatible instruction expected +[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d +[^:]+: 0583e7a1 and z1.d, z1.d, #0xfffffffffffffff3 // note: predicated instruction expected after `movprfx' +[^:]+: 0420bc61 movprfx z1, z3 +[^:]+: 0583e7a1 and z1.d, z1.d, #0xfffffffffffffff3 +[^:]+: 0420bc61 movprfx z1, z3 +[^:]+: 0543e7a1 eor z1.d, z1.d, #0xfffffffffffffff3 +[^:]+: 0420bc61 movprfx z1, z3 +[^:]+: 0503f021 orr z1.d, z1.d, #0xc +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_24.l b/gas/testsuite/gas/aarch64/sve-movprfx_24.l new file mode 100644 index 0000000..5b9e0fd --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_24.l @@ -0,0 +1,4 @@ +[^:]*: Assembler messages: +.*: Warning: SVE `movprfx' compatible instruction expected -- `bic z1.D,z1.D,z2.D' +.*: Warning: SVE `movprfx' compatible instruction expected -- `bic z1.D,z1.D,z2.D' +.*: Warning: predicated instruction expected after `movprfx' -- `bic z1.D,z1.D,#12' diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_24.s b/gas/testsuite/gas/aarch64/sve-movprfx_24.s new file mode 100644 index 0000000..d0f446b --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_24.s @@ -0,0 +1,36 @@ +/* Only predicated vector BIC is allowed following a movprfx, and some pseudo + instructions should be allowed due to the instructions they alias. + Has invalid usages. Diagnosis required. */ + .text + .arch armv8-a+sve + +f: + /* OK, vectored predicated. */ + movprfx z1.D, p1/m, z3.D + bic z1.D, p1/M, z1.D, z2.D + + /* Not OK, vectored unpredicated. */ + movprfx z1.D, p1/m, z3.D + bic z1.D, z1.D, z2.D + + /* Not OK, vectored unpredicated. */ + movprfx z1, z3 + bic z1.D, z1.D, z2.D + + /* Not OK, immediate form, unpredicated. */ + movprfx z1.D, p1/m, z3.D + bic z1.D, z1.D, #12 + + /* OK, immediate form alias of AND which is allowed. */ + movprfx z1, z3 + bic z1.D, z1.D, #12 + + /* OK, immediate form alias of EOR which is allowed. */ + movprfx z1, z3 + eon z1.D, z1.D, #12 + + /* OK, immediate form alias of ORR which is allowed. */ + movprfx z1, z3 + orr z1.D, z1.D, #12 + ret + diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_25.d b/gas/testsuite/gas/aarch64/sve-movprfx_25.d new file mode 100644 index 0000000..1573856 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_25.d @@ -0,0 +1,29 @@ +#source: sve-movprfx_25.s +#warning_output: sve-movprfx_25.l +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d +[^:]+: 05d14181 mov z1.d, p1/m, #12 +[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d +[^:]+: 05d14001 mov z1.d, p1/m, #0 +[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d +[^:]+: 05d14001 mov z1.d, p1/m, #0 +[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d +[^:]+: 05d94181 mov z1.d, p9/m, #12 // note: predicate register differs from that in preceding `movprfx' at operand 2 +[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d +[^:]+: 05d10181 mov z1.d, p1/z, #12 // note: merging predicate expected due to preceding `movprfx' at operand 2 +[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d +[^:]+: 05e8a441 mov z1.d, p1/m, x2 +[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d +[^:]+: 05e8a421 mov z1.d, p1/m, x1 // note: output register of preceding `movprfx' used as input at operand 3 +[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d +[^:]+: 05e08441 mov z1.d, p1/m, d2 +[^:]+: 04d12461 movprfx z1.d, p1/m, z3.d +[^:]+: 05e08421 mov z1.d, p1/m, d1 // note: output register of preceding `movprfx' used as input at operand 3 +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_25.l b/gas/testsuite/gas/aarch64/sve-movprfx_25.l new file mode 100644 index 0000000..ec7e2db --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_25.l @@ -0,0 +1,5 @@ +[^:]*: Assembler messages: +.*: Warning: predicate register differs from that in preceding `movprfx' at operand 2 -- `cpy z1.d,p9/m,#12' +.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `cpy z1.d,p1/z,#12' +.*: Warning: output register of preceding `movprfx' used as input at operand 3 -- `cpy z1.d,p1/m,x1' +.*: Warning: output register of preceding `movprfx' used as input at operand 3 -- `cpy z1.d,p1/m,d1' diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_25.s b/gas/testsuite/gas/aarch64/sve-movprfx_25.s new file mode 100644 index 0000000..58124ce --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_25.s @@ -0,0 +1,45 @@ +/* Checks that CPY is allowed after a movprfx, special case in that SIMD&Scalar + version is also valid and Pg is 4 bits rather than 3. + Has invalid usages. Diagnosis required. */ + .text + .arch armv8-a+sve + +f: + /* OK, immediate predicated, alias mov. */ + movprfx z1.d, p1/m, z3.d + cpy z1.d, p1/m, #12 + + /* OK, immediate predicated, alias mov, fmov. */ + movprfx z1.d, p1/m, z3.d + cpy z1.d, p1/m, #0 + + /* OK, immediate predicated, alias mov. */ + movprfx z1.d, p1/m, z3.d + fmov z1.d, p1/m, #0 + + /* Not OK, immediate predicated, but different predicate registers. */ + movprfx z1.d, p1/m, z3.d + cpy z1.d, p9/m, #12 + + /* Not OK, zeroing predicate. */ + movprfx z1.d, p1/m, z3.d + cpy z1.d, p1/z, #12 + + /* OK, scalar predicated, alias mov. */ + movprfx z1.d, p1/m, z3.d + cpy z1.d, p1/m, x2 + + /* Not OK, scalar but register z1 and x1 are architecturally the same. */ + movprfx z1.d, p1/m, z3.d + cpy z1.d, p1/m, x1 + + /* OK, SIMD&FP predicated, alias mov */ + movprfx z1.d, p1/m, z3.d + cpy z1.d, p1/m, d2 + + /* Not OK, SIMD&FP predicated, but register d1 is architecturally the + same. */ + movprfx z1.d, p1/m, z3.d + cpy z1.d, p1/m, d1 + ret + diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_26.d b/gas/testsuite/gas/aarch64/sve-movprfx_26.d new file mode 100644 index 0000000..00bafdc --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_26.d @@ -0,0 +1,23 @@ +#source: sve-movprfx_26.s +#warning_output: sve-movprfx_26.l +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 04912420 movprfx z0.s, p1/m, z1.s +[^:]+: 65caa440 fcvt z0.s, p1/m, z2.d // note: register size not compatible with previous `movprfx' at operand 1 +[^:]+: 04d12420 movprfx z0.d, p1/m, z1.d +[^:]+: 65caa440 fcvt z0.s, p1/m, z2.d +[^:]+: 04912420 movprfx z0.s, p1/m, z1.s +[^:]+: 65cba440 fcvt z0.d, p1/m, z2.s // note: register size not compatible with previous `movprfx' at operand 1 +[^:]+: 04d12420 movprfx z0.d, p1/m, z1.d +[^:]+: 65cba440 fcvt z0.d, p1/m, z2.s +[^:]+: 04112420 movprfx z0.b, p1/m, z1.b +[^:]+: 041b8440 lsl z0.b, p1/m, z0.b, z2.d +[^:]+: 04d12420 movprfx z0.d, p1/m, z1.d +[^:]+: 041b8440 lsl z0.b, p1/m, z0.b, z2.d // note: register size not compatible with previous `movprfx' at operand 1 +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_26.l b/gas/testsuite/gas/aarch64/sve-movprfx_26.l new file mode 100644 index 0000000..695f90f --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_26.l @@ -0,0 +1,4 @@ +[^:]*: Assembler messages: +.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvt Z0.S,P1/M,Z2.D' +.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvt Z0.D,P1/M,Z2.S' +.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `lsl Z0.B,P1/M,Z0.B,Z2.D'
\ No newline at end of file diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_26.s b/gas/testsuite/gas/aarch64/sve-movprfx_26.s new file mode 100644 index 0000000..15f52db --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_26.s @@ -0,0 +1,31 @@ +/* Checks the special cases for FCVT and LSL. + Has invalid usages. Diagnosis required. */ + .text + .arch armv8-a+sve + +f: + /* Not OK, 64-bit operation, upper 32-bits cleared. */ + movprfx Z0.S, P1/M, Z1.S + fcvt Z0.S, P1/M, Z2.D + + /* OK, 64-bit operation, upper 32-bits cleared. */ + movprfx Z0.D, P1/M, Z1.D + fcvt Z0.S, P1/M, Z2.D + + /* Not OK, 64-bit operation ignoring 32-bits. */ + movprfx Z0.S, P1/M, Z1.S + fcvt Z0.D, P1/M, Z2.S + + /* OK, 64-bit operation ignoring 32-bits. */ + movprfx Z0.D, P1/M, Z1.D + fcvt Z0.D, P1/M, Z2.S + + /* OK, 8-bit operation. */ + movprfx Z0.B, P1/M, Z1.B + lsl Z0.B, P1/M, Z0.B, Z2.D + + /* Not Ok, destination register sizes don't match. */ + movprfx Z0.D, P1/M, Z1.D + lsl Z0.B, P1/M, Z0.B, Z2.D + ret + diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_3.d b/gas/testsuite/gas/aarch64/sve-movprfx_3.d new file mode 100644 index 0000000..d56ad28 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_3.d @@ -0,0 +1,14 @@ +#source: sve-movprfx_3.s +#warning_output: sve-movprfx_3.l +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 0420bc01 movprfx z1, z0 +[^:]+: 0497a021 neg z1.s, p0/m, z1.s // note: output register of preceding `movprfx' used as input at operand 3 +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_3.l b/gas/testsuite/gas/aarch64/sve-movprfx_3.l new file mode 100644 index 0000000..538d767 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_3.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +.*: Warning: output register of preceding `movprfx' used as input at operand 3 -- `neg z1.s,p0/m,z1.s' diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_3.s b/gas/testsuite/gas/aarch64/sve-movprfx_3.s new file mode 100644 index 0000000..b6d0c8b --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_3.s @@ -0,0 +1,10 @@ +/* Prefixed register used as input on valid sve instruction at PC+4. + Diagnostic required. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1, z0 + neg z1.s, p0/m, z1.s + ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_4.d b/gas/testsuite/gas/aarch64/sve-movprfx_4.d new file mode 100644 index 0000000..056d67d --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_4.d @@ -0,0 +1,12 @@ +#source: sve-movprfx_4.s +#warning_output: sve-movprfx_4.l +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 0420bc01 movprfx z1, z0 diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_4.l b/gas/testsuite/gas/aarch64/sve-movprfx_4.l new file mode 100644 index 0000000..277a6d9 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_4.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +.*: Warning: previous `movprfx' sequence has not been closed diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_4.s b/gas/testsuite/gas/aarch64/sve-movprfx_4.s new file mode 100644 index 0000000..d5d4ffc --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_4.s @@ -0,0 +1,8 @@ +/* Prefixed register not used, movprfx last instruction. + Diagnostic required. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1, z0 diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_5.d b/gas/testsuite/gas/aarch64/sve-movprfx_5.d new file mode 100644 index 0000000..99f5a01 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_5.d @@ -0,0 +1,15 @@ +#source: sve-movprfx_5.s +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 0420bc01 movprfx z1, z0 + +0+8 <.*>: +[^:]+: 0497a041 neg z1.s, p0/m, z2.s +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_5.s b/gas/testsuite/gas/aarch64/sve-movprfx_5.s new file mode 100644 index 0000000..c4aabd9 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_5.s @@ -0,0 +1,11 @@ +/* Prefixed register used in valid sve instruction at PC+4. Label does not + change flow. No Diagnostic. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1, z0 +bar: + neg z1.s, p0/m, z2.s + ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_6.d b/gas/testsuite/gas/aarch64/sve-movprfx_6.d new file mode 100644 index 0000000..92e574c --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_6.d @@ -0,0 +1,15 @@ +#source: sve-movprfx_6.s +#warning_output: sve-movprfx_6.l +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 0420bc01 movprfx z1, z0 +[^:]+: 0420bc62 movprfx z2, z3 // note: instruction opens new dependency sequence without ending previous one +[^:]+: 0497a042 neg z2.s, p0/m, z2.s // note: output register of preceding `movprfx' used as input at operand 3 +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_6.l b/gas/testsuite/gas/aarch64/sve-movprfx_6.l new file mode 100644 index 0000000..51ad18b --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_6.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +.*: Warning: instruction opens new dependency sequence without ending previous one -- `movprfx z2,z3' +.*: Warning: output register of preceding `movprfx' used as input at operand 3 -- `neg z2.s,p0/m,z2.s' diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_6.s b/gas/testsuite/gas/aarch64/sve-movprfx_6.s new file mode 100644 index 0000000..03df04f --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_6.s @@ -0,0 +1,12 @@ +/* Prefixed register used in valid sve instruction at PC+4, but used as input + as well. Prefix block opened twice without closing first one. + Two diagnosis required. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1, z0 + movprfx z2, z3 + neg z2.s, p0/m, z2.s + ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_7.d b/gas/testsuite/gas/aarch64/sve-movprfx_7.d new file mode 100644 index 0000000..ce35370 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_7.d @@ -0,0 +1,17 @@ +#source: sve-movprfx_7.s +#warning_output: sve-movprfx_7.l +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 0420bc01 movprfx z1, z0 + +Disassembly of section .*: + +0+ <.*>: +[^:]+: d65f03c0 ret // note: previous `movprfx' sequence not closed
\ No newline at end of file diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_7.l b/gas/testsuite/gas/aarch64/sve-movprfx_7.l new file mode 100644 index 0000000..277a6d9 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_7.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +.*: Warning: previous `movprfx' sequence has not been closed diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_7.s b/gas/testsuite/gas/aarch64/sve-movprfx_7.s new file mode 100644 index 0000000..a913cea --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_7.s @@ -0,0 +1,10 @@ +/* New section started without sequence closed. Diagnostic required. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1, z0 + .section foo +g: + ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_8.d b/gas/testsuite/gas/aarch64/sve-movprfx_8.d new file mode 100644 index 0000000..d7f8bba --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_8.d @@ -0,0 +1,18 @@ +#source: sve-movprfx_8.s +#warning_output: sve-movprfx_8.l +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 0420bc01 movprfx z1, z0 + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 0497a041 neg z1.s, p0/m, z2.s // note: previous `movprfx' sequence not closed +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_8.l b/gas/testsuite/gas/aarch64/sve-movprfx_8.l new file mode 100644 index 0000000..277a6d9 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_8.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +.*: Warning: previous `movprfx' sequence has not been closed diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_8.s b/gas/testsuite/gas/aarch64/sve-movprfx_8.s new file mode 100644 index 0000000..711a8fc --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_8.s @@ -0,0 +1,10 @@ +/* New section started without sequence closed. Diagnostic required. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1, z0 + .section foo + neg z1.s, p0/m, z2.s + ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_9.d b/gas/testsuite/gas/aarch64/sve-movprfx_9.d new file mode 100644 index 0000000..0a316de --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_9.d @@ -0,0 +1,15 @@ +#source: sve-movprfx_9.s +#warning_output: sve-movprfx_9.l +#as: -march=armv8-a+sve -I$srcdir/$subdir +#objdump: -Dr -M notes + +.* file format .* + +Disassembly of section .*: + +0+ <.*>: +[^:]+: 2598e3e0 ptrue p0.s +[^:]+: 0420bc01 movprfx z1, z0 +[^:]+: 910003e0 mov x0, sp // note: SVE instruction expected after `movprfx' +[^:]+: 0497a042 neg z2.s, p0/m, z2.s +[^:]+: d65f03c0 ret diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_9.l b/gas/testsuite/gas/aarch64/sve-movprfx_9.l new file mode 100644 index 0000000..28d9ec2 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_9.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +.*: Warning: SVE instruction expected after `movprfx' -- `mov x0,sp' diff --git a/gas/testsuite/gas/aarch64/sve-movprfx_9.s b/gas/testsuite/gas/aarch64/sve-movprfx_9.s new file mode 100644 index 0000000..8e011c3 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sve-movprfx_9.s @@ -0,0 +1,11 @@ +/* Instruction at PC+4 after prefix sequence opening is not an SVE instruction. + Diagnostic required. */ + .text + .arch armv8-a+sve + +f: + ptrue p0.s + movprfx z1, z0 + mov x0, sp + neg z2.s, p0/m, z2.s + ret |