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-rw-r--r--gas/ChangeLog10
-rw-r--r--gas/config/tc-arm.c15
-rw-r--r--gas/testsuite/gas/arm/csdb.d10
-rw-r--r--gas/testsuite/gas/arm/csdb.s6
-rw-r--r--gas/testsuite/gas/arm/thumb2_it_bad.l1
-rw-r--r--gas/testsuite/gas/arm/thumb2_it_bad.s2
6 files changed, 44 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index d00ccb2..287656b 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,15 @@
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
+ * config/tc-arm.c (insns): Add csdb, enable for Armv3 and above
+ in Arm execution state, and Armv6T2 and above in Thumb execution
+ state.
+ * testsuite/gas/arm/csdb.s: New.
+ * testsuite/gas/arm/csdb.d: New.
+ * testsuite/gas/arm/thumb2_it_bad.l: Add csdb.
+ * testsuite/gas/arm/thumb2_it_bad.s: Add csdb.
+
+2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
+
* testsuite/gas/aarch64/system.d: Update expected results to expect
CSDB for hint 0x14.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 85f74a8..0b81c19 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -11275,6 +11275,12 @@ do_t_clz (void)
}
static void
+do_t_csdb (void)
+{
+ set_it_insn_type (OUTSIDE_IT_INSN);
+}
+
+static void
do_t_cps (void)
{
set_it_insn_type (OUTSIDE_IT_INSN);
@@ -19984,6 +19990,15 @@ static const struct asm_opcode insns[] =
TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
+#undef ARM_VARIANT
+#define ARM_VARIANT & arm_ext_v3
+#undef THUMB_VARIANT
+#define THUMB_VARIANT & arm_ext_v6t2
+
+ TUE("csdb", 320f014, f3af8014, 0, (), noargs, t_csdb),
+
+#undef ARM_VARIANT
+#define ARM_VARIANT & arm_ext_v6t2
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_v6t2_v8m
TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
diff --git a/gas/testsuite/gas/arm/csdb.d b/gas/testsuite/gas/arm/csdb.d
new file mode 100644
index 0000000..baf5855
--- /dev/null
+++ b/gas/testsuite/gas/arm/csdb.d
@@ -0,0 +1,10 @@
+#name: CSDB
+#source: csdb.s
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]*> f3af 8014 ? csdb
+0+004 <[^>]*> e320f014 ? csdb
+
diff --git a/gas/testsuite/gas/arm/csdb.s b/gas/testsuite/gas/arm/csdb.s
new file mode 100644
index 0000000..133a5f0
--- /dev/null
+++ b/gas/testsuite/gas/arm/csdb.s
@@ -0,0 +1,6 @@
+.text
+.thumb
+.syntax unified
+csdb
+.arm
+csdb
diff --git a/gas/testsuite/gas/arm/thumb2_it_bad.l b/gas/testsuite/gas/arm/thumb2_it_bad.l
index aa1f658..da9341f 100644
--- a/gas/testsuite/gas/arm/thumb2_it_bad.l
+++ b/gas/testsuite/gas/arm/thumb2_it_bad.l
@@ -10,3 +10,4 @@
[^:]*:19: Error: instruction is always unconditional -- `bkpteq 0'
[^:]*:20: Error: instruction not allowed in IT block -- `setendeq le'
[^:]*:22: Error: IT falling in the range of a previous IT block -- `iteq eq'
+[^:]*:25: Error: instruction not allowed in IT block -- `csdbeq'
diff --git a/gas/testsuite/gas/arm/thumb2_it_bad.s b/gas/testsuite/gas/arm/thumb2_it_bad.s
index 6add4fb..72f305d 100644
--- a/gas/testsuite/gas/arm/thumb2_it_bad.s
+++ b/gas/testsuite/gas/arm/thumb2_it_bad.s
@@ -21,4 +21,6 @@ thumb2_it_bad:
it eq
iteq eq
nop
+ it eq
+ csdbeq
foo: