diff options
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 8 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/illegal-ldapr.d | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/illegal-ldapr.l | 16 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/illegal-ldapr.s | 25 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.d | 20 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.s | 22 |
6 files changed, 93 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 7aafe4e..560a7bf 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,13 @@ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> + * testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Add ldaprb, ldaprh, ldapr tests. + * testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Likewise. + * testsuite/gas/aarch64/illegal-ldapr.s: Likewise. + * testsuite/gas/aarch64/illegal-ldapr.d: Likewise. + * testsuite/gas/aarch64/illegal-ldapr.l: Likewise. + +2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> + * testsuite/gas/aarch64/fp-armv8_3.s: Add fjcvtzs test. * testsuite/gas/aarch64/fp-armv8_3.d: Likewise. * testsuite/gas/aarch64/illegal-fjcvtzs.s: Likewise. diff --git a/gas/testsuite/gas/aarch64/illegal-ldapr.d b/gas/testsuite/gas/aarch64/illegal-ldapr.d new file mode 100644 index 0000000..36e94df --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-ldapr.d @@ -0,0 +1,2 @@ +#as: -march=armv8.3-a -mno-verbose-error +#error-output: illegal-ldapr.l diff --git a/gas/testsuite/gas/aarch64/illegal-ldapr.l b/gas/testsuite/gas/aarch64/illegal-ldapr.l new file mode 100644 index 0000000..f5d85f0 --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-ldapr.l @@ -0,0 +1,16 @@ +[^:]+: Assembler messages: +[^:]+:18: Error: operand mismatch -- `ldaprb x0,\[x1\]' +[^:]+:19: Error: operand mismatch -- `ldaprh x0,\[x1\]' +[^:]+:20: Error: the optional immediate offset can only be 0 at operand 2 -- `ldapr x0,\[x1,#8\]' +[^:]+:24: Error: 64-bit integer or SP register expected at operand 2 -- `ldaprb w1,\[xz\]' +[^:]+:24: Error: the optional immediate offset can only be 0 at operand 2 -- `ldaprb w1,\[x7,#8\]' +[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldaprb w1,\[x7,#8\]!' +[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldaprb w1,\[x7\],#8' +[^:]+:24: Error: 64-bit integer or SP register expected at operand 2 -- `ldaprh w1,\[xz\]' +[^:]+:24: Error: the optional immediate offset can only be 0 at operand 2 -- `ldaprh w1,\[x7,#8\]' +[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldaprh w1,\[x7,#8\]!' +[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldaprh w1,\[x7\],#8' +[^:]+:24: Error: 64-bit integer or SP register expected at operand 2 -- `ldapr w1,\[xz\]' +[^:]+:24: Error: the optional immediate offset can only be 0 at operand 2 -- `ldapr w1,\[x7,#8\]' +[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldapr w1,\[x7,#8\]!' +[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldapr w1,\[x7\],#8' diff --git a/gas/testsuite/gas/aarch64/illegal-ldapr.s b/gas/testsuite/gas/aarch64/illegal-ldapr.s new file mode 100644 index 0000000..5943f8b --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-ldapr.s @@ -0,0 +1,25 @@ +/* Test illegal ARMv8.3 weaker release consistency load instructions. */ + + /* <mnemonic> <Wt>, [<Xn|SP>{,#0}] */ + .macro LR32 op + \op w1, [xz] + \op w1, [x7, #8] + \op w1, [x7, #8]! + \op w1, [x7], #8 + .endm + +.text + /* Good. */ + ldaprb w0, [x1] + ldaprh w0, [x1] + ldapr x0, [x1] + + /* Bad. */ + ldaprb x0, [x1] + ldaprh x0, [x1] + ldapr x0, [x1,#8] + + .irp op, ldaprb, ldaprh, ldapr + LR32 \op + .endr + diff --git a/gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.d b/gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.d new file mode 100644 index 0000000..b0de88a --- /dev/null +++ b/gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.d @@ -0,0 +1,20 @@ +#objdump: -dr +#as: -march=armv8.3-a + +.*: file format .* + +Disassembly of section \.text: + +0000000000000000 <.*>: + 0: 38bfc0e1 ldaprb w1, \[x7\] + 4: 38bfc0e1 ldaprb w1, \[x7\] + 8: 38bfc0e1 ldaprb w1, \[x7\] + c: 78bfc0e1 ldaprh w1, \[x7\] + 10: 78bfc0e1 ldaprh w1, \[x7\] + 14: 78bfc0e1 ldaprh w1, \[x7\] + 18: b8bfc0e1 ldapr w1, \[x7\] + 1c: b8bfc0e1 ldapr w1, \[x7\] + 20: b8bfc0e1 ldapr w1, \[x7\] + 24: f8bfc0e1 ldapr x1, \[x7\] + 28: f8bfc0e1 ldapr x1, \[x7\] + 2c: f8bfc0e1 ldapr x1, \[x7\] diff --git a/gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.s b/gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.s new file mode 100644 index 0000000..bfa41e0 --- /dev/null +++ b/gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.s @@ -0,0 +1,22 @@ + /* ARMv8.3 weaker release consistency load instructions. */ + + /* <mnemonic> <Wt>, [<Xn|SP>{,#0}] */ + .macro LR32 op + \op w1, [x7] + \op w1, [x7, #0] + \op w1, [x7, 0] + .endm + + /* <mnemonic> <Xt>, [<Xn|SP>{,#0}] */ + .macro LR64 op + \op x1, [x7] + \op x1, [x7, #0] + \op x1, [x7, 0] + .endm + +func: + .irp op, ldaprb, ldaprh, ldapr + LR32 \op + .endr + + LR64 ldapr |