diff options
Diffstat (limited to 'gas')
56 files changed, 22111 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 7845ae5..ca922ec 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,21 @@ +Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com> + David Mosberger <davidm@hpl.hp.com> + Timothy Wall <twall@cygnus.com> + Andrew MacLeod <amacleod@cygnus.com> + Jim Wilson <wilson@cygnus.com> + + * Makefile.am (CPU_TYPES): Add ia64. + (TARGET_CPU_CFILES): Add cofnig/tc-ia64.c. + (TARGET_CPU_HFILES): Add config/tc-ia64.h. + * Makefile.in: Rebuild. + * app.c (do_scrub_chars): Handle DOUBLESLASH_COMMENTS. + * configure: Rebuild. + * configure.in: Recognize ia64 as cpu type. Set bfd_gas. + (ia64-*-elf*, ia64-*-linux-gnu*): New targets. + * expr.c (expr): Handle md_optimize_expr. + * read.c (LEX_HASH): Add comment. + * config/tc-ia64.c, config/tc-ia64.h: New files. + 2000-04-21 Richard Henderson <rth@cygnus.com> * config/tc-d30v.c (write_2_short): Disregard opcode1->ecc when diff --git a/gas/Makefile.am b/gas/Makefile.am index 12f8caa..d46b1bd 100644 --- a/gas/Makefile.am +++ b/gas/Makefile.am @@ -48,6 +48,7 @@ CPU_TYPES = \ h8300 \ h8500 \ hppa \ + ia64 \ i370 \ i386 \ i860 \ @@ -218,6 +219,7 @@ TARGET_CPU_CFILES = \ config/tc-h8300.c \ config/tc-h8500.c \ config/tc-hppa.c \ + config/tc-ia64.c \ config/tc-i370.c \ config/tc-i386.c \ config/tc-i860.c \ @@ -254,6 +256,7 @@ TARGET_CPU_HFILES = \ config/tc-h8300.h \ config/tc-h8500.h \ config/tc-hppa.h \ + config/tc-ia64.h \ config/tc-i370.h \ config/tc-i386.h \ config/tc-i860.h \ diff --git a/gas/Makefile.in b/gas/Makefile.in index d3237c0..96d5f28 100644 --- a/gas/Makefile.in +++ b/gas/Makefile.in @@ -152,6 +152,7 @@ CPU_TYPES = \ h8300 \ h8500 \ hppa \ + ia64 \ i370 \ i386 \ i860 \ @@ -328,6 +329,7 @@ TARGET_CPU_CFILES = \ config/tc-h8300.c \ config/tc-h8500.c \ config/tc-hppa.c \ + config/tc-ia64.c \ config/tc-i370.c \ config/tc-i386.c \ config/tc-i860.c \ @@ -365,6 +367,7 @@ TARGET_CPU_HFILES = \ config/tc-h8300.h \ config/tc-h8500.h \ config/tc-hppa.h \ + config/tc-ia64.h \ config/tc-i370.h \ config/tc-i386.h \ config/tc-i860.h \ @@ -913,6 +913,21 @@ do_scrub_chars (get, tostart, tolen) ch = ' '; goto recycle; } +#ifdef DOUBLESLASH_LINE_COMMENTS + else if (ch2 == '/') + { + do + { + ch = GET (); + } + while (ch != EOF && !IS_NEWLINE (ch)); + if (ch == EOF) + as_warn ("end of file in comment; newline inserted"); + state = 0; + PUT ('\n'); + break; + } +#endif else { if (ch2 != EOF) diff --git a/gas/config/tc-ia64.c b/gas/config/tc-ia64.c new file mode 100644 index 0000000..e4b6bbe --- /dev/null +++ b/gas/config/tc-ia64.c @@ -0,0 +1,8295 @@ +/* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture. + Copyright (C) 1998, 1999 Free Software Foundation. + Contributed by David Mosberger-Tang <davidm@hpl.hp.com> + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* + TODO: + + - optional operands + - directives: + .alias + .eb + .estate + .lb + .popsection + .previous + .psr + .pushsection + .save + .vframe + - labels are wrong if automatic alignment is introduced + (e.g., checkout the second real10 definition in test-data.s) + - DV-related stuff: + <reg>.safe_across_calls and any other DV-related directives I don't + have documentation for. + verify mod-sched-brs reads/writes are checked/marked (and other + notes) + + */ + +#include "as.h" +#include "dwarf2dbg.h" +#include "subsegs.h" + +#include "opcode/ia64.h" + +#include "elf/ia64.h" + +#define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0]))) +#define MIN(a,b) ((a) < (b) ? (a) : (b)) + +#define NUM_SLOTS 4 +#define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS] +#define CURR_SLOT md.slot[md.curr_slot] + +#define O_pseudo_fixup (O_max + 1) + +enum special_section + { + SPECIAL_SECTION_BSS = 0, + SPECIAL_SECTION_SBSS, + SPECIAL_SECTION_SDATA, + SPECIAL_SECTION_RODATA, + SPECIAL_SECTION_COMMENT, + SPECIAL_SECTION_UNWIND, + SPECIAL_SECTION_UNWIND_INFO + }; + +enum reloc_func + { + FUNC_FPTR_RELATIVE, + FUNC_GP_RELATIVE, + FUNC_LT_RELATIVE, + FUNC_PLT_RELATIVE, + FUNC_SEC_RELATIVE, + FUNC_SEG_RELATIVE, + FUNC_LTV_RELATIVE, + FUNC_LT_FPTR_RELATIVE, + }; + +enum reg_symbol + { + REG_GR = 0, + REG_FR = (REG_GR + 128), + REG_AR = (REG_FR + 128), + REG_CR = (REG_AR + 128), + REG_P = (REG_CR + 128), + REG_BR = (REG_P + 64), + REG_IP = (REG_BR + 8), + REG_CFM, + REG_PR, + REG_PR_ROT, + REG_PSR, + REG_PSR_L, + REG_PSR_UM, + /* The following are pseudo-registers for use by gas only. */ + IND_CPUID, + IND_DBR, + IND_DTR, + IND_ITR, + IND_IBR, + IND_MEM, + IND_MSR, + IND_PKR, + IND_PMC, + IND_PMD, + IND_RR, + REG_NUM + }; + +enum dynreg_type + { + DYNREG_GR = 0, /* dynamic general purpose register */ + DYNREG_FR, /* dynamic floating point register */ + DYNREG_PR, /* dynamic predicate register */ + DYNREG_NUM_TYPES + }; + +/* On the ia64, we can't know the address of a text label until the + instructions are packed into a bundle. To handle this, we keep + track of the list of labels that appear in front of each + instruction. */ +struct label_fix + { + struct label_fix *next; + struct symbol *sym; + }; + +extern int target_big_endian; + +/* Characters which always start a comment. */ +const char comment_chars[] = ""; + +/* Characters which start a comment at the beginning of a line. */ +const char line_comment_chars[] = "#"; + +/* Characters which may be used to separate multiple commands on a + single line. */ +const char line_separator_chars[] = ";"; + +/* Characters which are used to indicate an exponent in a floating + point number. */ +const char EXP_CHARS[] = "eE"; + +/* Characters which mean that a number is a floating point constant, + as in 0d1.0. */ +const char FLT_CHARS[] = "rRsSfFdDxXpP"; + +/* ia64-specific option processing: */ + +const char *md_shortopts = "M:N:x::"; + +struct option md_longopts[] = + { + { NULL, no_argument, NULL, 0} + }; + +size_t md_longopts_size = sizeof (md_longopts); + +static struct + { + struct hash_control *pseudo_hash; /* pseudo opcode hash table */ + struct hash_control *reg_hash; /* register name hash table */ + struct hash_control *dynreg_hash; /* dynamic register hash table */ + struct hash_control *const_hash; /* constant hash table */ + struct hash_control *entry_hash; /* code entry hint hash table */ + + symbolS *regsym[REG_NUM]; + + /* If X_op is != O_absent, the registername for the instruction's + qualifying predicate. If NULL, p0 is assumed for instructions + that are predicatable. */ + expressionS qp; + + unsigned int + manual_bundling : 1, + debug_dv: 1, + detect_dv: 1, + explicit_mode : 1, /* which mode we're in */ + default_explicit_mode : 1, /* which mode is the default */ + mode_explicitly_set : 1, /* was the current mode explicitly set? */ + auto_align : 1; + + /* Each bundle consists of up to three instructions. We keep + track of four most recent instructions so we can correctly set + the end_of_insn_group for the last instruction in a bundle. */ + int curr_slot; + int num_slots_in_use; + struct slot + { + unsigned int + end_of_insn_group : 1, + manual_bundling_on : 1, + manual_bundling_off : 1; + signed char user_template; /* user-selected template, if any */ + unsigned char qp_regno; /* qualifying predicate */ + /* This duplicates a good fraction of "struct fix" but we + can't use a "struct fix" instead since we can't call + fix_new_exp() until we know the address of the instruction. */ + int num_fixups; + struct insn_fix + { + bfd_reloc_code_real_type code; + enum ia64_opnd opnd; /* type of operand in need of fix */ + unsigned int is_pcrel : 1; /* is operand pc-relative? */ + expressionS expr; /* the value to be inserted */ + } + fixup[2]; /* at most two fixups per insn */ + struct ia64_opcode *idesc; + struct label_fix *label_fixups; + struct unw_rec_list *unwind_record; /* Unwind directive. */ + expressionS opnd[6]; + char *src_file; + unsigned int src_line; + struct dwarf2_line_info debug_line; + } + slot[NUM_SLOTS]; + + segT last_text_seg; + + struct dynreg + { + struct dynreg *next; /* next dynamic register */ + const char *name; + unsigned short base; /* the base register number */ + unsigned short num_regs; /* # of registers in this set */ + } + *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot; + + flagword flags; /* ELF-header flags */ + + struct mem_offset { + unsigned hint:1; /* is this hint currently valid? */ + bfd_vma offset; /* mem.offset offset */ + bfd_vma base; /* mem.offset base */ + } mem_offset; + + int path; /* number of alt. entry points seen */ + const char **entry_labels; /* labels of all alternate paths in + the current DV-checking block. */ + int maxpaths; /* size currently allocated for + entry_labels */ + } +md; + +/* application registers: */ + +#define AR_K0 0 +#define AR_K7 7 +#define AR_RSC 16 +#define AR_BSP 17 +#define AR_BSPSTORE 18 +#define AR_RNAT 19 +#define AR_UNAT 36 +#define AR_FPSR 40 +#define AR_ITC 44 + +static const struct + { + const char *name; + int regnum; + } +ar[] = + { + {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3}, + {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7}, + {"ar.rsc", 16}, {"ar.bsp", 17}, + {"ar.bspstore", 18}, {"ar.rnat", 19}, + {"ar.fcr", 21}, {"ar.eflag", 24}, + {"ar.csd", 25}, {"ar.ssd", 26}, + {"ar.cflg", 27}, {"ar.fsr", 28}, + {"ar.fir", 29}, {"ar.fdr", 30}, + {"ar.ccv", 32}, {"ar.unat", 36}, + {"ar.fpsr", 40}, {"ar.itc", 44}, + {"ar.pfs", 64}, {"ar.lc", 65}, + {"ar.ec", 66}, + }; + +#define CR_IPSR 16 +#define CR_ISR 17 +#define CR_IIP 19 +#define CR_IFA 20 +#define CR_ITIR 21 +#define CR_IIPA 22 +#define CR_IFS 23 +#define CR_IIM 24 +#define CR_IHA 25 +#define CR_IVR 65 +#define CR_TPR 66 +#define CR_EOI 67 +#define CR_IRR0 68 +#define CR_IRR3 71 +#define CR_LRR0 80 +#define CR_LRR1 81 + +/* control registers: */ +static const struct + { + const char *name; + int regnum; + } +cr[] = + { + {"cr.dcr", 0}, + {"cr.itm", 1}, + {"cr.iva", 2}, + {"cr.pta", 8}, + {"cr.gpta", 9}, + {"cr.ipsr", 16}, + {"cr.isr", 17}, + {"cr.iip", 19}, + {"cr.ifa", 20}, + {"cr.itir", 21}, + {"cr.iipa", 22}, + {"cr.ifs", 23}, + {"cr.iim", 24}, + {"cr.iha", 25}, + {"cr.lid", 64}, + {"cr.ivr", 65}, + {"cr.tpr", 66}, + {"cr.eoi", 67}, + {"cr.irr0", 68}, + {"cr.irr1", 69}, + {"cr.irr2", 70}, + {"cr.irr3", 71}, + {"cr.itv", 72}, + {"cr.pmv", 73}, + {"cr.cmcv", 74}, + {"cr.lrr0", 80}, + {"cr.lrr1", 81} + }; + +#define PSR_MFL 4 +#define PSR_IC 13 +#define PSR_DFL 18 +#define PSR_CPL 32 + +static const struct const_desc + { + const char *name; + valueT value; + } +const_bits[] = + { + /* PSR constant masks: */ + + /* 0: reserved */ + {"psr.be", ((valueT) 1) << 1}, + {"psr.up", ((valueT) 1) << 2}, + {"psr.ac", ((valueT) 1) << 3}, + {"psr.mfl", ((valueT) 1) << 4}, + {"psr.mfh", ((valueT) 1) << 5}, + /* 6-12: reserved */ + {"psr.ic", ((valueT) 1) << 13}, + {"psr.i", ((valueT) 1) << 14}, + {"psr.pk", ((valueT) 1) << 15}, + /* 16: reserved */ + {"psr.dt", ((valueT) 1) << 17}, + {"psr.dfl", ((valueT) 1) << 18}, + {"psr.dfh", ((valueT) 1) << 19}, + {"psr.sp", ((valueT) 1) << 20}, + {"psr.pp", ((valueT) 1) << 21}, + {"psr.di", ((valueT) 1) << 22}, + {"psr.si", ((valueT) 1) << 23}, + {"psr.db", ((valueT) 1) << 24}, + {"psr.lp", ((valueT) 1) << 25}, + {"psr.tb", ((valueT) 1) << 26}, + {"psr.rt", ((valueT) 1) << 27}, + /* 28-31: reserved */ + /* 32-33: cpl (current privilege level) */ + {"psr.is", ((valueT) 1) << 34}, + {"psr.mc", ((valueT) 1) << 35}, + {"psr.it", ((valueT) 1) << 36}, + {"psr.id", ((valueT) 1) << 37}, + {"psr.da", ((valueT) 1) << 38}, + {"psr.dd", ((valueT) 1) << 39}, + {"psr.ss", ((valueT) 1) << 40}, + /* 41-42: ri (restart instruction) */ + {"psr.ed", ((valueT) 1) << 43}, + {"psr.bn", ((valueT) 1) << 44}, + }; + +/* indirect register-sets/memory: */ + +static const struct + { + const char *name; + int regnum; + } +indirect_reg[] = + { + { "CPUID", IND_CPUID }, + { "cpuid", IND_CPUID }, + { "dbr", IND_DBR }, + { "dtr", IND_DTR }, + { "itr", IND_ITR }, + { "ibr", IND_IBR }, + { "msr", IND_MSR }, + { "pkr", IND_PKR }, + { "pmc", IND_PMC }, + { "pmd", IND_PMD }, + { "rr", IND_RR }, + }; + +/* Pseudo functions used to indicate relocation types (these functions + start with an at sign (@). */ +static struct + { + const char *name; + enum pseudo_type + { + PSEUDO_FUNC_NONE, + PSEUDO_FUNC_RELOC, + PSEUDO_FUNC_CONST, + PSEUDO_FUNC_FLOAT + } + type; + union + { + unsigned long ival; + symbolS *sym; + } + u; + } +pseudo_func[] = + { + /* reloc pseudo functions (these must come first!): */ + { "fptr", PSEUDO_FUNC_RELOC }, + { "gprel", PSEUDO_FUNC_RELOC }, + { "ltoff", PSEUDO_FUNC_RELOC }, + { "pltoff", PSEUDO_FUNC_RELOC }, + { "secrel", PSEUDO_FUNC_RELOC }, + { "segrel", PSEUDO_FUNC_RELOC }, + { "ltv", PSEUDO_FUNC_RELOC }, + { 0, }, /* placeholder for FUNC_LT_FPTR_RELATIVE */ + + /* mbtype4 constants: */ + { "alt", PSEUDO_FUNC_CONST, { 0xa } }, + { "brcst", PSEUDO_FUNC_CONST, { 0x0 } }, + { "mix", PSEUDO_FUNC_CONST, { 0x8 } }, + { "rev", PSEUDO_FUNC_CONST, { 0xb } }, + { "shuf", PSEUDO_FUNC_CONST, { 0x9 } }, + + /* fclass constants: */ + { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, + { "qnan", PSEUDO_FUNC_CONST, { 0x080 } }, + { "snan", PSEUDO_FUNC_CONST, { 0x040 } }, + { "pos", PSEUDO_FUNC_CONST, { 0x001 } }, + { "neg", PSEUDO_FUNC_CONST, { 0x002 } }, + { "zero", PSEUDO_FUNC_CONST, { 0x004 } }, + { "unorm", PSEUDO_FUNC_CONST, { 0x008 } }, + { "norm", PSEUDO_FUNC_CONST, { 0x010 } }, + { "inf", PSEUDO_FUNC_CONST, { 0x020 } }, + }; + +/* 41-bit nop opcodes (one per unit): */ +static const bfd_vma nop[IA64_NUM_UNITS] = + { + 0x0000000000LL, /* NIL => break 0 */ + 0x0008000000LL, /* I-unit nop */ + 0x0008000000LL, /* M-unit nop */ + 0x4000000000LL, /* B-unit nop */ + 0x0008000000LL, /* F-unit nop */ + 0x0008000000LL, /* L-"unit" nop */ + 0x0008000000LL, /* X-unit nop */ + }; + +/* Can't be `const' as it's passed to input routines (which have the + habit of setting temporary sentinels. */ +static char special_section_name[][20] = + { + {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"}, + {".IA_64.unwind"}, {".IA_64.unwind_info"} + }; + +/* The best template for a particular sequence of up to three + instructions: */ +#define N IA64_NUM_TYPES +static unsigned char best_template[N][N][N]; +#undef N + +/* Resource dependencies currently in effect */ +static struct rsrc { + int depind; /* dependency index */ + const struct ia64_dependency *dependency; /* actual dependency */ + unsigned specific:1, /* is this a specific bit/regno? */ + link_to_qp_branch:1; /* will a branch on the same QP clear it?*/ + int index; /* specific regno/bit within dependency */ + int note; /* optional qualifying note (0 if none) */ +#define STATE_NONE 0 +#define STATE_STOP 1 +#define STATE_SRLZ 2 + int insn_srlz; /* current insn serialization state */ + int data_srlz; /* current data serialization state */ + int qp_regno; /* qualifying predicate for this usage */ + char *file; /* what file marked this dependency */ + int line; /* what line marked this dependency */ + struct mem_offset mem_offset; /* optional memory offset hint */ + int path; /* corresponding code entry index */ +} *regdeps = NULL; +static int regdepslen = 0; +static int regdepstotlen = 0; +static const char *dv_mode[] = { "RAW", "WAW", "WAR" }; +static const char *dv_sem[] = { "none", "implied", "impliedf", + "data", "instr", "specific", "other" }; + +/* Current state of PR mutexation */ +static struct qpmutex { + valueT prmask; + int path; +} *qp_mutexes = NULL; /* QP mutex bitmasks */ +static int qp_mutexeslen = 0; +static int qp_mutexestotlen = 0; +static valueT qp_safe_across_calls = 0; + +/* Current state of PR implications */ +static struct qp_imply { + unsigned p1:6; + unsigned p2:6; + unsigned p2_branched:1; + int path; +} *qp_implies = NULL; +static int qp_implieslen = 0; +static int qp_impliestotlen = 0; + +/* Keep track of static GR values so that indirect register usage can + sometimes be tracked. */ +static struct gr { + unsigned known:1; + int path; + valueT value; +} gr_values[128] = {{ 1, 0 }}; + +/* These are the routines required to output the various types of + unwind records. */ + +typedef struct unw_rec_list { + unwind_record r; + unsigned long slot_number; + struct unw_rec_list *next; +} unw_rec_list; + +#define SLOT_NUM_NOT_SET -1 + +/* TRUE if processing unwind directives in a prologue region. */ +static int unwind_prologue = 0; + +/* Maintain a list of unwind entries for the current function. */ +static unw_rec_list *unwind_list = 0; +static unw_rec_list *unwind_tail = 0; + +/* Any unwind entires that should be attached to the current + slot that an insn is being constructed for. */ +static unw_rec_list *current_unwind_entry = 0; + +/* These are used to create the unwind table entry for this function. */ +static symbolS *proc_start = 0; +static symbolS *proc_end = 0; +static symbolS *unwind_info = 0; +static symbolS *personality_routine = 0; + +typedef void (*vbyte_func) PARAMS ((int, char *, char *)); + +/* Forward delarations: */ +static int ar_is_in_integer_unit PARAMS ((int regnum)); +static void set_section PARAMS ((char *name)); +static unsigned int set_regstack PARAMS ((unsigned int, unsigned int, + unsigned int, unsigned int)); +static void dot_radix PARAMS ((int)); +static void dot_special_section PARAMS ((int)); +static void dot_proc PARAMS ((int)); +static void dot_fframe PARAMS ((int)); +static void dot_vframe PARAMS ((int)); +static void dot_save PARAMS ((int)); +static void dot_restore PARAMS ((int)); +static void dot_handlerdata PARAMS ((int)); +static void dot_unwentry PARAMS ((int)); +static void dot_altrp PARAMS ((int)); +static void dot_savesp PARAMS ((int)); +static void dot_savepsp PARAMS ((int)); +static void dot_saveg PARAMS ((int)); +static void dot_savef PARAMS ((int)); +static void dot_saveb PARAMS ((int)); +static void dot_savegf PARAMS ((int)); +static void dot_spill PARAMS ((int)); +static void dot_unwabi PARAMS ((int)); +static void dot_personality PARAMS ((int)); +static void dot_body PARAMS ((int)); +static void dot_prologue PARAMS ((int)); +static void dot_endp PARAMS ((int)); +static void dot_template PARAMS ((int)); +static void dot_regstk PARAMS ((int)); +static void dot_rot PARAMS ((int)); +static void dot_byteorder PARAMS ((int)); +static void dot_psr PARAMS ((int)); +static void dot_alias PARAMS ((int)); +static void dot_ln PARAMS ((int)); +static char *parse_section_name PARAMS ((void)); +static void dot_xdata PARAMS ((int)); +static void stmt_float_cons PARAMS ((int)); +static void stmt_cons_ua PARAMS ((int)); +static void dot_xfloat_cons PARAMS ((int)); +static void dot_xstringer PARAMS ((int)); +static void dot_xdata_ua PARAMS ((int)); +static void dot_xfloat_cons_ua PARAMS ((int)); +static void dot_pred_rel PARAMS ((int)); +static void dot_reg_val PARAMS ((int)); +static void dot_dv_mode PARAMS ((int)); +static void dot_entry PARAMS ((int)); +static void dot_mem_offset PARAMS ((int)); +static symbolS* declare_register PARAMS ((const char *name, int regnum)); +static void declare_register_set PARAMS ((const char *, int, int)); +static unsigned int operand_width PARAMS ((enum ia64_opnd)); +static int operand_match PARAMS ((const struct ia64_opcode *idesc, + int index, expressionS *e)); +static int parse_operand PARAMS ((expressionS *e)); +static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *)); +static void build_insn PARAMS ((struct slot *, bfd_vma *)); +static void emit_one_bundle PARAMS ((void)); +static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT)); +static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym, + bfd_reloc_code_real_type r_type)); +static void insn_group_break PARAMS ((int, int, int)); +static void add_qp_mutex PARAMS((valueT mask)); +static void add_qp_imply PARAMS((int p1, int p2)); +static void clear_qp_branch_flag PARAMS((valueT mask)); +static void clear_qp_mutex PARAMS((valueT mask)); +static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask)); +static void clear_register_values PARAMS ((void)); +static void print_dependency PARAMS ((const char *action, int depind)); +static int is_conditional_branch PARAMS ((struct ia64_opcode *)); +static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *)); +static int check_dv PARAMS((struct ia64_opcode *idesc)); +static void check_dependencies PARAMS((struct ia64_opcode *)); +static void mark_resources PARAMS((struct ia64_opcode *)); +static void update_dependencies PARAMS((struct ia64_opcode *)); +static void note_register_values PARAMS((struct ia64_opcode *)); +static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); +static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long)); +static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); + +/* Determine if application register REGNUM resides in the integer + unit (as opposed to the memory unit). */ +static int +ar_is_in_integer_unit (reg) + int reg; +{ + reg -= REG_AR; + + return (reg == 64 /* pfs */ + || reg == 65 /* lc */ + || reg == 66 /* ec */ + /* ??? ias accepts and puts these in the integer unit. */ + || (reg >= 112 && reg <= 127)); +} + +/* Switch to section NAME and create section if necessary. It's + rather ugly that we have to manipulate input_line_pointer but I + don't see any other way to accomplish the same thing without + changing obj-elf.c (which may be the Right Thing, in the end). */ +static void +set_section (name) + char *name; +{ + char *saved_input_line_pointer; + + saved_input_line_pointer = input_line_pointer; + input_line_pointer = name; + obj_elf_section (0); + input_line_pointer = saved_input_line_pointer; +} + +/* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */ + +flagword +ia64_elf_section_flags (flags, attr, type) + flagword flags; + int attr, type; +{ + if (attr & SHF_IA_64_SHORT) + flags |= SEC_SMALL_DATA; + return flags; +} + +static unsigned int +set_regstack (ins, locs, outs, rots) + unsigned int ins, locs, outs, rots; +{ + unsigned int sof; /* size of frame */ + + sof = ins + locs + outs; + if (sof > 96) + { + as_bad ("Size of frame exceeds maximum of 96 registers"); + return 0; + } + if (rots > sof) + { + as_warn ("Size of rotating registers exceeds frame size"); + return 0; + } + md.in.base = REG_GR + 32; + md.loc.base = md.in.base + ins; + md.out.base = md.loc.base + locs; + + md.in.num_regs = ins; + md.loc.num_regs = locs; + md.out.num_regs = outs; + md.rot.num_regs = rots; + return sof; +} + +void +ia64_flush_insns () +{ + struct label_fix *lfix; + segT saved_seg; + subsegT saved_subseg; + + if (!md.last_text_seg) + return; + + saved_seg = now_seg; + saved_subseg = now_subseg; + + subseg_set (md.last_text_seg, 0); + + while (md.num_slots_in_use > 0) + emit_one_bundle (); /* force out queued instructions */ + + /* In case there are labels following the last instruction, resolve + those now: */ + for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next) + { + S_SET_VALUE (lfix->sym, frag_now_fix ()); + symbol_set_frag (lfix->sym, frag_now); + } + CURR_SLOT.label_fixups = 0; + + subseg_set (saved_seg, saved_subseg); +} + +void +ia64_do_align (nbytes) + int nbytes; +{ + char *saved_input_line_pointer = input_line_pointer; + + input_line_pointer = ""; + s_align_bytes (nbytes); + input_line_pointer = saved_input_line_pointer; +} + +void +ia64_cons_align (nbytes) + int nbytes; +{ + if (md.auto_align) + { + char *saved_input_line_pointer = input_line_pointer; + input_line_pointer = ""; + s_align_bytes (nbytes); + input_line_pointer = saved_input_line_pointer; + } +} + +/* Output COUNT bytes to a memory location. */ +static unsigned char *vbyte_mem_ptr = NULL; + +void +output_vbyte_mem (count, ptr, comment) + int count; + char *ptr; + char *comment; +{ + int x; + if (vbyte_mem_ptr == NULL) + abort (); + + if (count == 0) + return; + for (x = 0; x < count; x++) + *(vbyte_mem_ptr++) = ptr[x]; +} + +/* Count the number of bytes required for records. */ +static int vbyte_count = 0; +void +count_output (count, ptr, comment) + int count; + char *ptr; + char *comment; +{ + vbyte_count += count; +} + +static void +output_R1_format (f, rtype, rlen) + vbyte_func f; + unw_record_type rtype; + int rlen; +{ + int r; + char byte; + if (rlen > 0x1f) + { + output_R3_format (f, rtype, rlen); + return; + } + if (rtype == prologue) + r = 0; + else + if (rtype == body) + r = 1; + else + as_bad ("record type is not valid"); + + byte = UNW_R1 | (r << 5) | (rlen & 0x1f); + (*f) (1, &byte, NULL); +} + +static void +output_R2_format (f, mask, grsave, rlen) + vbyte_func f; + int mask, grsave; + unsigned long rlen; +{ + char bytes[20]; + int count = 2; + mask = (mask & 0x0f); + grsave = (grsave & 0x7f); + + bytes[0] = (UNW_R2 | (mask >> 1)); + bytes[1] = (((mask & 0x01) << 7) | grsave); + count += output_leb128 (bytes + 2, rlen, 0); + (*f) (count, bytes, NULL); +} + +static void +output_R3_format (f, rtype, rlen) + vbyte_func f; + unw_record_type rtype; + unsigned long rlen; +{ + int r, count; + char bytes[20]; + if (rlen <= 0x1f) + { + output_R1_format (f, rtype, rlen); + return; + } + if (rtype == prologue) + r = 0; + else + if (rtype == body) + r = 1; + else + as_bad ("record type is not valid"); + bytes[0] = (UNW_R3 | r); + count = output_leb128 (bytes + 1, rlen, 0); + (*f) (count + 1, bytes, NULL); +} + +static void +output_P1_format (f, brmask) + vbyte_func f; + int brmask; +{ + char byte; + byte = UNW_P1 | (brmask & 0x1f); + (*f) (1, &byte, NULL); +} + +static void +output_P2_format (f, brmask, gr) + vbyte_func f; + int brmask; + int gr; +{ + char bytes[2]; + brmask = (brmask & 0x1f); + bytes[0] = UNW_P2 | (brmask >> 1); + bytes[1] = (((brmask & 1) << 7) | gr); + (*f) (2, bytes, NULL); +} + +static void +output_P3_format (f, rtype, reg) + vbyte_func f; + unw_record_type rtype; + int reg; +{ + char bytes[2]; + int r; + reg = (reg & 0x7f); + switch (rtype) + { + case psp_gr: + r = 0; + break; + case rp_gr: + r = 1; + break; + case pfs_gr: + r = 2; + break; + case preds_gr: + r = 3; + break; + case unat_gr: + r = 4; + break; + case lc_gr: + r = 5; + break; + case rp_br: + r = 6; + break; + case rnat_gr: + r = 7; + break; + case bsp_gr: + r = 8; + break; + case bspstore_gr: + r = 9; + break; + case fpsr_gr: + r = 10; + break; + case priunat_gr: + r = 11; + break; + default: + as_bad ("Invalid record type for P3 format."); + } + bytes[0] = (UNW_P3 | (r >> 1)); + bytes[1] = (((r & 1) << 7) | reg); + (*f) (2, bytes, NULL); +} + + +static void +output_P4_format (f, count, imask) + vbyte_func f; + int count; + char *imask; +{ + char *bytes; + bytes = alloca (count + 1); + bytes[0] = UNW_P4; + memcpy (bytes + 1, imask, count); + (*f) (count + 1, bytes, NULL); +} + +static void +output_P5_format (f, grmask, frmask) + vbyte_func f; + int grmask; + unsigned long frmask; +{ + char bytes[4]; + grmask = (grmask & 0x0f); + + bytes[0] = UNW_P5; + bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16)); + bytes[2] = ((frmask & 0x0000ff00) >> 8); + bytes[3] = (frmask & 0x000000ff); + (*f) (4, bytes, NULL); +} + +static void +output_P6_format (f, rtype, rmask) + vbyte_func f; + unw_record_type rtype; + int rmask; +{ + char byte; + int r; + if (rtype == fr_mem) + r = 0; + else + if (rtype == gr_mem) + r = 1; + else + as_bad ("Invalid record type for format P6"); + byte = (UNW_P6 | (r << 4) | (rmask & 0x0f)); + (*f) (1, &byte, NULL); +} + +static void +output_P7_format (f, rtype, w1, w2) + vbyte_func f; + unw_record_type rtype; + unsigned long w1; + unsigned long w2; +{ + char bytes[20]; + int count = 1; + int r; + count += output_leb128 (bytes + 1, w1, 0); + switch (rtype) + { + case mem_stack_f: + r = 0; + count += output_leb128 (bytes + count, w2, 0); + break; + case mem_stack_v: + r = 1; + break; + case spill_base: + r = 2; + break; + case psp_sprel: + r = 3; + break; + case rp_when: + r = 4; + break; + case rp_psprel: + r = 5; + break; + case pfs_when: + r = 6; + break; + case pfs_psprel: + r = 7; + break; + case preds_when: + r = 8; + break; + case preds_psprel: + r = 9; + break; + case lc_when: + r = 10; + break; + case lc_psprel: + r = 11; + break; + case unat_when: + r = 12; + break; + case unat_psprel: + r = 13; + break; + case fpsr_when: + r = 14; + break; + case fpsr_psprel: + r = 15; + break; + } + bytes[0] = (UNW_P7 | r); + (*f) (count, bytes, NULL); +} + +static void +output_P8_format (f, rtype, t) + vbyte_func f; + unw_record_type rtype; + unsigned long t; +{ + char bytes[20]; + int r; + int count = 2; + bytes[0] = UNW_P8; + switch (rtype) + { + case rp_sprel: + r = 1; + break; + case pfs_sprel: + r = 2; + break; + case preds_sprel: + r = 3; + break; + case lc_sprel: + r = 4; + break; + case unat_sprel: + r = 5; + break; + case fpsr_sprel: + r = 6; + break; + case bsp_when: + r = 7; + break; + case bsp_psprel: + r = 8; + break; + case bsp_sprel: + r = 9; + break; + case bspstore_when: + r = 10; + break; + case bspstore_psprel: + r = 11; + break; + case bspstore_sprel: + r = 12; + break; + case rnat_when: + r = 13; + break; + case rnat_psprel: + r = 14; + break; + case rnat_sprel: + r = 15; + break; + case priunat_when_gr: + r = 16; + break; + case priunat_psprel: + r = 17; + break; + case priunat_sprel: + r = 18; + break; + case priunat_when_mem: + r = 19; + break; + } + bytes[1] = r; + count += output_leb128 (bytes + 2, t, 0); + (*f) (count, bytes, NULL); +} + +static void +output_P9_format (f, grmask, gr) + vbyte_func f; + int grmask; + int gr; +{ + char bytes[3]; + bytes[0] = UNW_P9; + bytes[1] = (grmask & 0x0f); + bytes[2] = (gr & 0x7f); + (*f) (3, bytes, NULL); +} + +static void +output_P10_format (f, abi, context) + vbyte_func f; + int abi; + int context; +{ + char bytes[3]; + bytes[0] = UNW_P10; + bytes[1] = (abi & 0xff); + bytes[2] = (context & 0xff); + (*f) (3, bytes, NULL); +} + +static void +output_B1_format (f, rtype, label) + vbyte_func f; + unw_record_type rtype; + unsigned long label; +{ + char byte; + int r; + if (label > 0x1f) + { + output_B4_format (f, rtype, label); + return; + } + if (rtype == label_state) + r = 0; + else + if (rtype == copy_state) + r = 1; + else + as_bad ("Invalid record type for format B1"); + + byte = (UNW_B1 | (r << 5) | (label & 0x1f)); + (*f) (1, &byte, NULL); +} + +static void +output_B2_format (f, ecount, t) + vbyte_func f; + unsigned long ecount; + unsigned long t; +{ + char bytes[20]; + int count = 1; + if (ecount > 0x1f) + { + output_B3_format (f, ecount, t); + return; + } + bytes[0] = (UNW_B2 | (ecount & 0x1f)); + count += output_leb128 (bytes + 1, t, 0); + (*f) (count, bytes, NULL); +} + +static void +output_B3_format (f, ecount, t) + vbyte_func f; + unsigned long ecount; + unsigned long t; +{ + char bytes[20]; + int count = 1; + if (ecount <= 0x1f) + { + output_B2_format (f, ecount, t); + return; + } + bytes[0] = UNW_B3; + count += output_leb128 (bytes + 1, t, 0); + count += output_leb128 (bytes + count, ecount, 0); + (*f) (count, bytes, NULL); +} + +static void +output_B4_format (f, rtype, label) + vbyte_func f; + unw_record_type rtype; + unsigned long label; +{ + char bytes[20]; + int r; + int count = 1; + if (label <= 0x1f) + { + output_B1_format (f, rtype, label); + return; + } + if (rtype == label_state) + r = 0; + else + if (rtype == copy_state) + r = 1; + else + as_bad ("Invalid record type for format B1"); + + bytes[0] = (UNW_B4 | (r << 3)); + count += output_leb128 (bytes + 1, label, 0); + (*f) (count, bytes, NULL); +} + +static char +format_a_b_reg (a, b, reg) + int a, b; + int reg; +{ + int ret; + a = (a & 1); + b = (b & 1); + reg = (reg & 0x1f); + ret = (a << 6) | (a << 5) | reg; + return ret; +} + +static void +output_X1_format (f, rtype, a, b, reg, t, w1) + vbyte_func f; + unw_record_type rtype; + int a, b, reg; + unsigned long t; + unsigned long w1; +{ + char bytes[20]; + int r; + int count = 2; + bytes[0] = UNW_X1; + if (rtype == spill_psprel) + r = 0; + else + if (rtype = spill_sprel) + r = 1; + else + as_bad ("Invalid record type for format X1"); + bytes[1] = ((r << 7) | format_a_b_reg (a, b, reg)); + count += output_leb128 (bytes + 2, t, 0); + count += output_leb128 (bytes + count, w1, 0); + (*f) (count, bytes, NULL); +} + +static void +output_X2_format (f, a, b, reg, x, y, treg, t) + vbyte_func f; + int a, b, reg; + int x, y, treg; + unsigned long t; +{ + char bytes[20]; + int r; + int count = 3; + bytes[0] = UNW_X2; + bytes[1] = (((x & 1) << 7) | format_a_b_reg (a, b, reg)); + bytes[2] = (((y & 1) << 7) | (treg & 0x7f)); + count += output_leb128 (bytes + 3, t, 0); + (*f) (count, bytes, NULL); +} + +static void +output_X3_format (f, rtype, qp, a, b, reg, t, w1) + vbyte_func f; + unw_record_type rtype; + int qp; + int a, b, reg; + unsigned long t; + unsigned long w1; +{ + char bytes[20]; + int r; + int count = 3; + bytes[0] = UNW_X1; + if (rtype == spill_psprel_p) + r = 0; + else + if (rtype = spill_sprel_p) + r = 1; + else + as_bad ("Invalid record type for format X1"); + bytes[1] = ((r << 7) | (qp & 0x3f)); + bytes[2] = format_a_b_reg (a, b, reg); + count += output_leb128 (bytes + 3, t, 0); + count += output_leb128 (bytes + count, w1, 0); + (*f) (count, bytes, NULL); +} + +static void +output_X4_format (f, qp, a, b, reg, x, y, treg, t) + vbyte_func f; + int qp; + int a, b, reg; + int x, y, treg; + unsigned long t; +{ + char bytes[20]; + int r; + int count = 4; + bytes[0] = UNW_X2; + bytes[1] = (qp & 0x3f); + bytes[2] = (((x & 1) << 7) | format_a_b_reg (a, b, reg)); + bytes[3] = (((y & 1) << 7) | (treg & 0x7f)); + count += output_leb128 (bytes + 4, t, 0); + (*f) (count, bytes, NULL); +} + +/* This function allocates a record list structure, and initializes fields. */ +static unw_rec_list * +alloc_record (unw_record_type t) +{ + unw_rec_list *ptr; + ptr = xmalloc (sizeof (*ptr)); + ptr->next = NULL; + ptr->slot_number = SLOT_NUM_NOT_SET; + ptr->r.type = t; + return ptr; +} + +/* This function frees a record list structure. */ +static void +free_record (unw_rec_list *ptr) +{ + free (ptr); +} + +/* This function frees an entire list of record structures. */ +void +free_list_records (unw_rec_list *first) +{ + unw_rec_list *ptr; + for (ptr = first; ptr != NULL; ) + { + unw_rec_list *tmp = ptr; + ptr = ptr->next; + free (tmp); + } +} + +static unw_rec_list * +output_prologue () +{ + unw_rec_list *ptr = alloc_record (prologue); + return ptr; +} + +static unw_rec_list * +output_prologue_gr (saved_mask, reg) + unsigned int saved_mask; + unsigned int reg; +{ + unw_rec_list *ptr = alloc_record (prologue_gr); + ptr->r.record.r.mask = saved_mask; + ptr->r.record.r.grsave = reg; + return ptr; +} + +static unw_rec_list * +output_body () +{ + unw_rec_list *ptr = alloc_record (body); + return ptr; +} + +static unw_rec_list * +output_mem_stack_f (size) + unsigned int size; +{ + unw_rec_list *ptr = alloc_record (mem_stack_f); + ptr->r.record.p.size = size; + return ptr; +} + +static unw_rec_list * +output_mem_stack_v () +{ + unw_rec_list *ptr = alloc_record (mem_stack_v); + return ptr; +} + +static unw_rec_list * +output_psp_gr (gr) + unsigned int gr; +{ + unw_rec_list *ptr = alloc_record (psp_gr); + ptr->r.record.p.gr = gr; + return ptr; +} + +static unw_rec_list * +output_psp_sprel (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (psp_sprel); + ptr->r.record.p.spoff = offset; + return ptr; +} + +static unw_rec_list * +output_rp_when () +{ + unw_rec_list *ptr = alloc_record (rp_when); + return ptr; +} + +static unw_rec_list * +output_rp_gr (gr) + unsigned int gr; +{ + unw_rec_list *ptr = alloc_record (rp_gr); + ptr->r.record.p.gr = gr; + return ptr; +} + +static unw_rec_list * +output_rp_br (br) + unsigned int br; +{ + unw_rec_list *ptr = alloc_record (rp_br); + ptr->r.record.p.br = br; + return ptr; +} + +static unw_rec_list * +output_rp_psprel (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (rp_psprel); + ptr->r.record.p.pspoff = offset; + return ptr; +} + +static unw_rec_list * +output_rp_sprel (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (rp_sprel); + ptr->r.record.p.spoff = offset; + return ptr; +} + +static unw_rec_list * +output_pfs_when () +{ + unw_rec_list *ptr = alloc_record (pfs_when); + return ptr; +} + +static unw_rec_list * +output_pfs_gr (gr) + unsigned int gr; +{ + unw_rec_list *ptr = alloc_record (pfs_gr); + ptr->r.record.p.gr = gr; + return ptr; +} + +static unw_rec_list * +output_pfs_psprel (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (pfs_psprel); + ptr->r.record.p.pspoff = offset; + return ptr; +} + +static unw_rec_list * +output_pfs_sprel (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (pfs_sprel); + ptr->r.record.p.spoff = offset; + return ptr; +} + +static unw_rec_list * +output_preds_when () +{ + unw_rec_list *ptr = alloc_record (preds_when); + return ptr; +} + +static unw_rec_list * +output_preds_gr (gr) + unsigned int gr; +{ + unw_rec_list *ptr = alloc_record (preds_gr); + ptr->r.record.p.gr = gr; + return ptr; +} + +static unw_rec_list * +output_preds_psprel (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (preds_psprel); + ptr->r.record.p.pspoff = offset; + return ptr; +} + +static unw_rec_list * +output_preds_sprel (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (preds_sprel); + ptr->r.record.p.spoff = offset; + return ptr; +} + +static unw_rec_list * +output_fr_mem (mask) + unsigned int mask; +{ + unw_rec_list *ptr = alloc_record (fr_mem); + ptr->r.record.p.rmask = mask; + return ptr; +} + +static unw_rec_list * +output_frgr_mem (gr_mask, fr_mask) + unsigned int gr_mask; + unsigned int fr_mask; +{ + unw_rec_list *ptr = alloc_record (frgr_mem); + ptr->r.record.p.grmask = gr_mask; + ptr->r.record.p.frmask = fr_mask; + return ptr; +} + +static unw_rec_list * +output_gr_gr (mask, reg) + unsigned int mask; + unsigned int reg; +{ + unw_rec_list *ptr = alloc_record (gr_gr); + ptr->r.record.p.grmask = mask; + ptr->r.record.p.gr = reg; + return ptr; +} + +static unw_rec_list * +output_gr_mem (mask) + unsigned int mask; +{ + unw_rec_list *ptr = alloc_record (gr_mem); + ptr->r.record.p.rmask = mask; + return ptr; +} + +static unw_rec_list * +output_br_mem (unsigned int mask) +{ + unw_rec_list *ptr = alloc_record (br_mem); + ptr->r.record.p.brmask = mask; + return ptr; +} + +static unw_rec_list * +output_br_gr (save_mask, reg) + unsigned int save_mask; + unsigned int reg; +{ + unw_rec_list *ptr = alloc_record (br_gr); + ptr->r.record.p.brmask = save_mask; + ptr->r.record.p.gr = reg; + return ptr; +} + +static unw_rec_list * +output_spill_base (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (spill_base); + ptr->r.record.p.pspoff = offset; + return ptr; +} + +static unw_rec_list * +output_spill_mask () +{ +/* TODO - how to implement this record.... I guess GAS could fill in the + correct fields from the record list and construct one of these + after the symbols have been resolved and we know how big the + region is. This could be done in fixup_unw_records. */ + unw_rec_list *ptr = NULL; + return ptr; +} + +static unw_rec_list * +output_unat_when () +{ + unw_rec_list *ptr = alloc_record (unat_when); + return ptr; +} + +static unw_rec_list * +output_unat_gr (gr) + unsigned int gr; +{ + unw_rec_list *ptr = alloc_record (unat_gr); + ptr->r.record.p.gr = gr; + return ptr; +} + +static unw_rec_list * +output_unat_psprel (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (unat_psprel); + ptr->r.record.p.pspoff = offset; + return ptr; +} + +static unw_rec_list * +output_unat_sprel (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (unat_sprel); + ptr->r.record.p.spoff = offset; + return ptr; +} + +static unw_rec_list * +output_lc_when () +{ + unw_rec_list *ptr = alloc_record (lc_when); + return ptr; +} + +static unw_rec_list * +output_lc_gr (gr) + unsigned int gr; +{ + unw_rec_list *ptr = alloc_record (lc_gr); + ptr->r.record.p.gr = gr; + return ptr; +} + +static unw_rec_list * +output_lc_psprel (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (lc_psprel); + ptr->r.record.p.pspoff = offset; + return ptr; +} + +static unw_rec_list * +output_lc_sprel (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (lc_sprel); + ptr->r.record.p.spoff = offset; + return ptr; +} + +static unw_rec_list * +output_fpsr_when () +{ + unw_rec_list *ptr = alloc_record (fpsr_when); + return ptr; +} + +static unw_rec_list * +output_fpsr_gr (gr) + unsigned int gr; +{ + unw_rec_list *ptr = alloc_record (fpsr_gr); + ptr->r.record.p.gr = gr; + return ptr; +} + +static unw_rec_list * +output_fpsr_psprel (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (fpsr_psprel); + ptr->r.record.p.pspoff = offset; + return ptr; +} + +static unw_rec_list * +output_fpsr_sprel (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (fpsr_sprel); + ptr->r.record.p.spoff = offset; + return ptr; +} + +static unw_rec_list * +output_priunat_when_gr () +{ + unw_rec_list *ptr = alloc_record (priunat_when_gr); + return ptr; +} + +static unw_rec_list * +output_priunat_when_mem () +{ + unw_rec_list *ptr = alloc_record (priunat_when_mem); + return ptr; +} + +static unw_rec_list * +output_priunat_gr (gr) + unsigned int gr; +{ + unw_rec_list *ptr = alloc_record (priunat_gr); + ptr->r.record.p.gr = gr; + return ptr; +} + +static unw_rec_list * +output_priunat_psprel (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (priunat_psprel); + ptr->r.record.p.pspoff = offset; + return ptr; +} + +static unw_rec_list * +output_priunat_sprel (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (priunat_sprel); + ptr->r.record.p.spoff = offset; + return ptr; +} + +static unw_rec_list * +output_bsp_when () +{ + unw_rec_list *ptr = alloc_record (bsp_when); + return ptr; +} + +static unw_rec_list * +output_bsp_gr (gr) + unsigned int gr; +{ + unw_rec_list *ptr = alloc_record (bsp_gr); + ptr->r.record.p.gr = gr; + return ptr; +} + +static unw_rec_list * +output_bsp_psprel (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (bsp_psprel); + ptr->r.record.p.pspoff = offset; + return ptr; +} + +static unw_rec_list * +output_bsp_sprel (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (bsp_sprel); + ptr->r.record.p.spoff = offset; + return ptr; +} + +static unw_rec_list * +output_bspstore_when () +{ + unw_rec_list *ptr = alloc_record (bspstore_when); + return ptr; +} + +static unw_rec_list * +output_bspstore_gr (gr) + unsigned int gr; +{ + unw_rec_list *ptr = alloc_record (bspstore_gr); + ptr->r.record.p.gr = gr; + return ptr; +} + +static unw_rec_list * +output_bspstore_psprel (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (bspstore_psprel); + ptr->r.record.p.pspoff = offset; + return ptr; +} + +static unw_rec_list * +output_bspstore_sprel (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (bspstore_sprel); + ptr->r.record.p.spoff = offset; + return ptr; +} + +static unw_rec_list * +output_rnat_when () +{ + unw_rec_list *ptr = alloc_record (rnat_when); + return ptr; +} + +static unw_rec_list * +output_rnat_gr (gr) + unsigned int gr; +{ + unw_rec_list *ptr = alloc_record (rnat_gr); + ptr->r.record.p.gr = gr; + return ptr; +} + +static unw_rec_list * +output_rnat_psprel (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (rnat_psprel); + ptr->r.record.p.pspoff = offset; + return ptr; +} + +static unw_rec_list * +output_rnat_sprel (offset) + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (rnat_sprel); + ptr->r.record.p.spoff = offset; + return ptr; +} + +static unw_rec_list * +output_epilogue () +{ + unw_rec_list *ptr = NULL; + return ptr; +} + +static unw_rec_list * +output_label_state () +{ + unw_rec_list *ptr = NULL; + return ptr; +} + +static unw_rec_list * +output_copy_state () +{ + unw_rec_list *ptr = NULL; + return ptr; +} + +static unw_rec_list * +output_spill_psprel (reg, offset) + unsigned int reg; + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (spill_psprel); + ptr->r.record.x.reg = reg; + ptr->r.record.x.pspoff = offset; + return ptr; +} + +static unw_rec_list * +output_spill_sprel (reg, offset) + unsigned int reg; + unsigned int offset; +{ + unw_rec_list *ptr = alloc_record (spill_sprel); + ptr->r.record.x.reg = reg; + ptr->r.record.x.spoff = offset; + return ptr; +} + +static unw_rec_list * +output_spill_psprel_p (reg, offset, predicate) + unsigned int reg; + unsigned int offset; + unsigned int predicate; +{ + unw_rec_list *ptr = alloc_record (spill_psprel_p); + ptr->r.record.x.reg = reg; + ptr->r.record.x.pspoff = offset; + ptr->r.record.x.qp = predicate; + return ptr; +} + +static unw_rec_list * +output_spill_sprel_p (reg, offset, predicate) + unsigned int reg; + unsigned int offset; + unsigned int predicate; +{ + unw_rec_list *ptr = alloc_record (spill_sprel_p); + ptr->r.record.x.reg = reg; + ptr->r.record.x.spoff = offset; + ptr->r.record.x.qp = predicate; + return ptr; +} + +static unw_rec_list * +output_spill_reg (reg, targ_reg, xy) + unsigned int reg; + unsigned int targ_reg; + unsigned int xy; +{ + unw_rec_list *ptr = alloc_record (spill_reg); + ptr->r.record.x.reg = reg; + ptr->r.record.x.treg = targ_reg; + ptr->r.record.x.xy = xy; + return ptr; +} + +static unw_rec_list * +output_spill_reg_p (reg, targ_reg, xy, predicate) + unsigned int reg; + unsigned int targ_reg; + unsigned int xy; + unsigned int predicate; +{ + unw_rec_list *ptr = alloc_record (spill_reg_p); + ptr->r.record.x.reg = reg; + ptr->r.record.x.treg = targ_reg; + ptr->r.record.x.xy = xy; + ptr->r.record.x.qp = predicate; + return ptr; +} + +/* Given a unw_rec_list process the correct format with the + specified function. */ +static void +process_one_record (ptr, f) + unw_rec_list *ptr; + vbyte_func f; +{ + switch (ptr->r.type) + { + case prologue: + case body: + output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); + break; + case prologue_gr: + output_R2_format (f, ptr->r.record.r.mask, + ptr->r.record.r.grsave, ptr->r.record.r.rlen); + break; + case mem_stack_f: + case mem_stack_v: + output_P7_format (f, ptr->r.type, ptr->r.record.p.t, + ptr->r.record.p.size); + break; + case psp_gr: + case rp_gr: + case pfs_gr: + case preds_gr: + case unat_gr: + case lc_gr: + case fpsr_gr: + case priunat_gr: + case bsp_gr: + case bspstore_gr: + case rnat_gr: + output_P3_format (f, ptr->r.type, ptr->r.record.p.gr); + break; + case rp_br: + output_P3_format (f, rp_br, ptr->r.record.p.br); + break; + case psp_sprel: + output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0); + break; + case rp_when: + case pfs_when: + case preds_when: + case unat_when: + case lc_when: + case fpsr_when: + output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0); + break; + case rp_psprel: + case pfs_psprel: + case preds_psprel: + case unat_psprel: + case lc_psprel: + case fpsr_psprel: + case spill_base: + output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0); + break; + case rp_sprel: + case pfs_sprel: + case preds_sprel: + case unat_sprel: + case lc_sprel: + case fpsr_sprel: + case priunat_sprel: + case bsp_sprel: + case bspstore_sprel: + case rnat_sprel: + output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff); + break; + case fr_mem: + case gr_mem: + output_P6_format (f, ptr->r.type, ptr->r.record.p.rmask); + break; + case frgr_mem: + output_P5_format (f, ptr->r.record.p.grmask, ptr->r.record.p.frmask); + break; + case gr_gr: + output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr); + break; + case br_mem: + output_P1_format (f, ptr->r.record.p.brmask); + break; + case br_gr: + output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr); + break; + case spill_mask: + as_bad ("spill_mask record unimplemented."); + break; + case priunat_when_gr: + case priunat_when_mem: + case bsp_when: + case bspstore_when: + case rnat_when: + output_P8_format (f, ptr->r.type, ptr->r.record.p.t); + break; + case priunat_psprel: + case bsp_psprel: + case bspstore_psprel: + case rnat_psprel: + output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff); + break; + case epilogue: + as_bad ("epilogue record unimplemented."); + break; + case label_state: + as_bad ("label_state record unimplemented."); + break; + case copy_state: + as_bad ("copy_state record unimplemented."); + break; + case spill_psprel: + case spill_sprel: + case spill_reg: + case spill_psprel_p: + case spill_sprel_p: + case spill_reg_p: + as_bad ("spill_* record unimplemented."); + break; + default: + as_bad ("record_type_not_valid"); + break; + } +} + +/* Given a unw_rec_list list, process all the records with + the specified function. */ +static void +process_unw_records (list, f) + unw_rec_list *list; + vbyte_func f; +{ + unw_rec_list *ptr; + for (ptr = list; ptr; ptr = ptr->next) + process_one_record (ptr, f); +} + +/* Determine the size of a record list in bytes. */ +static int +calc_record_size (list) + unw_rec_list *list; +{ + vbyte_count = 0; + process_unw_records (list, count_output); + return vbyte_count; +} + +/* Given a complete record list, process any records which have + unresolved fields, (ie length counts for a prologue). After + this has been run, all neccessary information should be available + within each record to generate an image. */ +static void +fixup_unw_records (list) + unw_rec_list *list; +{ + unw_rec_list *ptr; + unsigned long first_addr = 0; + for (ptr = list; ptr; ptr = ptr->next) + { + if (ptr->slot_number == SLOT_NUM_NOT_SET) + as_bad (" Insn slot not set in unwind record."); + switch (ptr->r.type) + { + case prologue: + case prologue_gr: + case body: + { + unw_rec_list *last; + int size; + unsigned long last_addr; + first_addr = ptr->slot_number; + ptr->slot_number = 0; + /* Find either the next body/prologue start, or the end of + the list, and determine the size of the region. */ + for (last = ptr; last->next != NULL; last = last->next) + if (last->next->r.type == prologue + || last->next->r.type == prologue_gr + || last->next->r.type == body) + { + break; + } + last_addr = last->slot_number; + size = ((last_addr - first_addr) / 16) * 3 + last_addr % 4; + ptr->r.record.r.rlen = size; + break; + } + case mem_stack_f: + case mem_stack_v: + case rp_when: + case pfs_when: + case preds_when: + case unat_when: + case lc_when: + case fpsr_when: + case priunat_when_gr: + case priunat_when_mem: + case bsp_when: + case bspstore_when: + case rnat_when: + { + /* All the time fields. */ + int x = ptr->slot_number - first_addr; + ptr->r.record.p.t = (x / 16) * 3 + (ptr->slot_number % 4); + break; + } + /* TODO. We also need to combine all the register masks into a single + record. (Ie, all the save.g save.gf, save.f and save.br's) */ + } + } +} + +/* Generate an unwind image from a record list. Returns the number of + bytes in the resulting image. The memory image itselof is returned + in the 'ptr' parameter. */ +static int +output_unw_records (list, ptr) + unw_rec_list *list; + void **ptr; +{ + int size, x, extra = 0; + unsigned char *mem; + + fixup_unw_records (list); + size = calc_record_size (list); + + /* pad to 8 byte boundry. */ + x = size % 8; + if (x != 0) + extra = 8 - x; + /* Add 8 for the header + 8 more bytes for the personality offset. */ + mem = xmalloc (size + extra + 16); + + vbyte_mem_ptr = mem + 8; + /* Clear the padding area and personality. */ + memset (mem + 8 + size, 0 , extra + 8); + /* Initialize the header area. */ + md_number_to_chars (mem, 1, 2); /* version number. */ + md_number_to_chars (mem + 2, 0x03, 2); /* Set E and U handler bits. */ + + /* Length in double words. */ + md_number_to_chars (mem + 4, (size + extra) / 8, 4); + + process_unw_records (list, output_vbyte_mem); + + *ptr = mem; + return size + extra + 16; +} + +static void +dot_radix (dummy) + int dummy; +{ + int radix; + + SKIP_WHITESPACE (); + radix = *input_line_pointer++; + + if (radix != 'C' && !is_end_of_line[(unsigned char) radix]) + { + as_bad ("Radix `%c' unsupported", *input_line_pointer); + ignore_rest_of_line (); + return; + } +} + +/* .sbss, .bss etc. are macros that expand into ".section SECNAME". */ +static void +dot_special_section (which) + int which; +{ + set_section ((char *) special_section_name[which]); +} + +static void +add_unwind_entry (ptr) + unw_rec_list *ptr; +{ + if (unwind_tail) + unwind_tail->next = ptr; + else + unwind_list = ptr; + unwind_tail = ptr; + + /* The current entry can in fact be a chain of unwind entries. */ + if (current_unwind_entry == NULL) + current_unwind_entry = ptr; +} + +static void +dot_fframe (dummy) + int dummy; +{ + expressionS e; + parse_operand (&e); + + if (e.X_op != O_constant) + as_bad ("Operand to .fframe must be a constant"); + else + { + add_unwind_entry (output_mem_stack_f (e.X_add_number)); + } +} + +static void +dot_vframe (dummy) + int dummy; +{ + discard_rest_of_line (); +} + +static void +dot_save (dummy) + int dummy; +{ + expressionS e1, e2; + int sep; + int reg1, reg2; + + sep = parse_operand (&e1); + if (sep != ',') + as_bad ("No second operand to .save"); + sep = parse_operand (&e2); + + reg1 = e1.X_add_number - REG_AR; + reg2 = e2.X_add_number - REG_GR; + + /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ + if (e1.X_op == O_register + && ((reg1 >=0 && reg1 < 128) || reg1 == REG_BR - REG_AR)) + { + if (e2.X_op == O_register && reg2 >=0 && reg2 < 128) + { + switch (reg1) + { + case 17: /* ar.bsp */ + add_unwind_entry (output_bsp_when ()); + add_unwind_entry (output_bsp_gr (reg2)); + break; + case 18: /* ar.bspstore */ + add_unwind_entry (output_bspstore_when ()); + add_unwind_entry (output_bspstore_gr (reg2)); + break; + case 19: /* ar.rnat */ + add_unwind_entry (output_rnat_when ()); + add_unwind_entry (output_rnat_gr (reg2)); + break; + case 36: /* ar.unat */ + add_unwind_entry (output_unat_when ()); + add_unwind_entry (output_unat_gr (reg2)); + break; + case 40: /* ar.fpsr */ + add_unwind_entry (output_fpsr_when ()); + add_unwind_entry (output_fpsr_gr (reg2)); + break; + case 64: /* ar.pfs */ + add_unwind_entry (output_pfs_when ()); + add_unwind_entry (output_pfs_gr (reg2)); + break; + case 65: /* ar.lc */ + add_unwind_entry (output_lc_when ()); + add_unwind_entry (output_lc_gr (reg2)); + break; + case REG_BR - REG_AR: /* rp */ + add_unwind_entry (output_rp_when ()); + add_unwind_entry (output_rp_gr (reg2)); + break; + default: + as_bad ("first operand is unknown application register"); + } + } + else + as_bad (" Second operand not a valid register"); + } + else + as_bad ("First operand not a valid register"); +} + +static void +dot_restore (dummy) + int dummy; +{ + discard_rest_of_line (); +} + +static int +generate_unwind_image () +{ + int size; + unsigned char *unw_rec; + int x; + + /* Generate the unwind record. */ + size = output_unw_records (unwind_list, &unw_rec); + if (size % 4 != 0) + as_bad ("Unwind record is ont a multiple of 4 bytes."); + + /* If there are unwind records, switch sections, and output the info. */ + if (size != 0) + { + int x; + unsigned char *where; + unsigned char *personality; + expressionS exp; + char *save; + set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND_INFO]); + + /* Set expression which points to start of unwind descriptor area. */ + unwind_info = expr_build_dot (); + + where = (unsigned char *)frag_more (size); + + /* Issue a label for this address, and keep track of it to put it + in the unwind section. */ + + /* Copy the information from the unwind record into this section. The + data is already in the correct byte order. */ + memcpy (where, unw_rec, size); + /* Add the personality address to the image. */ + if (personality_routine != 0) + { + exp.X_op = O_symbol; + exp.X_add_symbol = personality_routine; + exp.X_add_number = 0; + fix_new_exp (frag_now, frag_now_fix () - 8, 8, + &exp, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB); + personality_routine = 0; + } + obj_elf_previous (0); + } + + free_list_records (unwind_list); + unwind_list = unwind_tail = current_unwind_entry = NULL; + + return size; +} + +static void +dot_handlerdata (dummy) + int dummy; +{ + generate_unwind_image (); +} + +static void +dot_unwentry (dummy) + int dummy; +{ + discard_rest_of_line (); +} + +static void +dot_altrp (dummy) + int dummy; +{ + discard_rest_of_line (); +} + +static void +dot_savesp (dummy) + int dummy; +{ + expressionS e1, e2; + int sep; + int reg1, val; + + sep = parse_operand (&e1); + if (sep != ',') + as_bad ("No second operand to .savesp"); + sep = parse_operand (&e2); + + reg1 = e1.X_add_number - REG_AR; + val = e2.X_add_number; + + /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ + if (e1.X_op == O_register + && ((reg1 >=0 && reg1 < 128) || reg1 == REG_BR - REG_AR || reg1 == REG_PR - REG_AR)) + { + if (e2.X_op == O_constant) + { + switch (reg1) + { + case 17: /* ar.bsp */ + add_unwind_entry (output_bsp_when ()); + add_unwind_entry (output_bsp_sprel (val)); + break; + case 18: /* ar.bspstore */ + add_unwind_entry (output_bspstore_when ()); + add_unwind_entry (output_bspstore_sprel (val)); + break; + case 19: /* ar.rnat */ + add_unwind_entry (output_rnat_when ()); + add_unwind_entry (output_rnat_sprel (val)); + break; + case 36: /* ar.unat */ + add_unwind_entry (output_unat_when ()); + add_unwind_entry (output_unat_sprel (val)); + break; + case 40: /* ar.fpsr */ + add_unwind_entry (output_fpsr_when ()); + add_unwind_entry (output_fpsr_sprel (val)); + break; + case 64: /* ar.pfs */ + add_unwind_entry (output_pfs_when ()); + add_unwind_entry (output_pfs_sprel (val)); + break; + case 65: /* ar.lc */ + add_unwind_entry (output_lc_when ()); + add_unwind_entry (output_lc_sprel (val)); + break; + case REG_BR - REG_AR: /* rp */ + add_unwind_entry (output_rp_when ()); + add_unwind_entry (output_rp_sprel (val)); + break; + case REG_PR - REG_AR: /* Predicate registers. */ + add_unwind_entry (output_preds_when ()); + add_unwind_entry (output_preds_sprel (val)); + break; + default: + as_bad ("first operand is unknown application register"); + } + } + else + as_bad (" Second operand not a valid constant"); + } + else + as_bad ("First operand not a valid register"); +} + +static void +dot_savepsp (dummy) + int dummy; +{ + discard_rest_of_line (); +} + +static void +dot_saveg (dummy) + int dummy; +{ + expressionS e1, e2; + int sep; + sep = parse_operand (&e1); + if (sep == ',') + parse_operand (&e2); + + if (e1.X_op != O_constant) + as_bad ("First operand to .save.g must be a constant."); + else + { + int grmask = e1.X_add_number; + if (sep != ',') + add_unwind_entry (output_gr_mem (grmask)); + else + { + int reg = e2.X_add_number - REG_GR; + if (e2.X_op == O_register && reg >=0 && reg < 128) + add_unwind_entry (output_gr_gr (grmask, reg)); + else + as_bad ("Second operand is an invalid register."); + } + } +} + +static void +dot_savef (dummy) + int dummy; +{ + expressionS e1, e2; + int sep; + sep = parse_operand (&e1); + + if (e1.X_op != O_constant) + as_bad ("Operand to .save.f must be a constant."); + else + { + int frmask = e1.X_add_number; + add_unwind_entry (output_fr_mem (e1.X_add_number)); + } +} + +static void +dot_saveb (dummy) + int dummy; +{ + expressionS e1; + int sep; + sep = parse_operand (&e1); + + if (e1.X_op != O_constant) + as_bad ("Operand to .save.b must be a constant."); + else + { + int brmask = e1.X_add_number; + add_unwind_entry (output_br_mem (brmask)); + } +} + +static void +dot_savegf (dummy) + int dummy; +{ + expressionS e1, e2; + int sep; + sep = parse_operand (&e1); + if (sep == ',') + parse_operand (&e2); + + if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant) + as_bad ("Both operands of .save.gf must be constants."); + else + { + int grmask = e1.X_add_number; + int frmask = e2.X_add_number; + add_unwind_entry (output_frgr_mem (grmask, frmask)); + } +} + +static void +dot_spill (dummy) + int dummy; +{ + expressionS e; + parse_operand (&e); + + if (e.X_op != O_constant) + as_bad ("Operand to .spill must be a constant"); + else + { + add_unwind_entry (output_spill_base (e.X_add_number)); + } +} + +static void +dot_unwabi (dummy) + int dummy; +{ + discard_rest_of_line (); +} + +static void +dot_personality (dummy) + int dummy; +{ + char *name, *p, c; + SKIP_WHITESPACE (); + name = input_line_pointer; + c = get_symbol_end (); + p = input_line_pointer; + personality_routine = symbol_find_or_make (name); + *p = c; + SKIP_WHITESPACE (); + demand_empty_rest_of_line (); +} + +static void +dot_proc (dummy) + int dummy; +{ + char *name, *p, c; + symbolS *sym; + + proc_start = expr_build_dot (); + /* Parse names of main and alternate entry points and mark them s + function symbols: */ + while (1) + { + SKIP_WHITESPACE (); + name = input_line_pointer; + c = get_symbol_end (); + p = input_line_pointer; + sym = symbol_find_or_make (name); + if (proc_start == 0) + { + proc_start = sym; + } + symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION; + *p = c; + SKIP_WHITESPACE (); + if (*input_line_pointer != ',') + break; + ++input_line_pointer; + } + demand_empty_rest_of_line (); + ia64_do_align (16); + + unwind_list = unwind_tail = current_unwind_entry = NULL; + personality_routine = 0; +} + +static void +dot_body (dummy) + int dummy; +{ + unwind_prologue = 0; + add_unwind_entry (output_body ()); +} + +static void +dot_prologue (dummy) + int dummy; +{ + unwind_prologue = 1; + SKIP_WHITESPACE (); + if (! is_end_of_line[(unsigned char) *input_line_pointer]) + { + expressionS e1, e2; + char sep; + sep = parse_operand (&e1); + if (sep != ',') + as_bad ("No second operand to .prologue"); + sep = parse_operand (&e2); + + if (e1.X_op == O_constant) + { + if (e2.X_op == O_constant) + { + int mask = e1.X_add_number; + int reg = e2.X_add_number; + add_unwind_entry (output_prologue_gr (mask, reg)); + } + else + as_bad ("Second operand not a constant"); + } + else + as_bad ("First operand not a constant"); + } + else + add_unwind_entry (output_prologue ()); +} + +static void +dot_endp (dummy) + int dummy; +{ + expressionS e; + unsigned char *ptr; + int size; + long where; + segT saved_seg; + subsegT saved_subseg; + + saved_seg = now_seg; + saved_subseg = now_subseg; + + expression (&e); + demand_empty_rest_of_line (); + + insn_group_break (1, 0, 0); + ia64_flush_insns (); + + /* If there was a .handlerdata, we haven't generated an image yet. */ + if (unwind_info == 0) + { + generate_unwind_image (); + } + + subseg_set (md.last_text_seg, 0); + proc_end = expr_build_dot (); + + set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND]); + ptr = frag_more (24); + where = frag_now_fix () - 24; + + /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */ + e.X_op = O_pseudo_fixup; + e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; + e.X_add_number = 0; + e.X_add_symbol = proc_start; + ia64_cons_fix_new (frag_now, where, 8, &e); + + e.X_op = O_pseudo_fixup; + e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; + e.X_add_number = 0; + e.X_add_symbol = proc_end; + ia64_cons_fix_new (frag_now, where + 8, 8, &e); + + if (unwind_info != 0) + { + e.X_op = O_pseudo_fixup; + e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; + e.X_add_number = 0; + e.X_add_symbol = unwind_info; + ia64_cons_fix_new (frag_now, where + 16, 8, &e); + } + else + md_number_to_chars (ptr + 16, 0, 8); + + subseg_set (saved_seg, saved_subseg); + proc_start = proc_end = unwind_info = 0; +} + +static void +dot_template (template) + int template; +{ + CURR_SLOT.user_template = template; +} + +static void +dot_regstk (dummy) + int dummy; +{ + int ins, locs, outs, rots; + + if (is_it_end_of_statement ()) + ins = locs = outs = rots = 0; + else + { + ins = get_absolute_expression (); + if (*input_line_pointer++ != ',') + goto err; + locs = get_absolute_expression (); + if (*input_line_pointer++ != ',') + goto err; + outs = get_absolute_expression (); + if (*input_line_pointer++ != ',') + goto err; + rots = get_absolute_expression (); + } + set_regstack (ins, locs, outs, rots); + return; + + err: + as_bad ("Comma expected"); + ignore_rest_of_line (); +} + +static void +dot_rot (type) + int type; +{ + unsigned num_regs, num_alloced = 0; + struct dynreg **drpp, *dr; + int ch, base_reg = 0; + char *name, *start; + size_t len; + + switch (type) + { + case DYNREG_GR: base_reg = REG_GR + 32; break; + case DYNREG_FR: base_reg = REG_FR + 32; break; + case DYNREG_PR: base_reg = REG_P + 16; break; + default: break; + } + + /* first, remove existing names from hash table: */ + for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next) + { + hash_delete (md.dynreg_hash, dr->name); + dr->num_regs = 0; + } + + drpp = &md.dynreg[type]; + while (1) + { + start = input_line_pointer; + ch = get_symbol_end (); + *input_line_pointer = ch; + len = (input_line_pointer - start); + + SKIP_WHITESPACE (); + if (*input_line_pointer != '[') + { + as_bad ("Expected '['"); + goto err; + } + ++input_line_pointer; /* skip '[' */ + + num_regs = get_absolute_expression (); + + if (*input_line_pointer++ != ']') + { + as_bad ("Expected ']'"); + goto err; + } + SKIP_WHITESPACE (); + + num_alloced += num_regs; + switch (type) + { + case DYNREG_GR: + if (num_alloced > md.rot.num_regs) + { + as_bad ("Used more than the declared %d rotating registers", + md.rot.num_regs); + goto err; + } + break; + case DYNREG_FR: + if (num_alloced > 96) + { + as_bad ("Used more than the available 96 rotating registers"); + goto err; + } + break; + case DYNREG_PR: + if (num_alloced > 48) + { + as_bad ("Used more than the available 48 rotating registers"); + goto err; + } + break; + + default: + break; + } + + name = obstack_alloc (¬es, len + 1); + memcpy (name, start, len); + name[len] = '\0'; + + if (!*drpp) + { + *drpp = obstack_alloc (¬es, sizeof (*dr)); + memset (*drpp, 0, sizeof (*dr)); + } + + dr = *drpp; + dr->name = name; + dr->num_regs = num_regs; + dr->base = base_reg; + drpp = &dr->next; + base_reg += num_regs; + + if (hash_insert (md.dynreg_hash, name, dr)) + { + as_bad ("Attempt to redefine register set `%s'", name); + goto err; + } + + if (*input_line_pointer != ',') + break; + ++input_line_pointer; /* skip comma */ + SKIP_WHITESPACE (); + } + demand_empty_rest_of_line (); + return; + + err: + ignore_rest_of_line (); +} + +static void +dot_byteorder (byteorder) + int byteorder; +{ + target_big_endian = byteorder; +} + +static void +dot_psr (dummy) + int dummy; +{ + char *option; + int ch; + + while (1) + { + option = input_line_pointer; + ch = get_symbol_end (); + if (strcmp (option, "lsb") == 0) + md.flags &= ~EF_IA_64_BE; + else if (strcmp (option, "msb") == 0) + md.flags |= EF_IA_64_BE; + else if (strcmp (option, "abi32") == 0) + md.flags &= ~EF_IA_64_ABI64; + else if (strcmp (option, "abi64") == 0) + md.flags |= EF_IA_64_ABI64; + else + as_bad ("Unknown psr option `%s'", option); + *input_line_pointer = ch; + + SKIP_WHITESPACE (); + if (*input_line_pointer != ',') + break; + + ++input_line_pointer; + SKIP_WHITESPACE (); + } + demand_empty_rest_of_line (); +} + +static void +dot_alias (dummy) + int dummy; +{ + as_bad (".alias not implemented yet"); +} + +static void +dot_ln (dummy) + int dummy; +{ + new_logical_line (0, get_absolute_expression ()); + demand_empty_rest_of_line (); +} + +static char* +parse_section_name () +{ + char *name; + int len; + + SKIP_WHITESPACE (); + if (*input_line_pointer != '"') + { + as_bad ("Missing section name"); + ignore_rest_of_line (); + return 0; + } + name = demand_copy_C_string (&len); + if (!name) + { + ignore_rest_of_line (); + return 0; + } + SKIP_WHITESPACE (); + if (*input_line_pointer != ',') + { + as_bad ("Comma expected after section name"); + ignore_rest_of_line (); + return 0; + } + ++input_line_pointer; /* skip comma */ + return name; +} + +static void +dot_xdata (size) + int size; +{ + char *name = parse_section_name (); + if (!name) + return; + + set_section (name); + cons (size); + obj_elf_previous (0); +} + +/* Why doesn't float_cons() call md_cons_align() the way cons() does? */ +static void +stmt_float_cons (kind) + int kind; +{ + size_t size; + + switch (kind) + { + case 'd': size = 8; break; + case 'x': size = 10; break; + + case 'f': + default: + size = 4; + break; + } + ia64_do_align (size); + float_cons (kind); +} + +static void +stmt_cons_ua (size) + int size; +{ + int saved_auto_align = md.auto_align; + + md.auto_align = 0; + cons (size); + md.auto_align = saved_auto_align; +} + +static void +dot_xfloat_cons (kind) + int kind; +{ + char *name = parse_section_name (); + if (!name) + return; + + set_section (name); + stmt_float_cons (kind); + obj_elf_previous (0); +} + +static void +dot_xstringer (zero) + int zero; +{ + char *name = parse_section_name (); + if (!name) + return; + + set_section (name); + stringer (zero); + obj_elf_previous (0); +} + +static void +dot_xdata_ua (size) + int size; +{ + int saved_auto_align = md.auto_align; + char *name = parse_section_name (); + if (!name) + return; + + set_section (name); + md.auto_align = 0; + cons (size); + md.auto_align = saved_auto_align; + obj_elf_previous (0); +} + +static void +dot_xfloat_cons_ua (kind) + int kind; +{ + int saved_auto_align = md.auto_align; + char *name = parse_section_name (); + if (!name) + return; + + set_section (name); + md.auto_align = 0; + stmt_float_cons (kind); + md.auto_align = saved_auto_align; + obj_elf_previous (0); +} + +/* .reg.val <regname>,value */ +static void +dot_reg_val (dummy) + int dummy; +{ + expressionS reg; + + expression (®); + if (reg.X_op != O_register) + { + as_bad (_("Register name expected")); + ignore_rest_of_line (); + } + else if (*input_line_pointer++ != ',') + { + as_bad (_("Comma expected")); + ignore_rest_of_line (); + } + else + { + valueT value = get_absolute_expression (); + int regno = reg.X_add_number; + if (regno < REG_GR || regno > REG_GR+128) + as_warn (_("Register value annotation ignored")); + else + { + gr_values[regno-REG_GR].known = 1; + gr_values[regno-REG_GR].value = value; + gr_values[regno-REG_GR].path = md.path; + } + } + demand_empty_rest_of_line (); +} + +/* select dv checking mode + .auto + .explicit + .default + + A stop is inserted when changing modes + */ +static void +dot_dv_mode (type) + int type; +{ + if (md.manual_bundling) + as_warn (_("Directive invalid within a bundle")); + + if (type == 'E' || type == 'A') + md.mode_explicitly_set = 0; + else + md.mode_explicitly_set = 1; + + md.detect_dv = 1; + switch (type) + { + case 'A': + case 'a': + if (md.explicit_mode) + insn_group_break (1, 0, 0); + md.explicit_mode = 0; + break; + case 'E': + case 'e': + if (!md.explicit_mode) + insn_group_break (1, 0, 0); + md.explicit_mode = 1; + break; + default: + case 'd': + if (md.explicit_mode != md.default_explicit_mode) + insn_group_break (1, 0, 0); + md.explicit_mode = md.default_explicit_mode; + md.mode_explicitly_set = 0; + break; + } +} + +static void +print_prmask (mask) + valueT mask; +{ + int regno; + char *comma = ""; + for (regno = 0;regno < 64;regno++) + { + if (mask & ((valueT)1<<regno)) + { + fprintf (stderr, "%s p%d", comma, regno); + comma = ","; + } + } +} + +/* + .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear") + .pred.rel.imply p1, p2 (also .pred.rel "imply") + .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex") + .pred.safe_across_calls p1 [, p2 [,...]] + */ +static void +dot_pred_rel (type) + int type; +{ + valueT mask = 0; + int count = 0; + int p1 = -1, p2 = -1; + + if (type == 0) + { + if (*input_line_pointer != '"') + { + as_bad (_("Missing predicate relation type")); + ignore_rest_of_line (); + return; + } + else + { + int len; + char *form = demand_copy_C_string (&len); + if (strcmp (form, "mutex") == 0) + type = 'm'; + else if (strcmp (form, "clear") == 0) + type = 'c'; + else if (strcmp (form, "imply") == 0) + type = 'i'; + else + { + as_bad (_("Unrecognized predicate relation type")); + ignore_rest_of_line (); + return; + } + } + if (*input_line_pointer == ',') + ++input_line_pointer; + SKIP_WHITESPACE (); + } + + SKIP_WHITESPACE (); + while (1) + { + valueT bit = 1; + int regno; + + if (toupper (*input_line_pointer) != 'P' + || (regno = atoi (++input_line_pointer)) < 0 + || regno > 63) + { + as_bad (_("Predicate register expected")); + ignore_rest_of_line (); + return; + } + while (isdigit (*input_line_pointer)) + ++input_line_pointer; + if (p1 == -1) + p1 = regno; + else if (p2 == -1) + p2 = regno; + bit <<= regno; + if (mask & bit) + as_warn (_("Duplicate predicate register ignored")); + mask |= bit; count++; + /* see if it's a range */ + if (*input_line_pointer == '-') + { + valueT stop = 1; + ++input_line_pointer; + + if (toupper (*input_line_pointer) != 'P' + || (regno = atoi (++input_line_pointer)) < 0 + || regno > 63) + { + as_bad (_("Predicate register expected")); + ignore_rest_of_line (); + return; + } + while (isdigit (*input_line_pointer)) + ++input_line_pointer; + stop <<= regno; + if (bit >= stop) + { + as_bad (_("Bad register range")); + ignore_rest_of_line (); + return; + } + while (bit < stop) + { + bit <<= 1; + mask |= bit; count++; + } + SKIP_WHITESPACE (); + } + if (*input_line_pointer != ',') + break; + ++input_line_pointer; + SKIP_WHITESPACE (); + } + + switch (type) + { + case 'c': + if (count == 0) + mask = ~(valueT)0; + clear_qp_mutex (mask); + clear_qp_implies (mask, (valueT)0); + break; + case 'i': + if (count != 2 || p1 == -1 || p2 == -1) + as_bad (_("Predicate source and target required")); + else if (p1 == 0 || p2 == 0) + as_bad (_("Use of p0 is not valid in this context")); + else + add_qp_imply (p1, p2); + break; + case 'm': + if (count < 2) + { + as_bad (_("At least two PR arguments expected")); + break; + } + else if (mask & 1) + { + as_bad (_("Use of p0 is not valid in this context")); + break; + } + add_qp_mutex (mask); + break; + case 's': + /* note that we don't override any existing relations */ + if (count == 0) + { + as_bad (_("At least one PR argument expected")); + break; + } + if (md.debug_dv) + { + fprintf (stderr, "Safe across calls: "); + print_prmask (mask); + fprintf (stderr, "\n"); + } + qp_safe_across_calls = mask; + break; + } + demand_empty_rest_of_line (); +} + +/* .entry label [, label [, ...]] + Hint to DV code that the given labels are to be considered entry points. + Otherwise, only global labels are considered entry points. + */ +static void +dot_entry (dummy) + int dummy; +{ + const char *err; + char *name; + int c; + symbolS *symbolP; + + do + { + name = input_line_pointer; + c = get_symbol_end (); + symbolP = symbol_find_or_make (name); + + err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP); + if (err) + as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"), + name, err); + + *input_line_pointer = c; + SKIP_WHITESPACE (); + c = *input_line_pointer; + if (c == ',') + { + input_line_pointer++; + SKIP_WHITESPACE (); + if (*input_line_pointer == '\n') + c = '\n'; + } + } + while (c == ','); + + demand_empty_rest_of_line (); +} + +/* .mem.offset offset, base + "base" is used to distinguish between offsets from a different base. + */ +static void +dot_mem_offset (dummy) + int dummy; +{ + md.mem_offset.hint = 1; + md.mem_offset.offset = get_absolute_expression (); + if (*input_line_pointer != ',') + { + as_bad (_("Comma expected")); + ignore_rest_of_line (); + return; + } + ++input_line_pointer; + md.mem_offset.base = get_absolute_expression (); + demand_empty_rest_of_line (); +} + +/* ia64-specific pseudo-ops: */ +const pseudo_typeS md_pseudo_table[] = + { + { "radix", dot_radix, 0 }, + { "lcomm", s_lcomm_bytes, 1 }, + { "bss", dot_special_section, SPECIAL_SECTION_BSS }, + { "sbss", dot_special_section, SPECIAL_SECTION_SBSS }, + { "sdata", dot_special_section, SPECIAL_SECTION_SDATA }, + { "rodata", dot_special_section, SPECIAL_SECTION_RODATA }, + { "comment", dot_special_section, SPECIAL_SECTION_COMMENT }, + { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND }, + { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO }, + { "proc", dot_proc, 0 }, + { "body", dot_body, 0 }, + { "prologue", dot_prologue, 0 }, + { "endp", dot_endp }, + { "file", dwarf2_directive_file }, + { "loc", dwarf2_directive_loc }, + + { "fframe", dot_fframe }, + { "vframe", dot_vframe }, + { "save", dot_save }, + { "restore", dot_restore }, + { "handlerdata", dot_handlerdata }, + { "unwentry", dot_unwentry }, + { "alprp", dot_altrp }, + { "savesp", dot_savesp }, + { "savepsp", dot_savepsp }, + { "save.g", dot_saveg }, + { "save.f", dot_savef }, + { "save.b", dot_saveb }, + { "save.gf", dot_savegf }, + { "spill", dot_spill }, + { "unwabi", dot_unwabi }, + { "personality", dot_personality }, +#if 0 + { "estate", dot_estate }, +#endif + { "mii", dot_template, 0x0 }, + { "mli", dot_template, 0x2 }, /* old format, for compatibility */ + { "mlx", dot_template, 0x2 }, + { "mmi", dot_template, 0x4 }, + { "mfi", dot_template, 0x6 }, + { "mmf", dot_template, 0x7 }, + { "mib", dot_template, 0x8 }, + { "mbb", dot_template, 0x9 }, + { "bbb", dot_template, 0xb }, + { "mmb", dot_template, 0xc }, + { "mfb", dot_template, 0xe }, +#if 0 + { "lb", dot_scope, 0 }, + { "le", dot_scope, 1 }, +#endif + { "align", s_align_bytes, 0 }, + { "regstk", dot_regstk, 0 }, + { "rotr", dot_rot, DYNREG_GR }, + { "rotf", dot_rot, DYNREG_FR }, + { "rotp", dot_rot, DYNREG_PR }, + { "lsb", dot_byteorder, 0 }, + { "msb", dot_byteorder, 1 }, + { "psr", dot_psr, 0 }, + { "alias", dot_alias, 0 }, + { "ln", dot_ln, 0 }, /* source line info (for debugging) */ + + { "xdata1", dot_xdata, 1 }, + { "xdata2", dot_xdata, 2 }, + { "xdata4", dot_xdata, 4 }, + { "xdata8", dot_xdata, 8 }, + { "xreal4", dot_xfloat_cons, 'f' }, + { "xreal8", dot_xfloat_cons, 'd' }, + { "xreal10", dot_xfloat_cons, 'x' }, + { "xstring", dot_xstringer, 0 }, + { "xstringz", dot_xstringer, 1 }, + + /* unaligned versions: */ + { "xdata2.ua", dot_xdata_ua, 2 }, + { "xdata4.ua", dot_xdata_ua, 4 }, + { "xdata8.ua", dot_xdata_ua, 8 }, + { "xreal4.ua", dot_xfloat_cons_ua, 'f' }, + { "xreal8.ua", dot_xfloat_cons_ua, 'd' }, + { "xreal10.ua", dot_xfloat_cons_ua, 'x' }, + + /* annotations/DV checking support */ + { "entry", dot_entry, 0 }, + { "mem.offset", dot_mem_offset }, + { "pred.rel", dot_pred_rel, 0 }, + { "pred.rel.clear", dot_pred_rel, 'c' }, + { "pred.rel.imply", dot_pred_rel, 'i' }, + { "pred.rel.mutex", dot_pred_rel, 'm' }, + { "pred.safe_across_calls", dot_pred_rel, 's' }, + { "reg.val", dot_reg_val }, + { "auto", dot_dv_mode, 'a' }, + { "explicit", dot_dv_mode, 'e' }, + { "default", dot_dv_mode, 'd' }, + + { NULL, 0, 0 } + }; + +static const struct pseudo_opcode + { + const char *name; + void (*handler) (int); + int arg; + } +pseudo_opcode[] = + { + /* these are more like pseudo-ops, but don't start with a dot */ + { "data1", cons, 1 }, + { "data2", cons, 2 }, + { "data4", cons, 4 }, + { "data8", cons, 8 }, + { "real4", stmt_float_cons, 'f' }, + { "real8", stmt_float_cons, 'd' }, + { "real10", stmt_float_cons, 'x' }, + { "string", stringer, 0 }, + { "stringz", stringer, 1 }, + + /* unaligned versions: */ + { "data2.ua", stmt_cons_ua, 2 }, + { "data4.ua", stmt_cons_ua, 4 }, + { "data8.ua", stmt_cons_ua, 8 }, + { "real4.ua", float_cons, 'f' }, + { "real8.ua", float_cons, 'd' }, + { "real10.ua", float_cons, 'x' }, + }; + +/* Declare a register by creating a symbol for it and entering it in + the symbol table. */ +static symbolS* +declare_register (name, regnum) + const char *name; + int regnum; +{ + const char *err; + symbolS *sym; + + sym = symbol_new (name, reg_section, regnum, &zero_address_frag); + + err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym); + if (err) + as_fatal ("Inserting \"%s\" into register table failed: %s", + name, err); + + return sym; +} + +static void +declare_register_set (prefix, num_regs, base_regnum) + const char *prefix; + int num_regs; + int base_regnum; +{ + char name[8]; + int i; + + for (i = 0; i < num_regs; ++i) + { + sprintf (name, "%s%u", prefix, i); + declare_register (name, base_regnum + i); + } +} + +static unsigned int +operand_width (opnd) + enum ia64_opnd opnd; +{ + const struct ia64_operand *odesc = &elf64_ia64_operands[opnd]; + unsigned int bits = 0; + int i; + + bits = 0; + for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i) + bits += odesc->field[i].bits; + + return bits; +} + +static int +operand_match (idesc, index, e) + const struct ia64_opcode *idesc; + int index; + expressionS *e; +{ + enum ia64_opnd opnd = idesc->operands[index]; + int bits, relocatable = 0; + struct insn_fix *fix; + bfd_signed_vma val; + + switch (opnd) + { + /* constants: */ + + case IA64_OPND_AR_CCV: + if (e->X_op == O_register && e->X_add_number == REG_AR + 32) + return 1; + break; + + case IA64_OPND_AR_PFS: + if (e->X_op == O_register && e->X_add_number == REG_AR + 64) + return 1; + break; + + case IA64_OPND_GR0: + if (e->X_op == O_register && e->X_add_number == REG_GR + 0) + return 1; + break; + + case IA64_OPND_IP: + if (e->X_op == O_register && e->X_add_number == REG_IP) + return 1; + break; + + case IA64_OPND_PR: + if (e->X_op == O_register && e->X_add_number == REG_PR) + return 1; + break; + + case IA64_OPND_PR_ROT: + if (e->X_op == O_register && e->X_add_number == REG_PR_ROT) + return 1; + break; + + case IA64_OPND_PSR: + if (e->X_op == O_register && e->X_add_number == REG_PSR) + return 1; + break; + + case IA64_OPND_PSR_L: + if (e->X_op == O_register && e->X_add_number == REG_PSR_L) + return 1; + break; + + case IA64_OPND_PSR_UM: + if (e->X_op == O_register && e->X_add_number == REG_PSR_UM) + return 1; + break; + + case IA64_OPND_C1: + if (e->X_op == O_constant && e->X_add_number == 1) + return 1; + break; + + case IA64_OPND_C8: + if (e->X_op == O_constant && e->X_add_number == 8) + return 1; + break; + + case IA64_OPND_C16: + if (e->X_op == O_constant && e->X_add_number == 16) + return 1; + break; + + /* register operands: */ + + case IA64_OPND_AR3: + if (e->X_op == O_register && e->X_add_number >= REG_AR + && e->X_add_number < REG_AR + 128) + return 1; + break; + + case IA64_OPND_B1: + case IA64_OPND_B2: + if (e->X_op == O_register && e->X_add_number >= REG_BR + && e->X_add_number < REG_BR + 8) + return 1; + break; + + case IA64_OPND_CR3: + if (e->X_op == O_register && e->X_add_number >= REG_CR + && e->X_add_number < REG_CR + 128) + return 1; + break; + + case IA64_OPND_F1: + case IA64_OPND_F2: + case IA64_OPND_F3: + case IA64_OPND_F4: + if (e->X_op == O_register && e->X_add_number >= REG_FR + && e->X_add_number < REG_FR + 128) + return 1; + break; + + case IA64_OPND_P1: + case IA64_OPND_P2: + if (e->X_op == O_register && e->X_add_number >= REG_P + && e->X_add_number < REG_P + 64) + return 1; + break; + + case IA64_OPND_R1: + case IA64_OPND_R2: + case IA64_OPND_R3: + if (e->X_op == O_register && e->X_add_number >= REG_GR + && e->X_add_number < REG_GR + 128) + return 1; + break; + + case IA64_OPND_R3_2: + if (e->X_op == O_register && e->X_add_number >= REG_GR + && e->X_add_number < REG_GR + 4) + return 1; + break; + + /* indirect operands: */ + case IA64_OPND_CPUID_R3: + case IA64_OPND_DBR_R3: + case IA64_OPND_DTR_R3: + case IA64_OPND_ITR_R3: + case IA64_OPND_IBR_R3: + case IA64_OPND_MSR_R3: + case IA64_OPND_PKR_R3: + case IA64_OPND_PMC_R3: + case IA64_OPND_PMD_R3: + case IA64_OPND_RR_R3: + if (e->X_op == O_index && e->X_op_symbol + && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID + == opnd - IA64_OPND_CPUID_R3)) + return 1; + break; + + case IA64_OPND_MR3: + if (e->X_op == O_index && !e->X_op_symbol) + return 1; + break; + + /* immediate operands: */ + case IA64_OPND_CNT2a: + case IA64_OPND_LEN4: + case IA64_OPND_LEN6: + bits = operand_width (idesc->operands[index]); + if (e->X_op == O_constant + && (bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits)) + return 1; + break; + + case IA64_OPND_CNT2b: + if (e->X_op == O_constant + && (bfd_vma) (e->X_add_number - 1) < 3) + return 1; + break; + + case IA64_OPND_CNT2c: + val = e->X_add_number; + if (e->X_op == O_constant + && (val == 0 || val == 7 || val == 15 || val == 16)) + return 1; + break; + + case IA64_OPND_SOR: + /* SOR must be an integer multiple of 8 */ + if (e->X_add_number & 0x7) + break; + case IA64_OPND_SOF: + case IA64_OPND_SOL: + if (e->X_op == O_constant && + (bfd_vma) e->X_add_number <= 96) + return 1; + break; + + case IA64_OPND_IMMU62: + if (e->X_op == O_constant) + { + if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62)) + return 1; + } + else + { + /* FIXME -- need 62-bit relocation type */ + as_bad (_("62-bit relocation not yet implemented")); + } + break; + + case IA64_OPND_IMMU64: + if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup + || e->X_op == O_subtract) + { + fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; + fix->code = BFD_RELOC_IA64_IMM64; + if (e->X_op != O_subtract) + { + fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); + if (e->X_op == O_pseudo_fixup) + e->X_op = O_symbol; + } + + fix->opnd = idesc->operands[index]; + fix->expr = *e; + fix->is_pcrel = 0; + ++CURR_SLOT.num_fixups; + return 1; + } + else if (e->X_op == O_constant) + return 1; + break; + + case IA64_OPND_CCNT5: + case IA64_OPND_CNT5: + case IA64_OPND_CNT6: + case IA64_OPND_CPOS6a: + case IA64_OPND_CPOS6b: + case IA64_OPND_CPOS6c: + case IA64_OPND_IMMU2: + case IA64_OPND_IMMU7a: + case IA64_OPND_IMMU7b: + case IA64_OPND_IMMU9: + case IA64_OPND_IMMU21: + case IA64_OPND_IMMU24: + case IA64_OPND_MBTYPE4: + case IA64_OPND_MHTYPE8: + case IA64_OPND_POS6: + bits = operand_width (idesc->operands[index]); + if (e->X_op == O_constant + && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) + return 1; + break; + + case IA64_OPND_IMM44: + /* least 16 bits must be zero */ + if ((e->X_add_number & 0xffff) != 0) + as_warn (_("lower 16 bits of mask ignored")); + + if (e->X_op == O_constant + && ((e->X_add_number >= 0 + && e->X_add_number < ((bfd_vma) 1 << 44)) + || (e->X_add_number < 0 + && -e->X_add_number <= ((bfd_vma) 1 << 44)))) + { + /* sign-extend */ + if (e->X_add_number >= 0 + && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0) + { + e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1); + } + return 1; + } + break; + + case IA64_OPND_IMM17: + /* bit 0 is a don't care (pr0 is hardwired to 1) */ + if (e->X_op == O_constant + && ((e->X_add_number >= 0 + && e->X_add_number < ((bfd_vma) 1 << 17)) + || (e->X_add_number < 0 + && -e->X_add_number <= ((bfd_vma) 1 << 17)))) + { + /* sign-extend */ + if (e->X_add_number >= 0 + && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0) + { + e->X_add_number |= ~(((bfd_vma)1 << 17) - 1); + } + return 1; + } + break; + + case IA64_OPND_IMM14: + case IA64_OPND_IMM22: + relocatable = 1; + case IA64_OPND_IMM1: + case IA64_OPND_IMM8: + case IA64_OPND_IMM8U4: + case IA64_OPND_IMM8M1: + case IA64_OPND_IMM8M1U4: + case IA64_OPND_IMM8M1U8: + case IA64_OPND_IMM9a: + case IA64_OPND_IMM9b: + bits = operand_width (idesc->operands[index]); + if (relocatable && (e->X_op == O_symbol + || e->X_op == O_subtract + || e->X_op == O_pseudo_fixup)) + { + fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; + + if (idesc->operands[index] == IA64_OPND_IMM14) + fix->code = BFD_RELOC_IA64_IMM14; + else + fix->code = BFD_RELOC_IA64_IMM22; + + if (e->X_op != O_subtract) + { + fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); + if (e->X_op == O_pseudo_fixup) + e->X_op = O_symbol; + } + + fix->opnd = idesc->operands[index]; + fix->expr = *e; + fix->is_pcrel = 0; + ++CURR_SLOT.num_fixups; + return 1; + } + else if (e->X_op != O_constant + && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8)) + return 0; + + if (opnd == IA64_OPND_IMM8M1U4) + { + /* Zero is not valid for unsigned compares that take an adjusted + constant immediate range. */ + if (e->X_add_number == 0) + return 0; + + /* Sign-extend 32-bit unsigned numbers, so that the following range + checks will work. */ + val = e->X_add_number; + if (((val & (~(bfd_vma)0 << 32)) == 0) + && ((val & ((bfd_vma)1 << 31)) != 0)) + val = ((val << 32) >> 32); + + /* Check for 0x100000000. This is valid because + 0x100000000-1 is the same as ((uint32_t) -1). */ + if (val == ((bfd_signed_vma) 1 << 32)) + return 1; + + val = val - 1; + } + else if (opnd == IA64_OPND_IMM8M1U8) + { + /* Zero is not valid for unsigned compares that take an adjusted + constant immediate range. */ + if (e->X_add_number == 0) + return 0; + + /* Check for 0x10000000000000000. */ + if (e->X_op == O_big) + { + if (generic_bignum[0] == 0 + && generic_bignum[1] == 0 + && generic_bignum[2] == 0 + && generic_bignum[3] == 0 + && generic_bignum[4] == 1) + return 1; + else + return 0; + } + else + val = e->X_add_number - 1; + } + else if (opnd == IA64_OPND_IMM8M1) + val = e->X_add_number - 1; + else if (opnd == IA64_OPND_IMM8U4) + { + /* Sign-extend 32-bit unsigned numbers, so that the following range + checks will work. */ + val = e->X_add_number; + if (((val & (~(bfd_vma)0 << 32)) == 0) + && ((val & ((bfd_vma)1 << 31)) != 0)) + val = ((val << 32) >> 32); + } + else + val = e->X_add_number; + + if ((val >= 0 && val < ((bfd_vma) 1 << (bits - 1))) + || (val < 0 && -val <= ((bfd_vma) 1 << (bits - 1)))) + return 1; + break; + + case IA64_OPND_INC3: + /* +/- 1, 4, 8, 16 */ + val = e->X_add_number; + if (val < 0) + val = -val; + if (e->X_op == O_constant + && (val == 1 || val == 4 || val == 8 || val == 16)) + return 1; + break; + + case IA64_OPND_TGT25: + case IA64_OPND_TGT25b: + case IA64_OPND_TGT25c: + case IA64_OPND_TGT64: + if (e->X_op == O_symbol) + { + fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; + if (opnd == IA64_OPND_TGT25) + fix->code = BFD_RELOC_IA64_PCREL21F; + else if (opnd == IA64_OPND_TGT25b) + fix->code = BFD_RELOC_IA64_PCREL21M; + else if (opnd == IA64_OPND_TGT25c) + fix->code = BFD_RELOC_IA64_PCREL21B; + else + /* FIXME -- use appropriate relocation type */ + as_bad (_("long branch targets not implemented")); + fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); + fix->opnd = idesc->operands[index]; + fix->expr = *e; + fix->is_pcrel = 1; + ++CURR_SLOT.num_fixups; + return 1; + } + case IA64_OPND_TAG13: + case IA64_OPND_TAG13b: + switch (e->X_op) + { + case O_constant: + return 1; + + case O_symbol: + fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; + fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, 0); + fix->opnd = idesc->operands[index]; + fix->expr = *e; + fix->is_pcrel = 1; + ++CURR_SLOT.num_fixups; + return 1; + + default: + break; + } + break; + + default: + break; + } + return 0; +} + +static int +parse_operand (e) + expressionS *e; +{ + int sep = '\0'; + + memset (e, 0, sizeof (*e)); + e->X_op = O_absent; + SKIP_WHITESPACE (); + if (*input_line_pointer != '}') + expression (e); + sep = *input_line_pointer++; + + if (sep == '}') + { + if (!md.manual_bundling) + as_warn ("Found '}' when manual bundling is off"); + else + CURR_SLOT.manual_bundling_off = 1; + md.manual_bundling = 0; + sep = '\0'; + } + return sep; +} + +/* Returns the next entry in the opcode table that matches the one in + IDESC, and frees the entry in IDESC. If no matching entry is + found, NULL is returned instead. */ + +static struct ia64_opcode * +get_next_opcode (struct ia64_opcode *idesc) +{ + struct ia64_opcode *next = ia64_find_next_opcode (idesc); + ia64_free_opcode (idesc); + return next; +} + +/* Parse the operands for the opcode and find the opcode variant that + matches the specified operands, or NULL if no match is possible. */ +static struct ia64_opcode* +parse_operands (idesc) + struct ia64_opcode *idesc; +{ + int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0; + int sep = 0; + enum ia64_opnd expected_operand = IA64_OPND_NIL; + char mnemonic[129]; + char *first_arg = 0, *end, *saved_input_pointer; + unsigned int sof; + + assert (strlen (idesc->name) <= 128); + + strcpy (mnemonic, idesc->name); + if (idesc->operands[2] == IA64_OPND_SOF) + { + /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we + can't parse the first operand until we have parsed the + remaining operands of the "alloc" instruction. */ + SKIP_WHITESPACE (); + first_arg = input_line_pointer; + end = strchr (input_line_pointer, '='); + if (!end) + { + as_bad ("Expected separator `='"); + return 0; + } + input_line_pointer = end + 1; + ++i; + ++num_outputs; + } + + for (; i < NELEMS (CURR_SLOT.opnd); ++i) + { + sep = parse_operand (CURR_SLOT.opnd + i); + if (CURR_SLOT.opnd[i].X_op == O_absent) + break; + + ++num_operands; + + if (sep != '=' && sep != ',') + break; + + if (sep == '=') + { + if (num_outputs > 0) + as_bad ("Duplicate equal sign (=) in instruction"); + else + num_outputs = i + 1; + } + } + if (sep != '\0') + { + as_bad ("Illegal operand separator `%c'", sep); + return 0; + } + + if (idesc->operands[2] == IA64_OPND_SOF) + { + /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */ + know (strcmp (idesc->name, "alloc") == 0); + if (num_operands == 5 /* first_arg not included in this count! */ + && CURR_SLOT.opnd[2].X_op == O_constant + && CURR_SLOT.opnd[3].X_op == O_constant + && CURR_SLOT.opnd[4].X_op == O_constant + && CURR_SLOT.opnd[5].X_op == O_constant) + { + sof = set_regstack (CURR_SLOT.opnd[2].X_add_number, + CURR_SLOT.opnd[3].X_add_number, + CURR_SLOT.opnd[4].X_add_number, + CURR_SLOT.opnd[5].X_add_number); + + /* now we can parse the first arg: */ + saved_input_pointer = input_line_pointer; + input_line_pointer = first_arg; + sep = parse_operand (CURR_SLOT.opnd + 0); + if (sep != '=') + --num_outputs; /* force error */ + input_line_pointer = saved_input_pointer; + + CURR_SLOT.opnd[2].X_add_number = sof; + CURR_SLOT.opnd[3].X_add_number + = sof - CURR_SLOT.opnd[4].X_add_number; + CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5]; + } + } + + highest_unmatched_operand = 0; + expected_operand = idesc->operands[0]; + for (; idesc; idesc = get_next_opcode (idesc)) + { + if (num_outputs != idesc->num_outputs) + continue; /* mismatch in # of outputs */ + + CURR_SLOT.num_fixups = 0; + for (i = 0; i < num_operands && idesc->operands[i]; ++i) + if (!operand_match (idesc, i, CURR_SLOT.opnd + i)) + break; + + if (i != num_operands) + { + if (i > highest_unmatched_operand) + { + highest_unmatched_operand = i; + expected_operand = idesc->operands[i]; + } + continue; + } + + if (num_operands < NELEMS (idesc->operands) + && idesc->operands[num_operands]) + continue; /* mismatch in number of arguments */ + + break; + } + if (!idesc) + { + if (expected_operand) + as_bad ("Operand %u of `%s' should be %s", + highest_unmatched_operand + 1, mnemonic, + elf64_ia64_operands[expected_operand].desc); + else + as_bad ("Operand mismatch"); + return 0; + } + return idesc; +} + +static void +build_insn (slot, insnp) + struct slot *slot; + bfd_vma *insnp; +{ + const struct ia64_operand *odesc, *o2desc; + struct ia64_opcode *idesc = slot->idesc; + bfd_signed_vma insn, val; + const char *err; + int i; + + insn = idesc->opcode | slot->qp_regno; + + for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i) + { + if (idesc->operands[i] == IA64_OPND_IMMU64) + { + val = slot->opnd[i].X_add_number; + *insnp++ = (val >> 22) & 0x1ffffffffffLL; + insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27) + | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21) + | (((val >> 63) & 0x1) << 36)); + } + else if (idesc->operands[i] == IA64_OPND_IMMU62) + { + val = slot->opnd[i].X_add_number & 0x3fffffffffffffffULL; + if (val != slot->opnd[i].X_add_number) + as_warn (_("Value truncated to 62 bits")); + *insnp++ = (val >> 21) & 0x1ffffffffffLL; + insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36)); + } + else if (idesc->operands[i] == IA64_OPND_TGT64) + { + // FIXME -- need to implement the target address encoding properly + as_bad (_("long branch target encoding not implemented")); + *insnp++ = 0; + } + else if (slot->opnd[i].X_op == O_register + || slot->opnd[i].X_op == O_constant + || slot->opnd[i].X_op == O_index + || slot->opnd[i].X_op == O_big) + { + if (slot->opnd[i].X_op == O_big) + { + /* This must be the value 0x10000000000000000. */ + assert (idesc->operands[i] == IA64_OPND_IMM8M1U8); + val = 0; + } + else + val = slot->opnd[i].X_add_number; + + switch (idesc->operands[i]) + { + case IA64_OPND_AR3: val -= REG_AR; break; + case IA64_OPND_B1: case IA64_OPND_B2: val -= REG_BR; break; + case IA64_OPND_CR3: val -= REG_CR; break; + case IA64_OPND_F1: case IA64_OPND_F2: + case IA64_OPND_F3: case IA64_OPND_F4: val -= REG_FR; break; + case IA64_OPND_P1: case IA64_OPND_P2: val -= REG_P; break; + + case IA64_OPND_R1: case IA64_OPND_R2: + case IA64_OPND_R3: case IA64_OPND_R3_2: + case IA64_OPND_CPUID_R3: case IA64_OPND_DBR_R3: + case IA64_OPND_DTR_R3: case IA64_OPND_ITR_R3: + case IA64_OPND_IBR_R3: case IA64_OPND_MR3: + case IA64_OPND_MSR_R3: case IA64_OPND_PKR_R3: + case IA64_OPND_PMC_R3: case IA64_OPND_PMD_R3: + case IA64_OPND_RR_R3: + val -= REG_GR; + break; + + default: + break; + } + odesc = elf64_ia64_operands + idesc->operands[i]; + err = (*odesc->insert) (odesc, val, &insn); + if (err) + as_bad_where (slot->src_file, slot->src_line, + "Bad operand value: %s", err); + if (idesc->flags & IA64_OPCODE_PSEUDO) + { + if ((idesc->flags & IA64_OPCODE_F2_EQ_F3) + && odesc == elf64_ia64_operands + IA64_OPND_F3) + { + o2desc = elf64_ia64_operands + IA64_OPND_F2; + (*o2desc->insert) (o2desc, val, &insn); + + } + if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT) + && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a + || odesc == elf64_ia64_operands + IA64_OPND_POS6)) + { + o2desc = elf64_ia64_operands + IA64_OPND_LEN6; + (*o2desc->insert) (o2desc, 64 - val, &insn); + } + } + } + } + *insnp = insn; +} + +static void +emit_one_bundle () +{ + unsigned int manual_bundling_on = 0, manual_bundling_off = 0; + unsigned int manual_bundling = 0; + enum ia64_unit required_unit, insn_unit = 0; + enum ia64_insn_type type[3], insn_type; + unsigned int template, orig_template; + bfd_vma insn[3] = {-1, -1, -1}; + struct ia64_opcode *idesc; + int end_of_insn_group = 0, user_template = -1; + int n, i, j, first, curr; + bfd_vma t0 = 0, t1 = 0; + struct label_fix *lfix; + struct insn_fix *ifix; + char mnemonic[16]; + fixS *fix; + char *f; + + first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS; + know (first >= 0 & first < NUM_SLOTS); + n = MIN (3, md.num_slots_in_use); + + /* Determine template: user user_template if specified, best match + otherwise: */ + + if (md.slot[first].user_template >= 0) + user_template = template = md.slot[first].user_template; + else + { + /* auto select appropriate template */ + memset (type, 0, sizeof (type)); + curr = first; + for (i = 0; i < n; ++i) + { + type[i] = md.slot[curr].idesc->type; + curr = (curr + 1) % NUM_SLOTS; + } + template = best_template[type[0]][type[1]][type[2]]; + } + + /* initialize instructions with appropriate nops: */ + for (i = 0; i < 3; ++i) + insn[i] = nop[ia64_templ_desc[template].exec_unit[i]]; + + f = frag_more (16); + + /* now fill in slots with as many insns as possible: */ + curr = first; + idesc = md.slot[curr].idesc; + end_of_insn_group = 0; + for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i) + { + if (idesc->flags & IA64_OPCODE_SLOT2) + { + if (manual_bundling && i != 2) + as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, + "`%s' must be last in bundle", idesc->name); + else + i = 2; + } + if (idesc->flags & IA64_OPCODE_LAST) + { + int required_slot, required_template; + + /* If we need a stop bit after an M slot, our only choice is + template 5 (M;;MI). If we need a stop bit after a B + slot, our only choice is to place it at the end of the + bundle, because the only available templates are MIB, + MBB, BBB, MMB, and MFB. We don't handle anything other + than M and B slots because these are the only kind of + instructions that can have the IA64_OPCODE_LAST bit set. */ + required_template = template; + switch (idesc->type) + { + case IA64_TYPE_M: + required_slot = 0; + required_template = 5; + break; + + case IA64_TYPE_B: + required_slot = 2; + break; + + default: + as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, + "Internal error: don't know how to force %s to end" + "of instruction group", idesc->name); + required_slot = i; + break; + } + if (manual_bundling && i != required_slot) + as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, + "`%s' must be last in instruction group", + idesc->name); + if (required_slot < i) + /* Can't fit this instruction. */ + break; + + i = required_slot; + if (required_template != template) + { + /* If we switch the template, we need to reset the NOPs + after slot i. The slot-types of the instructions ahead + of i never change, so we don't need to worry about + changing NOPs in front of this slot. */ + for (j = i; j < 3; ++j) + insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]]; + } + template = required_template; + } + if (curr != first && md.slot[curr].label_fixups) + { + if (manual_bundling_on) + as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, + "Label must be first in a bundle"); + /* This insn must go into the first slot of a bundle. */ + break; + } + + manual_bundling_on = md.slot[curr].manual_bundling_on; + manual_bundling_off = md.slot[curr].manual_bundling_off; + + if (manual_bundling_on) + { + if (curr == first) + manual_bundling = 1; + else + break; /* need to start a new bundle */ + } + + if (end_of_insn_group && md.num_slots_in_use >= 1) + { + /* We need an instruction group boundary in the middle of a + bundle. See if we can switch to an other template with + an appropriate boundary. */ + + orig_template = template; + if (i == 1 && (user_template == 4 + || (user_template < 0 + && (ia64_templ_desc[template].exec_unit[0] + == IA64_UNIT_M)))) + { + template = 5; + end_of_insn_group = 0; + } + else if (i == 2 && (user_template == 0 + || (user_template < 0 + && (ia64_templ_desc[template].exec_unit[1] + == IA64_UNIT_I))) + /* This test makes sure we don't switch the template if + the next instruction is one that needs to be first in + an instruction group. Since all those instructions are + in the M group, there is no way such an instruction can + fit in this bundle even if we switch the template. The + reason we have to check for this is that otherwise we + may end up generating "MI;;I M.." which has the deadly + effect that the second M instruction is no longer the + first in the bundle! --davidm 99/12/16 */ + && (idesc->flags & IA64_OPCODE_FIRST) == 0) + { + template = 1; + end_of_insn_group = 0; + } + else if (curr != first) + /* can't fit this insn */ + break; + + if (template != orig_template) + /* if we switch the template, we need to reset the NOPs + after slot i. The slot-types of the instructions ahead + of i never change, so we don't need to worry about + changing NOPs in front of this slot. */ + for (j = i; j < 3; ++j) + insn[j] = nop[ia64_templ_desc[template].exec_unit[j]]; + } + required_unit = ia64_templ_desc[template].exec_unit[i]; + + /* resolve dynamic opcodes such as "break" and "nop": */ + if (idesc->type == IA64_TYPE_DYN) + { + if ((strcmp (idesc->name, "nop") == 0) + || (strcmp (idesc->name, "break") == 0)) + insn_unit = required_unit; + else if (strcmp (idesc->name, "chk.s") == 0) + { + insn_unit = IA64_UNIT_M; + if (required_unit == IA64_UNIT_I) + insn_unit = IA64_UNIT_I; + } + else + as_fatal ("emit_one_bundle: unexpected dynamic op"); + + sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]); + md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic); +#if 0 + know (!idesc->next); /* no resolved dynamic ops have collisions */ +#endif + } + else + { + insn_type = idesc->type; + insn_unit = IA64_UNIT_NIL; + switch (insn_type) + { + case IA64_TYPE_A: + if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M) + insn_unit = required_unit; + break; + case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break; + case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break; + case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break; + case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break; + case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break; + default: break; + } + } + + if (insn_unit != required_unit) + { + if (required_unit == IA64_UNIT_L + && insn_unit == IA64_UNIT_I + && !(idesc->flags & IA64_OPCODE_X_IN_MLX)) + { + /* we got ourselves an MLX template but the current + instruction isn't an X-unit, or an I-unit instruction + that can go into the X slot of an MLX template. Duh. */ + if (md.num_slots_in_use >= NUM_SLOTS) + { + as_bad_where (md.slot[curr].src_file, + md.slot[curr].src_line, + "`%s' can't go in X slot of " + "MLX template", idesc->name); + /* drop this insn so we don't livelock: */ + --md.num_slots_in_use; + } + break; + } + continue; /* try next slot */ + } + + if (debug_type == DEBUG_DWARF2) + { + bfd_vma addr; + + addr = frag_now->fr_address + frag_now_fix () - 16 + 1*i; + dwarf2_gen_line_info (addr, &md.slot[curr].debug_line); + } + + build_insn (md.slot + curr, insn + i); + + /* Set slot counts for unwind records. */ + while (md.slot[curr].unwind_record) + { + md.slot[curr].unwind_record->slot_number = (unsigned long) (f + i); + md.slot[curr].unwind_record = md.slot[curr].unwind_record->next; + } + if (required_unit == IA64_UNIT_L) + { + know (i == 1); + /* skip one slot for long/X-unit instructions */ + ++i; + } + --md.num_slots_in_use; + + /* now is a good time to fix up the labels for this insn: */ + for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next) + { + S_SET_VALUE (lfix->sym, frag_now_fix () - 16); + symbol_set_frag (lfix->sym, frag_now); + } + + for (j = 0; j < md.slot[curr].num_fixups; ++j) + { + ifix = md.slot[curr].fixup + j; + fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 4, + &ifix->expr, ifix->is_pcrel, ifix->code); + fix->tc_fix_data.opnd = ifix->opnd; + fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22); + fix->fx_file = md.slot[curr].src_file; + fix->fx_line = md.slot[curr].src_line; + } + + end_of_insn_group = md.slot[curr].end_of_insn_group; + + /* clear slot: */ + ia64_free_opcode (md.slot[curr].idesc); + memset (md.slot + curr, 0, sizeof (md.slot[curr])); + md.slot[curr].user_template = -1; + + if (manual_bundling_off) + { + manual_bundling = 0; + break; + } + curr = (curr + 1) % NUM_SLOTS; + idesc = md.slot[curr].idesc; + } + if (manual_bundling) + { + if (md.num_slots_in_use > 0) + as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, + "`%s' does not fit into %s template", + idesc->name, ia64_templ_desc[template].name); + else + as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, + "Missing '}' at end of file"); + } + know (md.num_slots_in_use < NUM_SLOTS); + + t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46); + t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); + + md_number_to_chars (f + 0, t0, 8); + md_number_to_chars (f + 8, t1, 8); +} + +int +md_parse_option (c, arg) + int c; + char *arg; +{ + /* Switches from the Intel assembler. */ + switch (c) + { + case 'M': + if (strcmp (arg, "ilp64") == 0 + || strcmp (arg, "lp64") == 0 + || strcmp (arg, "p64") == 0) + { + md.flags |= EF_IA_64_ABI64; + } + else if (strcmp (arg, "ilp32") == 0) + { + md.flags &= ~EF_IA_64_ABI64; + } + else if (strcmp (arg, "le") == 0) + { + md.flags &= ~EF_IA_64_BE; + } + else if (strcmp (arg, "be") == 0) + { + md.flags |= EF_IA_64_BE; + } + else + return 0; + break; + + case 'N': + if (strcmp (arg, "so") == 0) + { + /* Suppress signon message. */ + } + else if (strcmp (arg, "pi") == 0) + { + /* Reject privileged instructions. FIXME */ + } + else if (strcmp (arg, "us") == 0) + { + /* Allow union of signed and unsigned range. FIXME */ + } + else if (strcmp (arg, "close_fcalls") == 0) + { + /* Do not resolve global function calls. */ + } + else + return 0; + break; + + case 'C': + /* temp[="prefix"] Insert temporary labels into the object file + symbol table prefixed by "prefix". + Default prefix is ":temp:". + */ + break; + + case 'a': + /* ??? Conflicts with gas' listing option. */ + /* indirect=<tgt> Assume unannotated indirect branches behavior + according to <tgt> -- + exit: branch out from the current context (default) + labels: all labels in context may be branch targets + */ + break; + + case 'x': + /* -X conflicts with an ignored option, use -x instead */ + md.detect_dv = 1; + if (!arg || strcmp (arg, "explicit") == 0) + { + /* set default mode to explicit */ + md.default_explicit_mode = 1; + break; + } + else if (strcmp (arg, "auto") == 0) + { + md.default_explicit_mode = 0; + } + else if (strcmp (arg, "debug") == 0) + { + md.debug_dv = 1; + } + else if (strcmp (arg, "debugx") == 0) + { + md.default_explicit_mode = 1; + md.debug_dv = 1; + } + else + { + as_bad (_("Unrecognized option '-x%s'"), arg); + } + break; + + case 'S': + /* nops Print nops statistics. */ + break; + + default: + return 0; + } + + return 1; +} + +void +md_show_usage (stream) + FILE *stream; +{ + fputs(_("\ +IA-64 options:\n\ + -Milp32|-Milp64|-Mlp64|-Mp64 select data model (default -Mlp64)\n\ + -Mle | -Mbe select little- or big-endian byte order (default -Mle)\n\ + -x | -xexplicit turn on dependency violation checking (default)\n\ + -xauto automagically remove dependency violations\n\ + -xdebug debug dependency violation checker\n"), + stream); +} + +static inline int +match (int templ, int type, int slot) +{ + enum ia64_unit unit; + int result; + + unit = ia64_templ_desc[templ].exec_unit[slot]; + switch (type) + { + case IA64_TYPE_DYN: result = 1; break; /* for nop and break */ + case IA64_TYPE_A: + result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M); + break; + case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break; + case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break; + case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break; + case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break; + case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break; + default: result = 0; break; + } + return result; +} + +/* This function is called once, at assembler startup time. It sets + up all the tables, etc. that the MD part of the assembler will need + that can be determined before arguments are parsed. */ +void +md_begin () +{ + int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum; + const char *err; + char name[8]; + + md.auto_align = 1; + md.explicit_mode = md.default_explicit_mode; + + bfd_set_section_alignment (stdoutput, text_section, 4); + + target_big_endian = 0; + pseudo_func[FUNC_FPTR_RELATIVE].u.sym = + symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE, + &zero_address_frag); + + pseudo_func[FUNC_GP_RELATIVE].u.sym = + symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE, + &zero_address_frag); + + pseudo_func[FUNC_LT_RELATIVE].u.sym = + symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE, + &zero_address_frag); + + pseudo_func[FUNC_PLT_RELATIVE].u.sym = + symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE, + &zero_address_frag); + + pseudo_func[FUNC_SEC_RELATIVE].u.sym = + symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE, + &zero_address_frag); + + pseudo_func[FUNC_SEG_RELATIVE].u.sym = + symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE, + &zero_address_frag); + + pseudo_func[FUNC_LTV_RELATIVE].u.sym = + symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE, + &zero_address_frag); + + pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym = + symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE, + &zero_address_frag); + + /* compute the table of best templates: */ + for (i = 0; i < IA64_NUM_TYPES; ++i) + for (j = 0; j < IA64_NUM_TYPES; ++j) + for (k = 0; k < IA64_NUM_TYPES; ++k) + { + best = 0; + for (t = 0; t < NELEMS (ia64_templ_desc); ++t) + { + goodness = 0; + if (match (t, i, 0)) + { + if (match (t, j, 1)) + { + if (match (t, k, 2)) + goodness = 3; + else + goodness = 2; + } + else if (match (t, j, 2)) + goodness = 2; + else + goodness = 1; + } + else if (match (t, i, 1)) + { + if (match (t, j, 2)) + goodness = 2; + else + goodness = 1; + } + else if (match (t, i, 2)) + goodness = 1; + + if (goodness > best) + { + best = goodness; + best_template[i][j][k] = t; + } + } + } + + for (i = 0; i < NUM_SLOTS; ++i) + md.slot[i].user_template = -1; + + md.pseudo_hash = hash_new (); + for (i = 0; i < NELEMS (pseudo_opcode); ++i) + { + err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name, + (void *) (pseudo_opcode + i)); + if (err) + as_fatal ("ia64.md_begin: can't hash `%s': %s", + pseudo_opcode[i].name, err); + } + + md.reg_hash = hash_new (); + md.dynreg_hash = hash_new (); + md.const_hash = hash_new (); + md.entry_hash = hash_new (); + + /* general registers: */ + + total = 128; + for (i = 0; i < total; ++i) + { + sprintf (name, "r%d", i - REG_GR); + md.regsym[i] = declare_register (name, i); + } + + /* floating point registers: */ + total += 128; + for (; i < total; ++i) + { + sprintf (name, "f%d", i - REG_FR); + md.regsym[i] = declare_register (name, i); + } + + /* application registers: */ + total += 128; + ar_base = i; + for (; i < total; ++i) + { + sprintf (name, "ar%d", i - REG_AR); + md.regsym[i] = declare_register (name, i); + } + + /* control registers: */ + total += 128; + cr_base = i; + for (; i < total; ++i) + { + sprintf (name, "cr%d", i - REG_CR); + md.regsym[i] = declare_register (name, i); + } + + /* predicate registers: */ + total += 64; + for (; i < total; ++i) + { + sprintf (name, "p%d", i - REG_P); + md.regsym[i] = declare_register (name, i); + } + + /* branch registers: */ + total += 8; + for (; i < total; ++i) + { + sprintf (name, "b%d", i - REG_BR); + md.regsym[i] = declare_register (name, i); + } + + md.regsym[REG_IP] = declare_register ("ip", REG_IP); + md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM); + md.regsym[REG_PR] = declare_register ("pr", REG_PR); + md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT); + md.regsym[REG_PSR] = declare_register ("psr", REG_PSR); + md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L); + md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM); + + for (i = 0; i < NELEMS (indirect_reg); ++i) + { + regnum = indirect_reg[i].regnum; + md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum); + } + + /* define synonyms for application registers: */ + for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i) + md.regsym[i] = declare_register (ar[i - REG_AR].name, + REG_AR + ar[i - REG_AR].regnum); + + /* define synonyms for control registers: */ + for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i) + md.regsym[i] = declare_register (cr[i - REG_CR].name, + REG_CR + cr[i - REG_CR].regnum); + + declare_register ("gp", REG_GR + 1); + declare_register ("sp", REG_GR + 12); + declare_register ("rp", REG_BR + 0); + + declare_register_set ("ret", 4, REG_GR + 8); + declare_register_set ("farg", 8, REG_FR + 8); + declare_register_set ("fret", 8, REG_FR + 8); + + for (i = 0; i < NELEMS (const_bits); ++i) + { + err = hash_insert (md.const_hash, const_bits[i].name, + (PTR) (const_bits + i)); + if (err) + as_fatal ("Inserting \"%s\" into constant hash table failed: %s", + name, err); + } + + /* Default to 64-bit mode. */ + md.flags = EF_IA_64_ABI64; + + md.mem_offset.hint = 0; + md.path = 0; + md.maxpaths = 0; + md.entry_labels = NULL; +} + +void +ia64_end_of_source () +{ + /* terminate insn group upon reaching end of file: */ + insn_group_break (1, 0, 0); + + /* emits slots we haven't written yet: */ + ia64_flush_insns (); + + bfd_set_private_flags (stdoutput, md.flags); + + if (debug_type == DEBUG_DWARF2) + dwarf2_finish (); + + md.mem_offset.hint = 0; +} + +void +ia64_start_line () +{ + md.qp.X_op = O_absent; + + if (ignore_input ()) + return; + + if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';') + { + if (md.detect_dv && !md.explicit_mode) + as_warn (_("Explicit stops are ignored in auto mode")); + else + insn_group_break (1, 0, 0); + } +} + +int +ia64_unrecognized_line (ch) + int ch; +{ + switch (ch) + { + case '(': + expression (&md.qp); + if (*input_line_pointer++ != ')') + { + as_bad ("Expected ')'"); + return 0; + } + if (md.qp.X_op != O_register) + { + as_bad ("Qualifying predicate expected"); + return 0; + } + if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64) + { + as_bad ("Predicate register expected"); + return 0; + } + return 1; + + case '{': + if (md.manual_bundling) + as_warn ("Found '{' when manual bundling is already turned on"); + else + CURR_SLOT.manual_bundling_on = 1; + md.manual_bundling = 1; + + /* bundling is only acceptable in explicit mode + or when in default automatic mode */ + if (md.detect_dv && !md.explicit_mode) + { + if (!md.mode_explicitly_set + && !md.default_explicit_mode) + dot_dv_mode ('E'); + else + as_warn (_("Found '{' after explicit switch to automatic mode")); + } + return 1; + + case '}': + if (!md.manual_bundling) + as_warn ("Found '}' when manual bundling is off"); + else + PREV_SLOT.manual_bundling_off = 1; + md.manual_bundling = 0; + + /* switch back to automatic mode, if applicable */ + if (md.detect_dv + && md.explicit_mode + && !md.mode_explicitly_set + && !md.default_explicit_mode) + dot_dv_mode ('A'); + + /* Allow '{' to follow on the same line. We also allow ";;", but that + happens automatically because ';' is an end of line marker. */ + SKIP_WHITESPACE (); + if (input_line_pointer[0] == '{') + { + input_line_pointer++; + return ia64_unrecognized_line ('{'); + } + + demand_empty_rest_of_line (); + return 1; + + default: + break; + } + return 0; /* not a valid line */ +} + +void +ia64_frob_label (sym) + struct symbol *sym; +{ + struct label_fix *fix; + + if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) + { + md.last_text_seg = now_seg; + fix = obstack_alloc (¬es, sizeof (*fix)); + fix->sym = sym; + fix->next = CURR_SLOT.label_fixups; + CURR_SLOT.label_fixups = fix; + + /* keep track of how many code entry points we've seen */ + if (md.path == md.maxpaths) + { + md.maxpaths += 20; + md.entry_labels = (const char **) + xrealloc ((void *)md.entry_labels, md.maxpaths * sizeof (char *)); + } + md.entry_labels[md.path++] = S_GET_NAME (sym); + } +} + +void +ia64_flush_pending_output () +{ + if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) + { + /* ??? This causes many unnecessary stop bits to be emitted. + Unfortunately, it isn't clear if it is safe to remove this. */ + insn_group_break (1, 0, 0); + ia64_flush_insns (); + } +} + +/* Do ia64-specific expression optimization. All that's done here is + to transform index expressions that are either due to the indexing + of rotating registers or due to the indexing of indirect register + sets. */ +int +ia64_optimize_expr (l, op, r) + expressionS *l; + operatorT op; + expressionS *r; +{ + unsigned num_regs; + + if (op == O_index) + { + if (l->X_op == O_register && r->X_op == O_constant) + { + num_regs = (l->X_add_number >> 16); + if ((unsigned) r->X_add_number >= num_regs) + { + if (!num_regs) + as_bad ("No current frame"); + else + as_bad ("Index out of range 0..%u", num_regs - 1); + r->X_add_number = 0; + } + l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number; + return 1; + } + else if (l->X_op == O_register && r->X_op == O_register) + { + if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR + || l->X_add_number == IND_MEM) + { + as_bad ("Indirect register set name expected"); + l->X_add_number = IND_CPUID; + } + l->X_op = O_index; + l->X_op_symbol = md.regsym[l->X_add_number]; + l->X_add_number = r->X_add_number; + return 1; + } + } + return 0; +} + +int +ia64_parse_name (name, e) + char *name; + expressionS *e; +{ + struct const_desc *cdesc; + struct dynreg *dr = 0; + unsigned int regnum; + struct symbol *sym; + char *end; + + /* first see if NAME is a known register name: */ + sym = hash_find (md.reg_hash, name); + if (sym) + { + e->X_op = O_register; + e->X_add_number = S_GET_VALUE (sym); + return 1; + } + + cdesc = hash_find (md.const_hash, name); + if (cdesc) + { + e->X_op = O_constant; + e->X_add_number = cdesc->value; + return 1; + } + + /* check for inN, locN, or outN: */ + switch (name[0]) + { + case 'i': + if (name[1] == 'n' && isdigit (name[2])) + { + dr = &md.in; + name += 2; + } + break; + + case 'l': + if (name[1] == 'o' && name[2] == 'c' && isdigit (name[3])) + { + dr = &md.loc; + name += 3; + } + break; + + case 'o': + if (name[1] == 'u' && name[2] == 't' && isdigit (name[3])) + { + dr = &md.out; + name += 3; + } + break; + + default: + break; + } + + if (dr) + { + /* the name is inN, locN, or outN; parse the register number: */ + regnum = strtoul (name, &end, 10); + if (end > name && *end == '\0') + { + if ((unsigned) regnum >= dr->num_regs) + { + if (!dr->num_regs) + as_bad ("No current frame"); + else + as_bad ("Register number out of range 0..%u", dr->num_regs-1); + regnum = 0; + } + e->X_op = O_register; + e->X_add_number = dr->base + regnum; + return 1; + } + } + + if ((dr = hash_find (md.dynreg_hash, name))) + { + /* We've got ourselves the name of a rotating register set. + Store the base register number in the low 16 bits of + X_add_number and the size of the register set in the top 16 + bits. */ + e->X_op = O_register; + e->X_add_number = dr->base | (dr->num_regs << 16); + return 1; + } + return 0; +} + +/* Remove the '#' suffix that indicates a symbol as opposed to a register. */ + +char * +ia64_canonicalize_symbol_name (name) + char *name; +{ + size_t len = strlen(name); + if (len > 1 && name[len-1] == '#') + name[len-1] = '\0'; + return name; +} + +static int +is_conditional_branch (idesc) + struct ia64_opcode *idesc; +{ + return (strncmp (idesc->name, "br", 2) == 0 + && (strcmp (idesc->name, "br") == 0 + || strncmp (idesc->name, "br.cond", 7) == 0 + || strncmp (idesc->name, "br.call", 7) == 0 + || strncmp (idesc->name, "br.ret", 6) == 0 + || strcmp (idesc->name, "brl") == 0 + || strncmp (idesc->name, "brl.cond", 7) == 0 + || strncmp (idesc->name, "brl.call", 7) == 0 + || strncmp (idesc->name, "brl.ret", 6) == 0)); +} + +/* Return whether the given opcode is a taken branch. If there's any doubt, + returns zero */ +static int +is_taken_branch (idesc) + struct ia64_opcode *idesc; +{ + return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0) + || strncmp (idesc->name, "br.ia", 5) == 0); +} + +/* Return whether the given opcode is an interruption or rfi. If there's any + doubt, returns zero */ +static int +is_interruption_or_rfi (idesc) + struct ia64_opcode *idesc; +{ + if (strcmp (idesc->name, "rfi") == 0) + return 1; + return 0; +} + +/* Returns the index of the given dependency in the opcode's list of chks, or + -1 if there is no dependency. */ +static int +depends_on (depind, idesc) + int depind; + struct ia64_opcode *idesc; +{ + int i; + const struct ia64_opcode_dependency *dep = idesc->dependencies; + for (i = 0;i < dep->nchks; i++) + { + if (depind == DEP(dep->chks[i])) + return i; + } + return -1; +} + +/* Determine a set of specific resources used for a particular resource + class. Returns the number of specific resources identified For those + cases which are not determinable statically, the resource returned is + marked nonspecific. + + Meanings of value in 'NOTE': + 1) only read/write when the register number is explicitly encoded in the + insn. + 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only + accesses CFM when qualifying predicate is in the rotating region. + 3) general register value is used to specify an indirect register; not + determinable statically. + 4) only read the given resource when bits 7:0 of the indirect index + register value does not match the register number of the resource; not + determinable statically. + 5) all rules are implementation specific. + 6) only when both the index specified by the reader and the index specified + by the writer have the same value in bits 63:61; not determinable + statically. + 7) only access the specified resource when the corresponding mask bit is + set + 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is + only read when these insns reference FR2-31 + 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only + written when these insns write FR32-127 + 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the + instruction + 11) The target predicates are written independently of PR[qp], but source + registers are only read if PR[qp] is true. Since the state of PR[qp] + cannot statically be determined, all source registers are marked used. + 12) This insn only reads the specified predicate register when that + register is the PR[qp]. + 13) This reference to ld-c only applies to teh GR whose value is loaded + with data returned from memory, not the post-incremented address register. + 14) The RSE resource includes the implementation-specific RSE internal + state resources. At least one (and possibly more) of these resources are + read by each instruction listed in IC:rse-readers. At least one (and + possibly more) of these resources are written by each insn listed in + IC:rse-writers. + 15+16) Represents reserved instructions, which the assembler does not + generate. + + Memory resources (i.e. locations in memory) are *not* marked or tracked by + this code; there are no dependency violations based on memory access. + +*/ + +#define MAX_SPECS 256 +#define DV_CHK 1 +#define DV_REG 0 + +static int +specify_resource (dep, idesc, type, specs, note, path) + const struct ia64_dependency *dep; + struct ia64_opcode *idesc; + int type; /* is this a DV chk or a DV reg? */ + struct rsrc specs[MAX_SPECS]; /* returned specific resources */ + int note; /* resource note for this insn's usage */ + int path; /* which execution path to examine */ +{ + int count = 0; + int i; + int rsrc_write = 0; + struct rsrc tmpl; + + if (dep->mode == IA64_DV_WAW + || (dep->mode == IA64_DV_RAW && type == DV_REG) + || (dep->mode == IA64_DV_WAR && type == DV_CHK)) + rsrc_write = 1; + + /* template for any resources we identify */ + tmpl.dependency = dep; + tmpl.note = note; + tmpl.insn_srlz = tmpl.data_srlz = 0; + tmpl.qp_regno = CURR_SLOT.qp_regno; + tmpl.link_to_qp_branch = 1; + tmpl.mem_offset.hint = 0; + tmpl.specific = 1; + tmpl.index = 0; + +#define UNHANDLED \ +as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \ +dep->name, idesc->name, (rsrc_write?"write":"read"), note) +#define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path) + + /* we don't need to track these */ + if (dep->semantics == IA64_DVS_NONE) + return 0; + + switch (dep->specifier) + { + case IA64_RS_AR_K: + if (note == 1) + { + if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) + { + int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; + if (regno >= 0 && regno <= 7) + { + specs[count] = tmpl; + specs[count++].index = regno; + } + } + } + else if (note == 0) + { + for(i=0;i < 8;i++) + { + specs[count] = tmpl; + specs[count++].index = i; + } + } + else + { + UNHANDLED; + } + break; + + case IA64_RS_AR_UNAT: + /* This is a mov =AR or mov AR= instruction. */ + if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) + { + int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; + if (regno == AR_UNAT) + { + specs[count++] = tmpl; + } + } + else + { + /* This is a spill/fill, or other instruction that modifies the + unat register. */ + + /* Unless we can determine the specific bits used, mark the whole + thing; bits 8:3 of the memory address indicate the bit used in + UNAT. The .mem.offset hint may be used to eliminate a small + subset of conflicts. */ + specs[count] = tmpl; + if (md.mem_offset.hint) + { + if (md.debug_dv) + fprintf (stderr, " Using hint for spill/fill\n"); + /* the index isn't actually used, just set it to something + approximating the bit index */ + specs[count].index = (md.mem_offset.offset >> 3) & 0x3F; + specs[count].mem_offset.hint = 1; + specs[count].mem_offset.offset = md.mem_offset.offset; + specs[count++].mem_offset.base = md.mem_offset.base; + } + else + { + specs[count++].specific = 0; + } + } + break; + + case IA64_RS_AR: + if (note == 1) + { + if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) + { + int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; + if ((regno >= 8 && regno <= 15) + || (regno >= 20 && regno <= 23) + || (regno >= 31 && regno <= 39) + || (regno >= 41 && regno <= 47) + || (regno >= 67 && regno <= 111)) + { + specs[count] = tmpl; + specs[count++].index = regno; + } + } + } + else + { + UNHANDLED; + } + break; + + case IA64_RS_ARb: + if (note == 1) + { + if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) + { + int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; + if ((regno >= 48 && regno <= 63) + || (regno >= 112 && regno <= 127)) + { + specs[count] = tmpl; + specs[count++].index = regno; + } + } + } + else if (note == 0) + { + for (i=48;i < 64;i++) + { + specs[count] = tmpl; + specs[count++].index = i; + } + for (i=112;i < 128;i++) + { + specs[count] = tmpl; + specs[count++].index = i; + } + } + else + { + UNHANDLED; + } + break; + + case IA64_RS_BR: + if (note != 1) + { + UNHANDLED; + } + else + { + if (rsrc_write) + { + for (i=0;i < idesc->num_outputs;i++) + if (idesc->operands[i] == IA64_OPND_B1 + || idesc->operands[i] == IA64_OPND_B2) + { + specs[count] = tmpl; + specs[count++].index = + CURR_SLOT.opnd[i].X_add_number - REG_BR; + } + } + else + { + for (i = idesc->num_outputs;i < NELEMS(idesc->operands);i++) + if (idesc->operands[i] == IA64_OPND_B1 + || idesc->operands[i] == IA64_OPND_B2) + { + specs[count] = tmpl; + specs[count++].index = + CURR_SLOT.opnd[i].X_add_number - REG_BR; + } + } + } + break; + + case IA64_RS_CPUID: /* four or more registers */ + if (note == 3) + { + if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3) + { + int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; + if (regno >= 0 && regno < NELEMS(gr_values) + && KNOWN(regno)) + { + specs[count] = tmpl; + specs[count++].index = gr_values[regno].value & 0xFF; + } + else + { + specs[count] = tmpl; + specs[count++].specific = 0; + } + } + } + else + { + UNHANDLED; + } + break; + + case IA64_RS_DBR: /* four or more registers */ + if (note == 3) + { + if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3) + { + int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; + if (regno >= 0 && regno < NELEMS(gr_values) + && KNOWN(regno)) + { + specs[count] = tmpl; + specs[count++].index = gr_values[regno].value & 0xFF; + } + else + { + specs[count] = tmpl; + specs[count++].specific = 0; + } + } + } + else if (note == 0 && !rsrc_write) + { + specs[count] = tmpl; + specs[count++].specific = 0; + } + else + { + UNHANDLED; + } + break; + + case IA64_RS_IBR: /* four or more registers */ + if (note == 3) + { + if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3) + { + int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; + if (regno >= 0 && regno < NELEMS(gr_values) + && KNOWN(regno)) + { + specs[count] = tmpl; + specs[count++].index = gr_values[regno].value & 0xFF; + } + else + { + specs[count] = tmpl; + specs[count++].specific = 0; + } + } + } + else + { + UNHANDLED; + } + break; + + case IA64_RS_MSR: + if (note == 5) + { + /* These are implementation specific. Force all references to + conflict with all other references. */ + specs[count] = tmpl; + specs[count++].specific = 0; + } + else + { + UNHANDLED; + } + break; + + case IA64_RS_PKR: /* 16 or more registers */ + if (note == 3 || note == 4) + { + if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3) + { + int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; + if (regno >= 0 && regno < NELEMS(gr_values) + && KNOWN(regno)) + { + if (note == 3) + { + specs[count] = tmpl; + specs[count++].index = gr_values[regno].value & 0xFF; + } + else for (i=0;i < NELEMS(gr_values);i++) + { + /* uses all registers *except* the one in R3 */ + if (i != (gr_values[regno].value & 0xFF)) + { + specs[count] = tmpl; + specs[count++].index = i; + } + } + } + else + { + specs[count] = tmpl; + specs[count++].specific = 0; + } + } + } + else if (note == 0) + { + /* probe et al. */ + specs[count] = tmpl; + specs[count++].specific = 0; + } + break; + + case IA64_RS_PMC: /* four or more registers */ + if (note == 3) + { + if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3 + || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3)) + + { + int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write) + ? 1 : !rsrc_write); + int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR; + if (regno >= 0 && regno < NELEMS(gr_values) + && KNOWN(regno)) + { + specs[count] = tmpl; + specs[count++].index = gr_values[regno].value & 0xFF; + } + else + { + specs[count] = tmpl; + specs[count++].specific = 0; + } + } + } + else + { + UNHANDLED; + } + break; + + case IA64_RS_PMD: /* four or more registers */ + if (note == 3) + { + if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3) + { + int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; + if (regno >= 0 && regno < NELEMS(gr_values) + && KNOWN(regno)) + { + specs[count] = tmpl; + specs[count++].index = gr_values[regno].value & 0xFF; + } + else + { + specs[count] = tmpl; + specs[count++].specific = 0; + } + } + } + else + { + UNHANDLED; + } + break; + + case IA64_RS_RR: /* eight registers */ + if (note == 6) + { + if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3) + { + int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; + if (regno >= 0 && regno < NELEMS(gr_values) + && KNOWN(regno)) + { + specs[count] = tmpl; + specs[count++].index = (gr_values[regno].value >> 61) & 0x7; + } + else + { + specs[count] = tmpl; + specs[count++].specific = 0; + } + } + } + else if (note == 0 && !rsrc_write) + { + specs[count] = tmpl; + specs[count++].specific = 0; + } + else + { + UNHANDLED; + } + break; + + case IA64_RS_CR_IRR: + if (note == 0) + { + /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */ + int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR; + if (rsrc_write + && idesc->operands[1] == IA64_OPND_CR3 + && regno == CR_IVR) + { + for(i=0;i < 4;i++) + { + specs[count] = tmpl; + specs[count++].index = CR_IRR0 + i; + } + } + } + else if (note == 1) + { + int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; + if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 + && regno >= CR_IRR0 + && regno <= CR_IRR3) + { + specs[count] = tmpl; + specs[count++].index = regno; + } + } + else + { + UNHANDLED; + } + break; + + case IA64_RS_CR_LRR: + if (note != 1) + { + UNHANDLED; + } + else + { + int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; + if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 + && (regno == CR_LRR0 || regno == CR_LRR1)) + { + specs[count] = tmpl; + specs[count++].index = regno; + } + } + break; + + case IA64_RS_CR: + if (note == 1) + { + if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) + { + specs[count] = tmpl; + specs[count++].index = + CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; + } + } + else + { + UNHANDLED; + } + break; + + case IA64_RS_FR: + case IA64_RS_FRb: + if (note != 1) + { + UNHANDLED; + } + else if (rsrc_write) + { + if (dep->specifier == IA64_RS_FRb + && idesc->operands[0] == IA64_OPND_F1) + { + specs[count] = tmpl; + specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR; + } + } + else + { + for (i=idesc->num_outputs;i < NELEMS(idesc->operands);i++) + { + if (idesc->operands[i] == IA64_OPND_F2 + || idesc->operands[i] == IA64_OPND_F3 + || idesc->operands[i] == IA64_OPND_F4) + { + specs[count] = tmpl; + specs[count++].index = + CURR_SLOT.opnd[i].X_add_number - REG_FR; + } + } + } + break; + + case IA64_RS_GR: + if (note == 13) + { + /* This reference applies only to the GR whose value is loaded with + data returned from memory */ + specs[count] = tmpl; + specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR; + } + else if (note == 1) + { + if (rsrc_write) + { + for (i=0;i < idesc->num_outputs;i++) + { + if (idesc->operands[i] == IA64_OPND_R1 + || idesc->operands[i] == IA64_OPND_R2 + || idesc->operands[i] == IA64_OPND_R3) + { + specs[count] = tmpl; + specs[count++].index = + CURR_SLOT.opnd[i].X_add_number - REG_GR; + } + } + } + else + { + /* Look for anything that reads a GR */ + for (i=0;i < NELEMS(idesc->operands);i++) + { + if (idesc->operands[i] == IA64_OPND_MR3 + || idesc->operands[i] == IA64_OPND_CPUID_R3 + || idesc->operands[i] == IA64_OPND_DBR_R3 + || idesc->operands[i] == IA64_OPND_IBR_R3 + || idesc->operands[i] == IA64_OPND_MSR_R3 + || idesc->operands[i] == IA64_OPND_PKR_R3 + || idesc->operands[i] == IA64_OPND_PMC_R3 + || idesc->operands[i] == IA64_OPND_PMD_R3 + || idesc->operands[i] == IA64_OPND_RR_R3 + || ((i >= idesc->num_outputs) + && (idesc->operands[i] == IA64_OPND_R1 + || idesc->operands[i] == IA64_OPND_R2 + || idesc->operands[i] == IA64_OPND_R3))) + { + specs[count] = tmpl; + specs[count++].index = + CURR_SLOT.opnd[i].X_add_number - REG_GR; + } + } + } + } + else + { + UNHANDLED; + } + break; + + case IA64_RS_PR: + if (note == 0) + { + if (idesc->operands[0] == IA64_OPND_PR_ROT) + { + for (i=16;i < 63;i++) + { + specs[count] = tmpl; + specs[count++].index = i; + } + } + else + { + for (i=1;i < 63;i++) + { + specs[count] = tmpl; + specs[count++].index = i; + } + } + } + else if (note == 7) + { + valueT mask = 0; + /* mark only those registers indicated by the mask */ + if (rsrc_write + && idesc->operands[0] == IA64_OPND_PR) + { + mask = CURR_SLOT.opnd[2].X_add_number; + if (mask & ((valueT)1<<16)) + mask |= ~(valueT)0xffff; + for (i=1;i < 63;i++) + { + if (mask & ((valueT)1<<i)) + { + specs[count] = tmpl; + specs[count++].index = i; + } + } + } + else if (rsrc_write + && idesc->operands[0] == IA64_OPND_PR_ROT) + { + for (i=16;i < 63;i++) + { + specs[count] = tmpl; + specs[count++].index = i; + } + } + else + { + UNHANDLED; + } + } + else if (note == 11) /* note 11 implies note 1 as well */ + { + if (rsrc_write) + { + for (i=0;i < idesc->num_outputs;i++) + { + if (idesc->operands[i] == IA64_OPND_P1 + || idesc->operands[i] == IA64_OPND_P2) + { + int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; + if (regno != 0) + { + specs[count] = tmpl; + specs[count++].index = regno; + } + } + } + } + else + { + UNHANDLED; + } + } + else if (note == 12) + { + if (CURR_SLOT.qp_regno != 0) + { + specs[count] = tmpl; + specs[count++].index = CURR_SLOT.qp_regno; + } + } + else if (note == 1) + { + if (rsrc_write) + { + int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; + int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; + if ((idesc->operands[0] == IA64_OPND_P1 + || idesc->operands[0] == IA64_OPND_P2) + && p1 != 0 && p1 != 63) + { + specs[count] = tmpl; + specs[count++].index = p1; + } + if ((idesc->operands[1] == IA64_OPND_P1 + || idesc->operands[1] == IA64_OPND_P2) + && p2 != 0 && p2 != 63) + { + specs[count] = tmpl; + specs[count++].index = p2; + } + } + else + { + if (CURR_SLOT.qp_regno != 0) + { + specs[count] = tmpl; + specs[count++].index = CURR_SLOT.qp_regno; + } + if (idesc->operands[1] == IA64_OPND_PR) + { + for (i=1;i < 63;i++) + { + specs[count] = tmpl; + specs[count++].index = i; + } + } + } + } + else + { + UNHANDLED; + } + break; + + case IA64_RS_PSR: + /* Verify that the instruction is using the PSR bit indicated in + dep->regindex */ + if (note == 0) + { + if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM) + { + if (dep->regindex < 6) + { + specs[count++] = tmpl; + } + } + else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR) + { + if (dep->regindex < 32 + || dep->regindex == 35 + || dep->regindex == 36 + || (!rsrc_write && dep->regindex == PSR_CPL)) + { + specs[count++] = tmpl; + } + } + else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L) + { + if (dep->regindex < 32 + || dep->regindex == 35 + || dep->regindex == 36 + || (rsrc_write && dep->regindex == PSR_CPL)) + { + specs[count++] = tmpl; + } + } + else + { + /* Several PSR bits have very specific dependencies. */ + switch (dep->regindex) + { + default: + specs[count++] = tmpl; + break; + case PSR_IC: + if (rsrc_write) + { + specs[count++] = tmpl; + } + else + { + /* Only certain CR accesses use PSR.ic */ + if (idesc->operands[0] == IA64_OPND_CR3 + || idesc->operands[1] == IA64_OPND_CR3) + { + int index = + ((idesc->operands[0] == IA64_OPND_CR3) + ? 0 : 1); + int regno = + CURR_SLOT.opnd[index].X_add_number - REG_CR; + + switch (regno) + { + default: + break; + case CR_ITIR: + case CR_IFS: + case CR_IIM: + case CR_IIP: + case CR_IPSR: + case CR_ISR: + case CR_IFA: + case CR_IHA: + case CR_IIPA: + specs[count++] = tmpl; + break; + } + } + } + break; + case PSR_CPL: + if (rsrc_write) + { + specs[count++] = tmpl; + } + else + { + /* Only some AR accesses use cpl */ + if (idesc->operands[0] == IA64_OPND_AR3 + || idesc->operands[1] == IA64_OPND_AR3) + { + int index = + ((idesc->operands[0] == IA64_OPND_AR3) + ? 0 : 1); + int regno = + CURR_SLOT.opnd[index].X_add_number - REG_AR; + + if (regno == AR_ITC + || (index == 0 + && (regno == AR_ITC + || regno == AR_RSC + || (regno >= AR_K0 + && regno <= AR_K7)))) + { + specs[count++] = tmpl; + } + } + else + { + specs[count++] = tmpl; + } + break; + } + } + } + } + else if (note == 7) + { + valueT mask = 0; + if (idesc->operands[0] == IA64_OPND_IMMU24) + { + mask = CURR_SLOT.opnd[0].X_add_number; + } + else + { + UNHANDLED; + } + if (mask & ((valueT)1<<dep->regindex)) + { + specs[count++] = tmpl; + } + } + else if (note == 8) + { + int min = dep->regindex == PSR_DFL ? 2 : 32; + int max = dep->regindex == PSR_DFL ? 31 : 127; + /* dfh is read on FR32-127; dfl is read on FR2-31 */ + for (i=0;i < NELEMS(idesc->operands);i++) + { + if (idesc->operands[i] == IA64_OPND_F1 + || idesc->operands[i] == IA64_OPND_F2 + || idesc->operands[i] == IA64_OPND_F3 + || idesc->operands[i] == IA64_OPND_F4) + { + int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; + if (reg >= min && reg <= max) + { + specs[count++] = tmpl; + } + } + } + } + else if (note == 9) + { + int min = dep->regindex == PSR_MFL ? 2 : 32; + int max = dep->regindex == PSR_MFL ? 31 : 127; + /* mfh is read on writes to FR32-127; mfl is read on writes to + FR2-31 */ + for (i=0;i < idesc->num_outputs;i++) + { + if (idesc->operands[i] == IA64_OPND_F1) + { + int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; + if (reg >= min && reg <= max) + { + specs[count++] = tmpl; + } + } + } + } + else if (note == 10) + { + for (i=0;i < NELEMS(idesc->operands);i++) + { + if (idesc->operands[i] == IA64_OPND_R1 + || idesc->operands[i] == IA64_OPND_R2 + || idesc->operands[i] == IA64_OPND_R3) + { + int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; + if (regno >= 16 && regno <= 31) + { + specs[count++] = tmpl; + } + } + } + } + else + { + UNHANDLED; + } + break; + + case IA64_RS_AR_FPSR: + if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) + { + int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; + if (regno == AR_FPSR) + { + specs[count++] = tmpl; + } + } + else + { + specs[count++] = tmpl; + } + break; + + case IA64_RS_ARX: + /* Handle all AR[REG] resources */ + if (note == 0 || note == 1) + { + int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; + if (idesc->operands[!rsrc_write] == IA64_OPND_AR3 + && regno == dep->regindex) + { + specs[count++] = tmpl; + } + /* other AR[REG] resources may be affected by AR accesses */ + else if (idesc->operands[0] == IA64_OPND_AR3) + { + /* AR[] writes */ + regno = CURR_SLOT.opnd[0].X_add_number - REG_AR; + switch (dep->regindex) + { + default: + break; + case AR_BSP: + case AR_RNAT: + if (regno == AR_BSPSTORE) + { + specs[count++] = tmpl; + } + case AR_RSC: + if (!rsrc_write && + (regno == AR_BSPSTORE + || regno == AR_RNAT)) + { + specs[count++] = tmpl; + } + break; + } + } + else if (idesc->operands[1] == IA64_OPND_AR3) + { + /* AR[] reads */ + regno = CURR_SLOT.opnd[1].X_add_number - REG_AR; + switch (dep->regindex) + { + default: + break; + case AR_RSC: + if (regno == AR_BSPSTORE || regno == AR_RNAT) + { + specs[count++] = tmpl; + } + break; + } + } + else + { + specs[count++] = tmpl; + } + } + else + { + UNHANDLED; + } + break; + + case IA64_RS_CRX: + /* Handle all CR[REG] resources */ + if (note == 0 || note == 1) + { + if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) + { + int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; + if (regno == dep->regindex) + { + specs[count++] = tmpl; + } + else if (!rsrc_write) + { + /* Reads from CR[IVR] affect other resources. */ + if (regno == CR_IVR) + { + if ((dep->regindex >= CR_IRR0 + && dep->regindex <= CR_IRR3) + || dep->regindex == CR_TPR) + { + specs[count++] = tmpl; + } + } + } + } + else + { + specs[count++] = tmpl; + } + } + else + { + UNHANDLED; + } + break; + + case IA64_RS_INSERVICE: + /* look for write of EOI (67) or read of IVR (65) */ + if ((idesc->operands[0] == IA64_OPND_CR3 + && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI) + || (idesc->operands[1] == IA64_OPND_CR3 + && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR)) + { + specs[count++] = tmpl; + } + break; + + case IA64_RS_GR0: + if (note == 1) + { + specs[count++] = tmpl; + } + else + { + UNHANDLED; + } + break; + + case IA64_RS_CFM: + if (note != 2) + { + specs[count++] = tmpl; + } + else + { + /* Check if any of the registers accessed are in the rotating region. + mov to/from pr accesses CFM only when qp_regno is in the rotating + region */ + for (i=0;i < NELEMS(idesc->operands);i++) + { + if (idesc->operands[i] == IA64_OPND_R1 + || idesc->operands[i] == IA64_OPND_R2 + || idesc->operands[i] == IA64_OPND_R3) + { + int num = CURR_SLOT.opnd[i].X_add_number - REG_GR; + /* Assumes that md.rot.num_regs is always valid */ + if (md.rot.num_regs > 0 + && num > 31 + && num < 31 + md.rot.num_regs) + { + specs[count] = tmpl; + specs[count++].specific = 0; + } + } + else if (idesc->operands[i] == IA64_OPND_F1 + || idesc->operands[i] == IA64_OPND_F2 + || idesc->operands[i] == IA64_OPND_F3 + || idesc->operands[i] == IA64_OPND_F4) + { + int num = CURR_SLOT.opnd[i].X_add_number - REG_FR; + if (num > 31) + { + specs[count] = tmpl; + specs[count++].specific = 0; + } + } + else if (idesc->operands[i] == IA64_OPND_P1 + || idesc->operands[i] == IA64_OPND_P2) + { + int num = CURR_SLOT.opnd[i].X_add_number - REG_P; + if (num > 15) + { + specs[count] = tmpl; + specs[count++].specific = 0; + } + } + } + if (CURR_SLOT.qp_regno > 15) + { + specs[count] = tmpl; + specs[count++].specific = 0; + } + } + break; + + case IA64_RS_PR63: + if (note == 0) + { + specs[count++] = tmpl; + } + else if (note == 11) + { + if ((idesc->operands[0] == IA64_OPND_P1 + && CURR_SLOT.opnd[0].X_add_number - REG_P == 63) + || (idesc->operands[1] == IA64_OPND_P2 + && CURR_SLOT.opnd[1].X_add_number - REG_P == 63)) + { + specs[count++] = tmpl; + } + } + else if (note == 12) + { + if (CURR_SLOT.qp_regno == 63) + { + specs[count++] = tmpl; + } + } + else if (note == 7) + { + valueT mask = 0; + if (idesc->operands[2] == IA64_OPND_IMM17) + mask = CURR_SLOT.opnd[2].X_add_number; + if (mask & ((valueT)1<<63)) + { + specs[count++] = tmpl; + } + } + else if (note == 1) + { + if (rsrc_write) + { + for (i=0;i < idesc->num_outputs;i++) + if ((idesc->operands[i] == IA64_OPND_P1 + || idesc->operands[i] == IA64_OPND_P2) + && CURR_SLOT.opnd[i].X_add_number - REG_P == 63) + { + specs[count++] = tmpl; + } + } + else + { + if (CURR_SLOT.qp_regno == 63) + { + specs[count++] = tmpl; + } + } + } + else + { + UNHANDLED; + } + break; + + case IA64_RS_RSE: + /* FIXME we can identify some individual RSE written resources, but RSE + read resources have not yet been completely identified, so for now + treat RSE as a single resource */ + if (strncmp (idesc->name, "mov", 3) == 0) + { + if (rsrc_write) + { + if (idesc->operands[0] == IA64_OPND_AR3 + && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE) + { + specs[count] = tmpl; + specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */ + } + } + else + { + if (idesc->operands[0] == IA64_OPND_AR3) + { + if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE + || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT) + { + specs[count++] = tmpl; + } + } + else if (idesc->operands[1] == IA64_OPND_AR3) + { + if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP + || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE + || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT) + { + specs[count++] = tmpl; + } + } + } + } + else + { + specs[count++] = tmpl; + } + break; + + case IA64_RS_ANY: + /* FIXME -- do any of these need to be non-specific? */ + specs[count++] = tmpl; + break; + + default: + as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier); + break; + } + + return count; +} + +/* Clear branch flags on marked resources. This breaks the link between the + QP of the marking instruction and a subsequent branch on the same QP. +*/ +static void +clear_qp_branch_flag (mask) + valueT mask; +{ + int i; + for (i = 0;i < regdepslen;i++) + { + valueT bit = ((valueT)1 << regdeps[i].qp_regno); + if ((bit & mask) != 0) + { + regdeps[i].link_to_qp_branch = 0; + } + } +} + +/* Remove any mutexes which contain any of the PRs indicated in the mask. + + Any changes to a PR clears the mutex relations which include that PR. +*/ +static void +clear_qp_mutex (mask) + valueT mask; +{ + int i; + + i = 0; + while (i < qp_mutexeslen) + { + if ((qp_mutexes[i].prmask & mask) != 0) + { + if (md.debug_dv) + { + fprintf (stderr, " Clearing mutex relation"); + print_prmask (qp_mutexes[i].prmask); + fprintf (stderr, "\n"); + } + qp_mutexes[i] = qp_mutexes[--qp_mutexeslen]; + } + else + ++i; + } +} + +/* Clear implies relations which contain PRs in the given masks. + P1_MASK indicates the source of the implies relation, while P2_MASK + indicates the implied PR. +*/ +static void +clear_qp_implies (p1_mask, p2_mask) + valueT p1_mask; + valueT p2_mask; +{ + int i; + + i = 0; + while (i < qp_implieslen) + { + if ((((valueT)1 << qp_implies[i].p1) & p1_mask) != 0 + || (((valueT)1 << qp_implies[i].p2) & p2_mask) != 0) + { + if (md.debug_dv) + fprintf (stderr, "Clearing implied relation PR%d->PR%d\n", + qp_implies[i].p1, qp_implies[i].p2); + qp_implies[i] = qp_implies[--qp_implieslen]; + } + else + ++i; + } +} + +/* add the PRs specified to the list of implied relations */ +static void +add_qp_imply (p1, p2) + int p1, p2; +{ + valueT mask; + valueT bit; + int i; + + /* p0 is not meaningful here */ + if (p1 == 0 || p2 == 0) + abort (); + + if (p1 == p2) + return; + + /* if it exists already, ignore it */ + for (i=0;i < qp_implieslen;i++) + { + if (qp_implies[i].p1 == p1 + && qp_implies[i].p2 == p2 + && qp_implies[i].path == md.path + && !qp_implies[i].p2_branched) + return; + } + + if (qp_implieslen == qp_impliestotlen) + { + qp_impliestotlen += 20; + qp_implies = (struct qp_imply *) + xrealloc ((void *)qp_implies, + qp_impliestotlen * sizeof (struct qp_imply)); + } + if (md.debug_dv) + fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2); + qp_implies[qp_implieslen].p1 = p1; + qp_implies[qp_implieslen].p2 = p2; + qp_implies[qp_implieslen].path = md.path; + qp_implies[qp_implieslen++].p2_branched = 0; + + /* Add in the implied transitive relations; for everything that p2 implies, + make p1 imply that, too; for everything that implies p1, make it imply p2 + as well. */ + for (i=0;i < qp_implieslen;i++) + { + if (qp_implies[i].p1 == p2) + add_qp_imply (p1, qp_implies[i].p2); + if (qp_implies[i].p2 == p1) + add_qp_imply (qp_implies[i].p1, p2); + } + /* Add in mutex relations implied by this implies relation; for each mutex + relation containing p2, duplicate it and replace p2 with p1. */ + bit = (valueT)1 << p1; + mask = (valueT)1 << p2; + for (i=0;i < qp_mutexeslen;i++) + { + if (qp_mutexes[i].prmask & mask) + add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit); + } +} + + +/* Add the PRs specified in the mask to the mutex list; this means that only + one of the PRs can be true at any time. PR0 should never be included in + the mask. */ +static void +add_qp_mutex (mask) + valueT mask; +{ + if (mask & 0x1) + abort (); + + if (qp_mutexeslen == qp_mutexestotlen) + { + qp_mutexestotlen += 20; + qp_mutexes = (struct qpmutex *) + xrealloc ((void *)qp_mutexes, + qp_mutexestotlen * sizeof (struct qpmutex)); + } + if (md.debug_dv) + { + fprintf (stderr, " Registering mutex on"); + print_prmask (mask); + fprintf (stderr, "\n"); + } + qp_mutexes[qp_mutexeslen].path = md.path; + qp_mutexes[qp_mutexeslen++].prmask = mask; +} + +static void +clear_register_values () +{ + int i; + if (md.debug_dv) + fprintf (stderr, " Clearing register values\n"); + for (i=1;i < NELEMS(gr_values);i++) + gr_values[i].known = 0; +} + +/* Keep track of register values/changes which affect DV tracking. + + optimization note: should add a flag to classes of insns where otherwise we + have to examine a group of strings to identify them. + + */ +static void +note_register_values (idesc) + struct ia64_opcode *idesc; +{ + valueT qp_changemask = 0; + int i; + + /* invalidate values for registers being written to */ + for (i=0;i < idesc->num_outputs;i++) + { + if (idesc->operands[i] == IA64_OPND_R1 + || idesc->operands[i] == IA64_OPND_R2 + || idesc->operands[i] == IA64_OPND_R3) + { + int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; + if (regno > 0 && regno < NELEMS(gr_values)) + gr_values[regno].known = 0; + } + else if (idesc->operands[i] == IA64_OPND_P1 + || idesc->operands[i] == IA64_OPND_P2) + { + int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; + qp_changemask |= (valueT)1 << regno; + } + else if (idesc->operands[i] == IA64_OPND_PR) + { + if (idesc->operands[2] & (valueT)0x10000) + qp_changemask = ~(valueT)0x1FFFF | idesc->operands[2]; + else + qp_changemask = idesc->operands[2]; + break; + } + else if (idesc->operands[i] == IA64_OPND_PR_ROT) + { + if (idesc->operands[1] & ((valueT)1 << 43)) + qp_changemask = ~(valueT)0xFFFFFFFFFFF | idesc->operands[1]; + else + qp_changemask = idesc->operands[1]; + qp_changemask &= ~(valueT)0xFFFF; + break; + } + } + + /* Always clear qp branch flags on any PR change */ + /* FIXME there may be exceptions for certain compares */ + clear_qp_branch_flag (qp_changemask); + + /* invalidate rotating registers on insns which affect RRBs in CFM */ + if (idesc->flags & IA64_OPCODE_MOD_RRBS) + { + qp_changemask |= ~(valueT)0xFFFF; + if (strcmp (idesc->name, "clrrrb.pr") != 0) + { + for (i=32;i < 32+md.rot.num_regs;i++) + gr_values[i].known = 0; + } + clear_qp_mutex (qp_changemask); + clear_qp_implies (qp_changemask, qp_changemask); + } + /* after a call, all register values are undefined, except those marked + as "safe" */ + else if (strncmp (idesc->name, "br.call", 6) == 0 + || strncmp (idesc->name, "brl.call", 7) == 0) + { + // FIXME keep GR values which are marked as "safe_across_calls" + clear_register_values (); + clear_qp_mutex (~qp_safe_across_calls); + clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls); + clear_qp_branch_flag (~qp_safe_across_calls); + } + /* Look for mutex and implies relations */ + else if ((idesc->operands[0] == IA64_OPND_P1 + || idesc->operands[0] == IA64_OPND_P2) + && (idesc->operands[1] == IA64_OPND_P1 + || idesc->operands[1] == IA64_OPND_P2)) + { + int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; + int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; + valueT p1mask = (valueT)1 << p1; + valueT p2mask = (valueT)1 << p2; + + /* if one of the PRs is PR0, we can't really do anything */ + if (p1 == 0 || p2 == 0) + { + if (md.debug_dv) + fprintf (stderr, " Ignoring PRs due to inclusion of p0\n"); + } + /* In general, clear mutexes and implies which include P1 or P2, + with the following exceptions */ + else if (strstr (idesc->name, ".or.andcm") != NULL) + { + add_qp_mutex (p1mask | p2mask); + clear_qp_implies (p2mask, p1mask); + } + else if (strstr (idesc->name, ".and.orcm") != NULL) + { + add_qp_mutex (p1mask | p2mask); + clear_qp_implies (p1mask, p2mask); + } + else if (strstr (idesc->name, ".and") != NULL) + { + clear_qp_implies (0, p1mask | p2mask); + } + else if (strstr (idesc->name, ".or") != NULL) + { + clear_qp_mutex (p1mask | p2mask); + clear_qp_implies (p1mask | p2mask, 0); + } + else + { + clear_qp_implies (p1mask | p2mask, p1mask | p2mask); + if (strstr (idesc->name, ".unc") != NULL) + { + add_qp_mutex (p1mask | p2mask); + if (CURR_SLOT.qp_regno != 0) + { + add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P, + CURR_SLOT.qp_regno); + add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P, + CURR_SLOT.qp_regno); + } + } + else if (CURR_SLOT.qp_regno == 0) + { + add_qp_mutex (p1mask | p2mask); + } + else + { + clear_qp_mutex (p1mask | p2mask); + } + } + } + /* Look for mov imm insns into GRs */ + else if (idesc->operands[0] == IA64_OPND_R1 + && (idesc->operands[1] == IA64_OPND_IMM22 + || idesc->operands[1] == IA64_OPND_IMMU64) + && (strcmp(idesc->name, "mov") == 0 + || strcmp(idesc->name, "movl") == 0)) + { + int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR; + if (regno > 0 && regno < NELEMS(gr_values)) + { + gr_values[regno].known = 1; + gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number; + gr_values[regno].path = md.path; + if (md.debug_dv) + fprintf (stderr, " Know gr%d = 0x%llx\n", + regno, gr_values[regno].value); + } + } + else + { + clear_qp_mutex (qp_changemask); + clear_qp_implies (qp_changemask, qp_changemask); + } +} + +/* Return whether the given predicate registers are currently mutex */ +static int +qp_mutex (p1, p2, path) + int p1; + int p2; + int path; +{ + int i; + valueT mask; + + if (p1 != p2) + { + mask = ((valueT)1<<p1) | (valueT)1<<p2; + for (i=0;i < qp_mutexeslen;i++) + { + if (qp_mutexes[i].path >= path + && (qp_mutexes[i].prmask & mask) == mask) + return 1; + } + } + return 0; +} + +/* Return whether the given resource is in the given insn's list of chks + Return 1 if the conflict is absolutely determined, 2 if it's a potential + conflict. + */ +static int +resources_match (rs, idesc, note, qp_regno, path) + struct rsrc *rs; + struct ia64_opcode *idesc; + int note; + int qp_regno; + int path; +{ + struct rsrc specs[MAX_SPECS]; + int count; + + /* If the marked resource's qp_regno and the given qp_regno are mutex, + we don't need to check. One exception is note 11, which indicates that + target predicates are written regardless of PR[qp]. */ + if (qp_mutex (rs->qp_regno, qp_regno, path) + && note != 11) + return 0; + + count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path); + while (count-- > 0) + { + /* UNAT checking is a bit more specific than other resources */ + if (rs->dependency->specifier == IA64_RS_AR_UNAT + && specs[count].mem_offset.hint + && rs->mem_offset.hint) + { + if (rs->mem_offset.base == specs[count].mem_offset.base) + { + if (((rs->mem_offset.offset >> 3) & 0x3F) == + ((specs[count].mem_offset.offset >> 3) & 0x3F)) + return 1; + else + continue; + } + } + + /* If either resource is not specific, conservatively assume a conflict + */ + if (!specs[count].specific || !rs->specific) + return 2; + else if (specs[count].index == rs->index) + return 1; + } +#if 0 + if (md.debug_dv) + fprintf (stderr, " No %s conflicts\n", rs->dependency->name); +#endif + + return 0; +} + +/* Indicate an instruction group break; if INSERT_STOP is non-zero, then + insert a stop to create the break. Update all resource dependencies + appropriately. If QP_REGNO is non-zero, only apply the break to resources + which use the same QP_REGNO and have the link_to_qp_branch flag set. + If SAVE_CURRENT is non-zero, don't affect resources marked by the current + instruction. +*/ + +static void +insn_group_break (insert_stop, qp_regno, save_current) + int insert_stop; + int qp_regno; + int save_current; +{ + int i; + + if (insert_stop && md.num_slots_in_use > 0) + PREV_SLOT.end_of_insn_group = 1; + + if (md.debug_dv) + { + fprintf (stderr, " Insn group break%s", + (insert_stop ? " (w/stop)" : "")); + if (qp_regno != 0) + fprintf (stderr, " effective for QP=%d", qp_regno); + fprintf (stderr, "\n"); + } + + i = 0; + while (i < regdepslen) + { + const struct ia64_dependency *dep = regdeps[i].dependency; + + if (qp_regno != 0 + && regdeps[i].qp_regno != qp_regno) + { + ++i; + continue; + } + + if (save_current + && CURR_SLOT.src_file == regdeps[i].file + && CURR_SLOT.src_line == regdeps[i].line) + { + ++i; + continue; + } + + /* clear dependencies which are automatically cleared by a stop, or + those that have reached the appropriate state of insn serialization */ + if (dep->semantics == IA64_DVS_IMPLIED + || dep->semantics == IA64_DVS_IMPLIEDF + || regdeps[i].insn_srlz == STATE_SRLZ) + { + print_dependency ("Removing", i); + regdeps[i] = regdeps[--regdepslen]; + } + else + { + if (dep->semantics == IA64_DVS_DATA + || dep->semantics == IA64_DVS_INSTR + || dep->semantics == IA64_DVS_SPECIFIC) + { + if (regdeps[i].insn_srlz == STATE_NONE) + regdeps[i].insn_srlz = STATE_STOP; + if (regdeps[i].data_srlz == STATE_NONE) + regdeps[i].data_srlz = STATE_STOP; + } + ++i; + } + } +} + +/* Add the given resource usage spec to the list of active dependencies */ +static void +mark_resource (idesc, dep, spec, depind, path) + struct ia64_opcode *idesc; + const struct ia64_dependency *dep; + struct rsrc *spec; + int depind; + int path; +{ + if (regdepslen == regdepstotlen) + { + regdepstotlen += 20; + regdeps = (struct rsrc *) + xrealloc ((void *)regdeps, + regdepstotlen * sizeof(struct rsrc)); + } + + regdeps[regdepslen] = *spec; + regdeps[regdepslen].depind = depind; + regdeps[regdepslen].path = path; + regdeps[regdepslen].file = CURR_SLOT.src_file; + regdeps[regdepslen].line = CURR_SLOT.src_line; + + print_dependency ("Adding", regdepslen); + + ++regdepslen; +} + +static void +print_dependency (action, depind) + const char *action; + int depind; +{ + if (md.debug_dv) + { + fprintf (stderr, " %s %s '%s'", + action, dv_mode[(regdeps[depind].dependency)->mode], + (regdeps[depind].dependency)->name); + if (regdeps[depind].specific && regdeps[depind].index != 0) + fprintf (stderr, " (%d)", regdeps[depind].index); + if (regdeps[depind].mem_offset.hint) + fprintf (stderr, " 0x%llx+0x%llx", + regdeps[depind].mem_offset.base, + regdeps[depind].mem_offset.offset); + fprintf (stderr, "\n"); + } +} + +static void +instruction_serialization () +{ + int i; + if (md.debug_dv) + fprintf (stderr, " Instruction serialization\n"); + for (i=0;i < regdepslen;i++) + if (regdeps[i].insn_srlz == STATE_STOP) + regdeps[i].insn_srlz = STATE_SRLZ; +} + +static void +data_serialization () +{ + int i = 0; + if (md.debug_dv) + fprintf (stderr, " Data serialization\n"); + while (i < regdepslen) + { + if (regdeps[i].data_srlz == STATE_STOP + /* Note: as of 991210, all "other" dependencies are cleared by a + data serialization. This might change with new tables */ + || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER) + { + print_dependency ("Removing", i); + regdeps[i] = regdeps[--regdepslen]; + } + else + ++i; + } +} + +/* Insert stops and serializations as needed to avoid DVs */ +static void +remove_marked_resource (rs) + struct rsrc *rs; +{ + switch (rs->dependency->semantics) + { + case IA64_DVS_SPECIFIC: + if (md.debug_dv) + fprintf (stderr, "Implementation-specific, assume worst case...\n"); + /* ...fall through... */ + case IA64_DVS_INSTR: + if (md.debug_dv) + fprintf (stderr, "Inserting instr serialization\n"); + if (rs->insn_srlz < STATE_STOP) + insn_group_break (1, 0, 0); + if (rs->insn_srlz < STATE_SRLZ) + { + int oldqp = CURR_SLOT.qp_regno; + struct ia64_opcode *oldidesc = CURR_SLOT.idesc; + /* Manually jam a srlz.i insn into the stream */ + CURR_SLOT.qp_regno = 0; + CURR_SLOT.idesc = ia64_find_opcode ("srlz.i"); + instruction_serialization (); + md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; + if (++md.num_slots_in_use >= NUM_SLOTS) + emit_one_bundle (); + CURR_SLOT.qp_regno = oldqp; + CURR_SLOT.idesc = oldidesc; + } + insn_group_break (1, 0, 0); + break; + case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all + "other" types of DV are eliminated + by a data serialization */ + case IA64_DVS_DATA: + if (md.debug_dv) + fprintf (stderr, "Inserting data serialization\n"); + if (rs->data_srlz < STATE_STOP) + insn_group_break (1, 0, 0); + { + int oldqp = CURR_SLOT.qp_regno; + struct ia64_opcode *oldidesc = CURR_SLOT.idesc; + /* Manually jam a srlz.d insn into the stream */ + CURR_SLOT.qp_regno = 0; + CURR_SLOT.idesc = ia64_find_opcode ("srlz.d"); + data_serialization (); + md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; + if (++md.num_slots_in_use >= NUM_SLOTS) + emit_one_bundle (); + CURR_SLOT.qp_regno = oldqp; + CURR_SLOT.idesc = oldidesc; + } + break; + case IA64_DVS_IMPLIED: + case IA64_DVS_IMPLIEDF: + if (md.debug_dv) + fprintf (stderr, "Inserting stop\n"); + insn_group_break (1, 0, 0); + break; + default: + break; + } +} + +/* Check the resources used by the given opcode against the current dependency + list. + + The check is run once for each execution path encountered. In this case, + a unique execution path is the sequence of instructions following a code + entry point, e.g. the following has three execution paths, one starting + at L0, one at L1, and one at L2. + + L0: nop + L1: add + L2: add + br.ret +*/ +static void +check_dependencies (idesc) + struct ia64_opcode *idesc; +{ + const struct ia64_opcode_dependency *opdeps = idesc->dependencies; + int path; + int i; + + /* Note that the number of marked resources may change within the + loop if in auto mode. */ + i = 0; + while (i < regdepslen) + { + struct rsrc *rs = ®deps[i]; + const struct ia64_dependency *dep = rs->dependency; + int chkind; + int note; + int start_over = 0; + + if (dep->semantics == IA64_DVS_NONE + || (chkind = depends_on (rs->depind, idesc)) == -1) + { + ++i; continue; + } + + note = NOTE(opdeps->chks[chkind]); + + /* Check this resource against each execution path seen thus far */ + for (path=0;path <= md.path;path++) + { + int matchtype; + + /* If the dependency wasn't on the path being checked, ignore it */ + if (rs->path < path) + continue; + + /* If the QP for this insn implies a QP which has branched, don't + bother checking. Ed. NOTE: I don't think this check is terribly + useful; what's the point of generating code which will only be + reached if its QP is zero? + This code was specifically inserted to handle the following code, + based on notes from Intel's DV checking code, where p1 implies p2. + + mov r4 = 2 + (p2) br.cond L + (p1) mov r4 = 7 + + */ + if (CURR_SLOT.qp_regno != 0) + { + int skip = 0; + int implies; + for (implies=0;implies < qp_implieslen;implies++) + { + if (qp_implies[implies].path >= path + && qp_implies[implies].p1 == CURR_SLOT.qp_regno + && qp_implies[implies].p2_branched) + { + skip = 1; + break; + } + } + if (skip) + continue; + } + + if ((matchtype = resources_match (rs, idesc, note, + CURR_SLOT.qp_regno, path)) != 0) + { + char msg[1024]; + char pathmsg[256] = ""; + char indexmsg[256] = ""; + int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0); + + if (path != 0) + sprintf (pathmsg, " when entry is at label '%s'", + md.entry_labels[path-1]); + if (rs->specific && rs->index != 0) + sprintf (indexmsg, ", specific resource number is %d", + rs->index); + sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s", + idesc->name, + (certain ? "violates" : "may violate"), + dv_mode[dep->mode], dep->name, + dv_sem[dep->semantics], + pathmsg, indexmsg); + + if (md.explicit_mode) + { + as_warn ("%s", msg); + if (path < md.path) + as_warn (_("Only the first path encountering the conflict " + "is reported")); + as_warn_where (rs->file, rs->line, + _("This is the location of the " + "conflicting usage")); + /* Don't bother checking other paths, to avoid duplicating + the same warning */ + break; + } + else + { + if (md.debug_dv) + fprintf(stderr, "%s @ %s:%d\n", msg, rs->file, rs->line); + + remove_marked_resource (rs); + + /* since the set of dependencies has changed, start over */ + /* FIXME -- since we're removing dvs as we go, we + probably don't really need to start over... */ + start_over = 1; + break; + } + } + } + if (start_over) + i = 0; + else + ++i; + } +} + +/* register new dependencies based on the given opcode */ +static void +mark_resources (idesc) + struct ia64_opcode *idesc; +{ + int i; + const struct ia64_opcode_dependency *opdeps = idesc->dependencies; + int add_only_qp_reads = 0; + + /* A conditional branch only uses its resources if it is taken; if it is + taken, we stop following that path. The other branch types effectively + *always* write their resources. If it's not taken, register only QP + reads. */ + if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc)) + { + add_only_qp_reads = 1; + } + + if (md.debug_dv) + fprintf (stderr, "Registering '%s' resource usage\n", idesc->name); + + for (i=0;i < opdeps->nregs;i++) + { + const struct ia64_dependency *dep; + struct rsrc specs[MAX_SPECS]; + int note; + int path; + int count; + + dep = ia64_find_dependency (opdeps->regs[i]); + note = NOTE(opdeps->regs[i]); + + if (add_only_qp_reads + && !(dep->mode == IA64_DV_WAR + && (dep->specifier == IA64_RS_PR + || dep->specifier == IA64_RS_PR63))) + continue; + + count = specify_resource (dep, idesc, DV_REG, specs, note, md.path); + +#if 0 + if (md.debug_dv && !count) + fprintf (stderr, " No %s %s usage found (path %d)\n", + dv_mode[dep->mode], dep->name, md.path); +#endif + + while (count-- > 0) + { + mark_resource (idesc, dep, &specs[count], + DEP(opdeps->regs[i]), md.path); + } + + /* The execution path may affect register values, which may in turn + affect which indirect-access resources are accessed. */ + switch (dep->specifier) + { + default: + break; + case IA64_RS_CPUID: + case IA64_RS_DBR: + case IA64_RS_IBR: + case IA64_RS_MSR: + case IA64_RS_PKR: + case IA64_RS_PMC: + case IA64_RS_PMD: + case IA64_RS_RR: + for (path=0;path < md.path;path++) + { + count = specify_resource (dep, idesc, DV_REG, specs, note, path); + while (count-- > 0) + mark_resource (idesc, dep, &specs[count], + DEP(opdeps->regs[i]), path); + } + break; + } + } +} + +/* remove dependencies when they no longer apply */ +static void +update_dependencies (idesc) + struct ia64_opcode *idesc; +{ + int i; + + if (strcmp (idesc->name, "srlz.i") == 0) + { + instruction_serialization (); + } + else if (strcmp (idesc->name, "srlz.d") == 0) + { + data_serialization (); + } + else if (is_interruption_or_rfi (idesc) + || is_taken_branch (idesc)) + { + /* although technically the taken branch doesn't clear dependencies + which require a srlz.[id], we don't follow the branch; the next + instruction is assumed to start with a clean slate */ + regdepslen = 0; + clear_register_values (); + clear_qp_mutex (~(valueT)0); + clear_qp_implies (~(valueT)0, ~(valueT)0); + md.path = 0; + } + else if (is_conditional_branch (idesc) + && CURR_SLOT.qp_regno != 0) + { + int is_call = strstr (idesc->name, ".call") != NULL; + + for (i=0;i < qp_implieslen;i++) + { + /* if the conditional branch's predicate is implied by the predicate + in an existing dependency, remove that dependency */ + if (qp_implies[i].p2 == CURR_SLOT.qp_regno) + { + int depind = 0; + /* note that this implied predicate takes a branch so that if + a later insn generates a DV but its predicate implies this + one, we can avoid the false DV warning */ + qp_implies[i].p2_branched = 1; + while (depind < regdepslen) + { + if (regdeps[depind].qp_regno == qp_implies[i].p1) + { + print_dependency ("Removing", depind); + regdeps[depind] = regdeps[--regdepslen]; + } + else + ++depind; + } + } + } + /* Any marked resources which have this same predicate should be + cleared, provided that the QP hasn't been modified between the + marking instruction and the branch. + */ + if (is_call) + { + insn_group_break (0, CURR_SLOT.qp_regno, 1); + } + else + { + i = 0; + while (i < regdepslen) + { + if (regdeps[i].qp_regno == CURR_SLOT.qp_regno + && regdeps[i].link_to_qp_branch + && (regdeps[i].file != CURR_SLOT.src_file + || regdeps[i].line != CURR_SLOT.src_line)) + { + /* Treat like a taken branch */ + print_dependency ("Removing", i); + regdeps[i] = regdeps[--regdepslen]; + } + else + ++i; + } + } + } +} + +/* Examine the current instruction for dependency violations. */ +static int +check_dv (idesc) + struct ia64_opcode *idesc; +{ + if (md.debug_dv) + { + fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n", + idesc->name, CURR_SLOT.src_line, + idesc->dependencies->nchks, + idesc->dependencies->nregs); + } + + /* Look through the list of currently marked resources; if the current + instruction has the dependency in its chks list which uses that resource, + check against the specific resources used. + */ + check_dependencies (idesc); + + /* + Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads), + then add them to the list of marked resources. + */ + mark_resources (idesc); + + /* There are several types of dependency semantics, and each has its own + requirements for being cleared + + Instruction serialization (insns separated by interruption, rfi, or + writer + srlz.i + reader, all in separate groups) clears DVS_INSTR. + + Data serialization (instruction serialization, or writer + srlz.d + + reader, where writer and srlz.d are in separate groups) clears + DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to + always be the case). + + Instruction group break (groups separated by stop, taken branch, + interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF. + */ + update_dependencies (idesc); + + /* Sometimes, knowing a register value allows us to avoid giving a false DV + warning. Keep track of as many as possible that are useful. */ + note_register_values (idesc); + + /* We don't need or want this anymore. */ + md.mem_offset.hint = 0; + + return 0; +} + +/* Translate one line of assembly. Pseudo ops and labels do not show + here. */ +void +md_assemble (str) + char *str; +{ + char *saved_input_line_pointer, *mnemonic; + const struct pseudo_opcode *pdesc; + struct ia64_opcode *idesc; + unsigned char qp_regno; + unsigned int flags; + int ch; + + saved_input_line_pointer = input_line_pointer; + input_line_pointer = str; + + /* extract the opcode (mnemonic): */ + + mnemonic = input_line_pointer; + ch = get_symbol_end (); + pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic); + if (pdesc) + { + *input_line_pointer = ch; + (*pdesc->handler) (pdesc->arg); + goto done; + } + + /* find the instruction descriptor matching the arguments: */ + + idesc = ia64_find_opcode (mnemonic); + *input_line_pointer = ch; + if (!idesc) + { + as_bad ("Unknown opcode `%s'", mnemonic); + goto done; + } + + idesc = parse_operands (idesc); + if (!idesc) + goto done; + + /* Handle the dynamic ops we can handle now: */ + if (idesc->type == IA64_TYPE_DYN) + { + if (strcmp (idesc->name, "add") == 0) + { + if (CURR_SLOT.opnd[2].X_op == O_register + && CURR_SLOT.opnd[2].X_add_number < 4) + mnemonic = "addl"; + else + mnemonic = "adds"; + idesc = ia64_find_opcode (mnemonic); +#if 0 + know (!idesc->next); +#endif + } + else if (strcmp (idesc->name, "mov") == 0) + { + enum ia64_opnd opnd1, opnd2; + int rop; + + opnd1 = idesc->operands[0]; + opnd2 = idesc->operands[1]; + if (opnd1 == IA64_OPND_AR3) + rop = 0; + else if (opnd2 == IA64_OPND_AR3) + rop = 1; + else + abort (); + if (CURR_SLOT.opnd[rop].X_op == O_register + && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number)) + mnemonic = "mov.i"; + else + mnemonic = "mov.m"; + idesc = ia64_find_opcode (mnemonic); + while (idesc != NULL + && (idesc->operands[0] != opnd1 + || idesc->operands[1] != opnd2)) + idesc = get_next_opcode (idesc); + } + } + + qp_regno = 0; + if (md.qp.X_op == O_register) + qp_regno = md.qp.X_add_number - REG_P; + + flags = idesc->flags; + + if ((flags & IA64_OPCODE_FIRST) != 0) + insn_group_break (1, 0, 0); + + if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0) + { + as_bad ("`%s' cannot be predicated", idesc->name); + goto done; + } + + /* build the instruction: */ + CURR_SLOT.qp_regno = qp_regno; + CURR_SLOT.idesc = idesc; + as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line); + if (debug_type == DEBUG_DWARF2) + dwarf2_where (&CURR_SLOT.debug_line); + + /* Add unwind entry, if there is one. */ + if (current_unwind_entry) + { + CURR_SLOT.unwind_record = current_unwind_entry; + current_unwind_entry = NULL; + } + + /* check for dependency violations */ + if (md.detect_dv) + check_dv(idesc); + + md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; + if (++md.num_slots_in_use >= NUM_SLOTS) + emit_one_bundle (); + + if ((flags & IA64_OPCODE_LAST) != 0) + insn_group_break (1, 0, 0); + + md.last_text_seg = now_seg; + + done: + input_line_pointer = saved_input_line_pointer; +} + +/* Called when symbol NAME cannot be found in the symbol table. + Should be used for dynamic valued symbols only. */ +symbolS* +md_undefined_symbol (name) + char *name; +{ + return 0; +} + +/* Called for any expression that can not be recognized. When the + function is called, `input_line_pointer' will point to the start of + the expression. */ +void +md_operand (e) + expressionS *e; +{ + enum pseudo_type pseudo_type; + size_t len; + int ch, i; + + switch (*input_line_pointer) + { + case '@': + /* find what relocation pseudo-function we're dealing with: */ + pseudo_type = 0; + ch = *++input_line_pointer; + for (i = 0; i < NELEMS (pseudo_func); ++i) + if (pseudo_func[i].name && pseudo_func[i].name[0] == ch) + { + len = strlen (pseudo_func[i].name); + if (strncmp (pseudo_func[i].name + 1, + input_line_pointer + 1, len - 1) == 0 + && !is_part_of_name (input_line_pointer[len])) + { + input_line_pointer += len; + pseudo_type = pseudo_func[i].type; + break; + } + } + switch (pseudo_type) + { + case PSEUDO_FUNC_RELOC: + SKIP_WHITESPACE (); + if (*input_line_pointer != '(') + { + as_bad ("Expected '('"); + goto err; + } + ++input_line_pointer; /* skip '(' */ + expression (e); + if (*input_line_pointer++ != ')') + { + as_bad ("Missing ')'"); + goto err; + } + if (e->X_op != O_symbol) + { + if (e->X_op != O_pseudo_fixup) + { + as_bad ("Not a symbolic expression"); + goto err; + } + if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE + && i == FUNC_LT_RELATIVE) + i = FUNC_LT_FPTR_RELATIVE; + else + { + as_bad ("Illegal combination of relocation functions"); + goto err; + } + } + /* make sure gas doesn't get rid of local symbols that are used + in relocs: */ + e->X_op = O_pseudo_fixup; + e->X_op_symbol = pseudo_func[i].u.sym; + break; + + case PSEUDO_FUNC_CONST: + e->X_op = O_constant; + e->X_add_number = pseudo_func[i].u.ival; + break; + + default: + as_bad ("Unknown pseudo function `%s'", input_line_pointer - 1); + goto err; + } + break; + + case '[': + ++input_line_pointer; + expression (e); + if (*input_line_pointer != ']') + { + as_bad ("Closing bracket misssing"); + goto err; + } + else + { + if (e->X_op != O_register) + as_bad ("Register expected as index"); + + ++input_line_pointer; + e->X_op = O_index; + } + break; + + default: + break; + } + return; + + err: + ignore_rest_of_line (); +} + +/* Return 1 if it's OK to adjust a reloc by replacing the symbol with + a section symbol plus some offset. For relocs involving @fptr(), + directives we don't want such adjustments since we need to have the + original symbol's name in the reloc. */ +int +ia64_fix_adjustable (fix) + fixS *fix; +{ + /* Prevent all adjustments to global symbols */ + if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy)) + return 0; + + switch (fix->fx_r_type) + { + case BFD_RELOC_IA64_FPTR64I: + case BFD_RELOC_IA64_FPTR32MSB: + case BFD_RELOC_IA64_FPTR32LSB: + case BFD_RELOC_IA64_FPTR64MSB: + case BFD_RELOC_IA64_FPTR64LSB: + case BFD_RELOC_IA64_LTOFF_FPTR22: + case BFD_RELOC_IA64_LTOFF_FPTR64I: + return 0; + default: + break; + } + + return 1; +} + +int +ia64_force_relocation (fix) + fixS *fix; +{ + switch (fix->fx_r_type) + { + case BFD_RELOC_IA64_FPTR64I: + case BFD_RELOC_IA64_FPTR32MSB: + case BFD_RELOC_IA64_FPTR32LSB: + case BFD_RELOC_IA64_FPTR64MSB: + case BFD_RELOC_IA64_FPTR64LSB: + + case BFD_RELOC_IA64_LTOFF22: + case BFD_RELOC_IA64_LTOFF64I: + case BFD_RELOC_IA64_LTOFF_FPTR22: + case BFD_RELOC_IA64_LTOFF_FPTR64I: + case BFD_RELOC_IA64_PLTOFF22: + case BFD_RELOC_IA64_PLTOFF64I: + case BFD_RELOC_IA64_PLTOFF64MSB: + case BFD_RELOC_IA64_PLTOFF64LSB: + return 1; + + default: + return 0; + } + return 0; +} + +/* Decide from what point a pc-relative relocation is relative to, + relative to the pc-relative fixup. Er, relatively speaking. */ +long +ia64_pcrel_from_section (fix, sec) + fixS *fix; + segT sec; +{ + unsigned long off = fix->fx_frag->fr_address + fix->fx_where; + + if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE) + off &= ~0xfUL; + + return off; +} + +/* This is called whenever some data item (not an instruction) needs a + fixup. We pick the right reloc code depending on the byteorder + currently in effect. */ +void +ia64_cons_fix_new (f, where, nbytes, exp) + fragS *f; + int where; + int nbytes; + expressionS *exp; +{ + bfd_reloc_code_real_type code; + fixS *fix; + + switch (nbytes) + { + /* There are no reloc for 8 and 16 bit quantities, but we allow + them here since they will work fine as long as the expression + is fully defined at the end of the pass over the source file. */ + case 1: code = BFD_RELOC_8; break; + case 2: code = BFD_RELOC_16; break; + case 4: + if (target_big_endian) + code = BFD_RELOC_IA64_DIR32MSB; + else + code = BFD_RELOC_IA64_DIR32LSB; + break; + + case 8: + if (target_big_endian) + code = BFD_RELOC_IA64_DIR64MSB; + else + code = BFD_RELOC_IA64_DIR64LSB; + break; + + default: + as_bad ("Unsupported fixup size %d", nbytes); + ignore_rest_of_line (); + return; + } + if (exp->X_op == O_pseudo_fixup) + { + /* ??? */ + exp->X_op = O_symbol; + code = ia64_gen_real_reloc_type (exp->X_op_symbol, code); + } + fix = fix_new_exp (f, where, nbytes, exp, 0, code); + /* We need to store the byte order in effect in case we're going + to fix an 8 or 16 bit relocation (for which there no real + relocs available). See md_apply_fix(). */ + fix->tc_fix_data.bigendian = target_big_endian; +} + +/* Return the actual relocation we wish to associate with the pseudo + reloc described by SYM and R_TYPE. SYM should be one of the + symbols in the pseudo_func array, or NULL. */ + +static bfd_reloc_code_real_type +ia64_gen_real_reloc_type (sym, r_type) + struct symbol *sym; + bfd_reloc_code_real_type r_type; +{ + bfd_reloc_code_real_type new = 0; + + if (sym == NULL) + { + return r_type; + } + + switch (S_GET_VALUE (sym)) + { + case FUNC_FPTR_RELATIVE: + switch (r_type) + { + case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break; + case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break; + case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break; + case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break; + case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break; + default: break; + } + break; + + case FUNC_GP_RELATIVE: + switch (r_type) + { + case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break; + case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break; + case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break; + case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break; + case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break; + case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break; + default: break; + } + break; + + case FUNC_LT_RELATIVE: + switch (r_type) + { + case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break; + case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break; + default: break; + } + break; + + case FUNC_PLT_RELATIVE: + switch (r_type) + { + case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break; + case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break; + case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break; + case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break; + default: break; + } + break; + + case FUNC_SEC_RELATIVE: + switch (r_type) + { + case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break; + case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break; + case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break; + case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break; + default: break; + } + break; + + case FUNC_SEG_RELATIVE: + switch (r_type) + { + case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break; + case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break; + case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break; + case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break; + default: break; + } + break; + + case FUNC_LTV_RELATIVE: + switch (r_type) + { + case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break; + case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break; + case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break; + case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break; + default: break; + } + break; + + case FUNC_LT_FPTR_RELATIVE: + switch (r_type) + { + case BFD_RELOC_IA64_IMM22: + new = BFD_RELOC_IA64_LTOFF_FPTR22; break; + case BFD_RELOC_IA64_IMM64: + new = BFD_RELOC_IA64_LTOFF_FPTR64I; break; + default: + break; + } + break; + default: + abort (); + } + /* Hmmmm. Should this ever occur? */ + if (new) + return new; + else + return r_type; +} + +/* Here is where generate the appropriate reloc for pseudo relocation + functions. */ +void +ia64_validate_fix (fix) + fixS *fix; +{ + switch (fix->fx_r_type) + { + case BFD_RELOC_IA64_FPTR64I: + case BFD_RELOC_IA64_FPTR32MSB: + case BFD_RELOC_IA64_FPTR64LSB: + case BFD_RELOC_IA64_LTOFF_FPTR22: + case BFD_RELOC_IA64_LTOFF_FPTR64I: + if (fix->fx_offset != 0) + as_bad_where (fix->fx_file, fix->fx_line, + "No addend allowed in @fptr() relocation"); + break; + default: + break; + } + + return; +} + +static void +fix_insn (fix, odesc, value) + fixS *fix; + const struct ia64_operand *odesc; + valueT value; +{ + bfd_vma insn[3], t0, t1, control_bits; + const char *err; + char *fixpos; + long slot; + + slot = fix->fx_where & 0x3; + fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot); + + /* bundles are always in little-endian byte order */ + t0 = bfd_getl64 (fixpos); + t1 = bfd_getl64 (fixpos + 8); + control_bits = t0 & 0x1f; + insn[0] = (t0 >> 5) & 0x1ffffffffffLL; + insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18); + insn[2] = (t1 >> 23) & 0x1ffffffffffLL; + + err = (*odesc->insert) (odesc, value, insn + slot); + if (err) + { + as_bad_where (fix->fx_file, fix->fx_line, err); + return; + } + + t0 = control_bits | (insn[0] << 5) | (insn[1] << 46); + t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); + md_number_to_chars (fixpos + 0, t0, 8); + md_number_to_chars (fixpos + 8, t1, 8); + +} + +/* Attempt to simplify or even eliminate a fixup. The return value is + ignored; perhaps it was once meaningful, but now it is historical. + To indicate that a fixup has been eliminated, set FIXP->FX_DONE. + + If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry + (if possible). */ +int +md_apply_fix3 (fix, valuep, seg) + fixS *fix; + valueT *valuep; + segT seg; +{ + char *fixpos; + valueT value = *valuep; + int adjust = 0; + + fixpos = fix->fx_frag->fr_literal + fix->fx_where; + + if (fix->fx_pcrel) + { + switch (fix->fx_r_type) + { + case BFD_RELOC_IA64_DIR32MSB: + fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB; + adjust = 1; + break; + + case BFD_RELOC_IA64_DIR32LSB: + fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB; + adjust = 1; + break; + + case BFD_RELOC_IA64_DIR64MSB: + fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB; + adjust = 1; + break; + + case BFD_RELOC_IA64_DIR64LSB: + fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB; + adjust = 1; + break; + + default: + break; + } + } + if (fix->fx_addsy) + { + switch (fix->fx_r_type) + { + case 0: + as_bad_where (fix->fx_file, fix->fx_line, + "%s must have a constant value", + elf64_ia64_operands[fix->tc_fix_data.opnd].desc); + break; + + default: + break; + } + + /* ??? This is a hack copied from tc-i386.c to make PCREL relocs + work. There should be a better way to handle this. */ + if (adjust) + fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address; + } + else if (fix->tc_fix_data.opnd == IA64_OPND_NIL) + { + if (fix->tc_fix_data.bigendian) + number_to_chars_bigendian (fixpos, value, fix->fx_size); + else + number_to_chars_littleendian (fixpos, value, fix->fx_size); + fix->fx_done = 1; + return 1; + } + else + { + fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value); + fix->fx_done = 1; + return 1; + } + return 1; +} + +/* Generate the BFD reloc to be stuck in the object file from the + fixup used internally in the assembler. */ +arelent* +tc_gen_reloc (sec, fixp) + asection *sec; + fixS *fixp; +{ + arelent *reloc; + + reloc = xmalloc (sizeof (*reloc)); + reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); + *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); + reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; + reloc->addend = fixp->fx_offset; + reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); + + if (!reloc->howto) + { + as_bad_where (fixp->fx_file, fixp->fx_line, + "Cannot represent %s relocation in object file", + bfd_get_reloc_code_name (fixp->fx_r_type)); + } + return reloc; +} + +/* Turn a string in input_line_pointer into a floating point constant + of type type, and store the appropriate bytes in *lit. The number + of LITTLENUMS emitted is stored in *size. An error message is + returned, or NULL on OK. */ + +#define MAX_LITTLENUMS 5 + +char* +md_atof (type, lit, size) + int type; + char *lit; + int *size; +{ + LITTLENUM_TYPE words[MAX_LITTLENUMS]; + LITTLENUM_TYPE *word; + char *t; + int prec; + + switch (type) + { + /* IEEE floats */ + case 'f': + case 'F': + case 's': + case 'S': + prec = 2; + break; + + case 'd': + case 'D': + case 'r': + case 'R': + prec = 4; + break; + + case 'x': + case 'X': + case 'p': + case 'P': + prec = 5; + break; + + default: + *size = 0; + return "Bad call to MD_ATOF()"; + } + t = atof_ieee (input_line_pointer, type, words); + if (t) + input_line_pointer = t; + *size = prec * sizeof (LITTLENUM_TYPE); + + for (word = words + prec - 1; prec--;) + { + md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE)); + lit += sizeof (LITTLENUM_TYPE); + } + return 0; +} + +/* Round up a section's size to the appropriate boundary. */ +valueT +md_section_align (seg, size) + segT seg; + valueT size; +{ + int align = bfd_get_section_alignment (stdoutput, seg); + valueT mask = ((valueT)1 << align) - 1; + + return (size + mask) & ~mask; +} + +/* Handle ia64 specific semantics of the align directive. */ + +int +ia64_md_do_align (n, fill, len, max) + int n; + const char *fill; + int len; + int max; +{ + /* Fill any pending bundle with nops. */ + if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) + ia64_flush_insns (); + + /* When we align code in a text section, emit a bundle of 3 nops instead of + zero bytes. We can only do this if a multiple of 16 bytes was requested. + N is log base 2 of the requested alignment. */ + if (fill == NULL + && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE + && n > 4) + { + /* Use mfi bundle of nops with no stop bits. */ + static const unsigned char be_nop[] + = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c}; + static const unsigned char le_nop[] + = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00}; + + /* Make sure we are on a 16-byte boundary, in case someone has been + putting data into a text section. */ + frag_align (4, 0, 0); + + if (target_big_endian) + frag_align_pattern (n, be_nop, 16, max); + else + frag_align_pattern (n, le_nop, 16, max); + return 1; + } + + return 0; +} diff --git a/gas/config/tc-ia64.h b/gas/config/tc-ia64.h new file mode 100644 index 0000000..db8d7a4 --- /dev/null +++ b/gas/config/tc-ia64.h @@ -0,0 +1,218 @@ +/* tc-ia64.h -- Header file for tc-ia64.c. + Copyright (C) 1998, 1999 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang <davidm@hpl.hp.com> + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include <opcode/ia64.h> +#include <elf/ia64.h> + +#define TC_IA64 + +#define TARGET_FORMAT (OUTPUT_FLAVOR == bfd_target_elf_flavour \ + ? "elf64-ia64-little" \ + : "unknown-format") + +#define TARGET_ARCH bfd_arch_ia64 +#define TARGET_BYTES_BIG_ENDIAN 0 +#define DOUBLESLASH_LINE_COMMENTS /* allow //-style comments */ +#define md_number_to_chars number_to_chars_littleendian +#define TC_HANDLES_FX_DONE + +#define NEED_LITERAL_POOL /* need gp literal pool */ +#define RELOC_REQUIRES_SYMBOL +#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */ +#define NEED_INDEX_OPERATOR /* [ ] is index operator */ + +#define QUOTES_IN_INSN /* allow `string "foo;bar"' */ +#define LEX_AT LEX_NAME /* allow `@' inside name */ +#define LEX_QM LEX_NAME /* allow `?' inside name */ +#define LEX_HASH LEX_END_NAME /* allow `#' ending a name */ + +struct ia64_fix + { + int bigendian; /* byte order at fix location */ + enum ia64_opnd opnd; + }; + +extern void ia64_do_align PARAMS((int n)); +extern void ia64_end_of_source PARAMS((void)); +extern void ia64_start_line PARAMS((void)); +extern int ia64_unrecognized_line PARAMS((int ch)); +extern void ia64_frob_label PARAMS((struct symbol *sym)); +extern void ia64_flush_pending_output PARAMS((void)); +extern int ia64_parse_name (char *name, expressionS *e); +extern int ia64_optimize_expr PARAMS((expressionS *l, operatorT op, + expressionS *r)); +extern void ia64_cons_align PARAMS((int)); +extern void ia64_flush_insns PARAMS((void)); +extern int ia64_fix_adjustable PARAMS((struct fix *fix)); +extern int ia64_force_relocation PARAMS((struct fix *)); +extern void ia64_cons_fix_new PARAMS ((fragS *f, int where, int nbytes, + expressionS *exp)); +extern void ia64_validate_fix PARAMS ((struct fix *fix)); +extern char * ia64_canonicalize_symbol_name PARAMS ((char *)); +extern flagword ia64_elf_section_flags PARAMS ((flagword, int, int)); +extern long ia64_pcrel_from_section PARAMS ((struct fix *fix, segT sec)); +extern int ia64_md_do_align PARAMS ((int, const char *, int, int)); + +#define md_end() ia64_end_of_source () +#define md_start_line_hook() ia64_start_line () +#define tc_unrecognized_line(ch) ia64_unrecognized_line (ch) +#define tc_frob_label(s) ia64_frob_label (s) +#define md_flush_pending_output() ia64_flush_pending_output () +#define md_parse_name(s,e) ia64_parse_name (s, e) +#define tc_canonicalize_symbol_name(s) ia64_canonicalize_symbol_name (s) +#define md_optimize_expr(l,o,r) ia64_optimize_expr (l, o, r) +#define md_cons_align(n) ia64_cons_align (n) +#define TC_FORCE_RELOCATION(f) ia64_force_relocation (f) +#define tc_fix_adjustable(f) ia64_fix_adjustable (f) +#define md_convert_frag(b,s,f) as_fatal ("ia64_convert_frag") +#define md_create_long_jump(p,f,t,fr,s) as_fatal("ia64_create_long_jump") +#define md_create_short_jump(p,f,t,fr,s) \ + as_fatal("ia64_create_short_jump") +#define md_estimate_size_before_relax(f,s) \ + (as_fatal ("ia64_estimate_size_before_relax"), 1) +#define md_elf_section_flags ia64_elf_section_flags +#define TC_FIX_TYPE struct ia64_fix +#define TC_INIT_FIX_DATA(f) { f->tc_fix_data.opnd = 0; } +#define TC_CONS_FIX_NEW(f,o,l,e) ia64_cons_fix_new (f, o, l, e) +#define TC_VALIDATE_FIX(fix,seg,skip) ia64_validate_fix (fix) +#define MD_PCREL_FROM_SECTION(fix,sec) ia64_pcrel_from_section (fix, sec) +#define md_do_align(n,f,l,m,j) if (ia64_md_do_align (n,f,l,m)) goto j + +/* Call md_apply_fix3 with segment instead of md_apply_fix. */ +#define MD_APPLY_FIX3 + +#define WORKING_DOT_WORD /* don't do broken word processing for now */ + +#define ELF_TC_SPECIAL_SECTIONS \ +{ ".sbss", SHT_NOBITS, SHF_ALLOC + SHF_WRITE + SHF_IA_64_SHORT }, \ +{ ".sdata", SHT_PROGBITS, SHF_ALLOC + SHF_WRITE + SHF_IA_64_SHORT }, \ +{ ".IA_64.unwind", SHT_IA_64_UNWIND, SHF_ALLOC }, \ +{ ".IA_64.unwind_info", SHT_PROGBITS, SHF_ALLOC }, + +#define DWARF2_LINE_MIN_INSN_LENGTH 1 /* so slot-multipliers can be 1 */ + +/* This is the information required for unwind records in an ia64 + object file. This is required by GAS and the compiler runtime. */ + +/* These are the starting point masks for the various types of + unwind records. To create a record of type R3 for instance, one + starts by using the value UNW_R3 and or-ing in any other required values. + These values are also unique (in context), so they can be used to identify + the various record types as well. UNW_Bx and some UNW_Px do have the + same value, but Px can only occur in a prologue context, and Bx in + a body context. */ + +#define UNW_R1 0x00 +#define UNW_R2 0x40 +#define UNW_R3 0x60 +#define UNW_P1 0x80 +#define UNW_P2 0xA0 +#define UNW_P3 0xB0 +#define UNW_P4 0xB8 +#define UNW_P5 0xB9 +#define UNW_P6 0xC0 +#define UNW_P7 0xE0 +#define UNW_P8 0xF0 +#define UNW_P9 0xF1 +#define UNW_P10 0xFF +#define UNW_X1 0xF9 +#define UNW_X2 0xFA +#define UNW_X3 0xFB +#define UNW_X4 0xFC +#define UNW_B1 0x80 +#define UNW_B2 0xC0 +#define UNW_B3 0xE0 +#define UNW_B4 0xF0 + +/* These are all the various types of unwind records. */ + +typedef enum +{ + prologue, prologue_gr, body, mem_stack_f, mem_stack_v, psp_gr, psp_sprel, + rp_when, rp_gr, rp_br, rp_psprel, rp_sprel, pfs_when, pfs_gr, pfs_psprel, + pfs_sprel, preds_when, preds_gr, preds_psprel, preds_sprel, + fr_mem, frgr_mem, gr_gr, gr_mem, br_mem, br_gr, spill_base, spill_mask, + unat_when, unat_gr, unat_psprel, unat_sprel, lc_when, lc_gr, lc_psprel, + lc_sprel, fpsr_when, fpsr_gr, fpsr_psprel, fpsr_sprel, + priunat_when_gr, priunat_when_mem, priunat_gr, priunat_psprel, + priunat_sprel, bsp_when, bsp_gr, bsp_psprel, bsp_sprel, bspstore_when, + bspstore_gr, bspstore_psprel, bspstore_sprel, rnat_when, rnat_gr, + rnat_psprel, rnat_sprel, epilogue, label_state, copy_state, + spill_psprel, spill_sprel, spill_reg, spill_psprel_p, spill_sprel_p, + spill_reg_p +} unw_record_type; + + +/* These structures declare the fields that can be used in each of the + 4 record formats, R, P, B and X. */ + +typedef struct unw_r_record +{ + unsigned long rlen; + unsigned short mask; + unsigned short grsave; +} unw_r_record; + +typedef struct unw_p_record +{ + void *imask; + unsigned long t; + unsigned long size; + unsigned long spoff; + unsigned long br; + unsigned long pspoff; + unsigned short gr; + unsigned short rmask; + unsigned short grmask; + unsigned long frmask; + unsigned short brmask; +} unw_p_record; + +typedef struct unw_b_record +{ + unsigned long t; + unsigned long label; + unsigned short ecount; +} unw_b_record; + +typedef struct unw_x_record +{ + unsigned long t; + unsigned long spoff; + unsigned long pspoff; + unsigned short reg; + unsigned short treg; + unsigned short qp; + unsigned short xy; /* Value of the XY field.. */ +} unw_x_record; + +/* This structure is used to determine the specific record type and + its fields. */ +typedef struct unwind_record +{ + unw_record_type type; + union { + unw_r_record r; + unw_p_record p; + unw_b_record b; + unw_x_record x; + } record; +} unwind_record; diff --git a/gas/configure b/gas/configure index 04e8870..1904b6c 100755 --- a/gas/configure +++ b/gas/configure @@ -1659,6 +1659,7 @@ for this_target in $target $canon_targets ; do thumb*) cpu_type=arm endian=little ;; hppa*) cpu_type=hppa ;; i[456]86) cpu_type=i386 ;; + ia64) cpu_type=ia64 ;; m680[012346]0) cpu_type=m68k ;; m68008) cpu_type=m68k ;; m683??) cpu_type=m68k ;; @@ -1797,6 +1798,9 @@ EOF i960-*-vxworks*) fmt=bout ;; i960-*-elf*) fmt=elf ;; + ia64-*-elf*) fmt=elf ;; + ia64-*-linux-gnu*) fmt=elf em=linux ;; + m32r-*-*) fmt=elf bfd_gas=yes ;; m68k-*-vxworks* | m68k-ericsson-ose | m68k-*-sunos*) @@ -1963,6 +1967,7 @@ EOF arm-*) bfd_gas=yes ;; # not yet # i386-aout) bfd_gas=preferred ;; + ia64*-*) bfd_gas=yes ;; mips-*) bfd_gas=yes ;; ns32k-*) bfd_gas=yes ;; ppc-*) bfd_gas=yes ;; diff --git a/gas/configure.in b/gas/configure.in index 01fd0c5..9802bcd 100644 --- a/gas/configure.in +++ b/gas/configure.in @@ -121,6 +121,7 @@ changequote([,])dnl hppa*) cpu_type=hppa ;; changequote(,)dnl i[456]86) cpu_type=i386 ;; + ia64) cpu_type=ia64 ;; m680[012346]0) cpu_type=m68k ;; changequote([,])dnl m68008) cpu_type=m68k ;; @@ -258,6 +259,9 @@ changequote([,])dnl i960-*-vxworks*) fmt=bout ;; i960-*-elf*) fmt=elf ;; + ia64-*-elf*) fmt=elf ;; + ia64-*-linux-gnu*) fmt=elf em=linux ;; + m32r-*-*) fmt=elf bfd_gas=yes ;; m68k-*-vxworks* | m68k-ericsson-ose | m68k-*-sunos*) @@ -418,6 +422,7 @@ changequote([,])dnl arm-*) bfd_gas=yes ;; # not yet # i386-aout) bfd_gas=preferred ;; + ia64*-*) bfd_gas=yes ;; mips-*) bfd_gas=yes ;; ns32k-*) bfd_gas=yes ;; ppc-*) bfd_gas=yes ;; @@ -1744,6 +1744,13 @@ expr (rankarg, resultP) } /* Optimize common cases. */ +#ifdef md_optimize_expr + if (md_optimize_expr (resultP, op_left, &right)) + { + /* skip */; + } + else +#endif if (op_left == O_add && right.X_op == O_constant) { /* X + constant. */ @@ -105,6 +105,8 @@ die horribly; #endif #ifndef LEX_HASH +/* The IA-64 assembler uses # as a suffix designating a symbol. We include + it in the symbol and strip it out in tc_canonicalize_symbol_name. */ #define LEX_HASH 0 #endif diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 5337849..ee01f3b 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,11 @@ +Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com> + David Mosberger <davidm@hpl.hp.com> + Timothy Wall <twall@cygnus.com> + Jim Wilson <wilson@cygnus.com> + + * gas/vtable/vtable.exp: Disable for ia64. + * gas/testsuite/gas/ia64: New testsuite directory. + 2000-04-03 Alan Modra <alan@linuxcare.com.au> * gas/i386/general.s: Check 16-bit immediates, and move call/jump diff --git a/gas/testsuite/gas/ia64/dv-branch.d b/gas/testsuite/gas/ia64/dv-branch.d new file mode 100644 index 0000000..f334d8d --- /dev/null +++ b/gas/testsuite/gas/ia64/dv-branch.d @@ -0,0 +1,15 @@ +# as: -xexplicit +# objdump: -d +# name ia64 dv-branch + +.*: +file format .* + +Disassembly of section \.text: + +0000000000000000 <\.text>: + 0: d0 08 00 10 18 90 \[MIB\] \(p06\) ld8 r1=\[r8\] + 6: 61 10 04 80 03 03 \(p06\) mov b6=r2 + c: 68 00 00 10 \(p06\) br\.call\.sptk\.many b0=b6 + 10: 11 08 00 3c 00 21 \[MIB\] mov r1=r30 + 16: 00 00 00 02 00 03 nop\.i 0x0 + 1c: f0 ff ff 48 \(p06\) br\.cond\.sptk\.few 0x0;; diff --git a/gas/testsuite/gas/ia64/dv-branch.s b/gas/testsuite/gas/ia64/dv-branch.s new file mode 100644 index 0000000..09c5141 --- /dev/null +++ b/gas/testsuite/gas/ia64/dv-branch.s @@ -0,0 +1,16 @@ +// +// Verify DV detection on branch variations +// +.text + .explicit + // example from rth +3: + { .mib +(p6) ld8 gp = [ret0] +(p6) mov b6 = r2 +(p6) br.call.sptk.many b0 = b6 // if taken, clears b6/r2 usage + } + { .mib + mov gp = r30 +(p6) br.sptk.few 3b + } diff --git a/gas/testsuite/gas/ia64/dv-entry-err.l b/gas/testsuite/gas/ia64/dv-entry-err.l new file mode 100644 index 0000000..f7b1f72 --- /dev/null +++ b/gas/testsuite/gas/ia64/dv-entry-err.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*:14: Warning: Use of 'mov' .* WAW dependency 'GR%, % in 1 - 127' \(impliedf\) when entry is at label 'L', specific resource number is 5 +.*:13: Warning: This is the location of the conflicting usage diff --git a/gas/testsuite/gas/ia64/dv-entry-err.s b/gas/testsuite/gas/ia64/dv-entry-err.s new file mode 100644 index 0000000..7eee7ae --- /dev/null +++ b/gas/testsuite/gas/ia64/dv-entry-err.s @@ -0,0 +1,15 @@ +// +// Verify DV detection on multiple paths +// +.text + .explicit +// RAW on r4 is avoided on both paths +// RAW on r5 is avoided on path 0 (from top) but not path 1 (from L) + cmp.eq p1, p2 = r1, r2 + cmp.eq p3, p4 = r3, r0 +(p1) mov r4 = 2 +L: +(p2) mov r4 = 5 +(p3) mov r5 = r7 +(p4) mov r5 = r8 + diff --git a/gas/testsuite/gas/ia64/dv-imply.d b/gas/testsuite/gas/ia64/dv-imply.d new file mode 100644 index 0000000..45ad833 --- /dev/null +++ b/gas/testsuite/gas/ia64/dv-imply.d @@ -0,0 +1,42 @@ +# as: -xexplicit +# objdump: -d +# name ia64 dv-mutex + +.*: +file format .* + +Disassembly of section \.text: + +0000000000000000 <L-0xb0>: + 0: 30 20 08 00 00 21 \[MIB\] \(p01\) mov r4=2 + 6: 00 00 00 02 00 01 nop\.i 0x0 + c: b0 00 00 40 \(p02\) br\.cond\.sptk\.few b0 <L> + 10: 11 20 1c 00 00 21 \[MIB\] mov r4=7 + 16: 00 00 00 02 00 00 nop\.i 0x0 + 1c: 00 00 20 00 rfi;; + 20: 10 20 08 00 00 21 \[MIB\] mov r4=2 + 26: 00 00 00 02 00 01 nop\.i 0x0 + 2c: 90 00 00 40 \(p02\) br\.cond\.sptk\.few b0 <L> + 30: 31 20 1c 00 00 21 \[MIB\] \(p01\) mov r4=7 + 36: 00 00 00 02 00 00 nop\.i 0x0 + 3c: 00 00 20 00 rfi;; + 40: 70 08 06 04 02 78 \[MIB\] \(p03\) cmp\.eq\.unc p1,p2=r1,r2 + 46: 40 10 00 00 c2 01 \(p01\) mov r4=2 + 4c: 70 00 00 40 \(p03\) br\.cond\.sptk\.few b0 <L> + 50: 11 20 1c 00 00 21 \[MIB\] mov r4=7 + 56: 00 00 00 02 00 00 nop\.i 0x0 + 5c: 00 00 20 00 rfi;; + 60: 60 08 06 04 02 38 \[MII\] \(p03\) cmp\.eq\.unc p1,p2=r1,r2 + 66: 30 28 18 88 e8 80 cmp\.eq\.or p3,p4=r5,r6 + 6c: 20 00 00 84 \(p01\) mov r4=2 + 70: 10 00 00 00 01 00 \[MIB\] nop\.m 0x0 + 76: 00 00 00 02 80 01 nop\.i 0x0 + 7c: 40 00 00 40 \(p03\) br\.cond\.sptk\.few b0 <L> + 80: 11 20 1c 00 00 21 \[MIB\] mov r4=7 + 86: 00 00 00 02 00 00 nop\.i 0x0 + 8c: 00 00 20 00 rfi;; + 90: 10 08 16 0c 42 70 \[MIB\] cmp\.ne\.and p1,p2=r5,r6 + 96: 40 10 00 00 c2 01 \(p01\) mov r4=2 + 9c: 20 00 00 40 \(p03\) br\.cond\.sptk\.few b0 <L> + a0: 11 20 1c 00 00 21 \[MIB\] mov r4=7 + a6: 00 00 00 02 00 00 nop\.i 0x0 + ac: 00 00 20 00 rfi;; diff --git a/gas/testsuite/gas/ia64/dv-imply.s b/gas/testsuite/gas/ia64/dv-imply.s new file mode 100644 index 0000000..b12bf7e --- /dev/null +++ b/gas/testsuite/gas/ia64/dv-imply.s @@ -0,0 +1,44 @@ +// +// Test various implies relations +// +.text +// User-supplied hint + .pred.rel.imply p1, p2 +(p1) mov r4 = 2 +(p2) br.cond.sptk L + mov r4 = 7 + rfi + +// Symmetric to previous example + .pred.rel.imply p1, p2 + mov r4 = 2 +(p2) br.cond.sptk L +(p1) mov r4 = 7 + rfi + +// Verify that the implies relationship caused by the unconditional compare +// prevents RAW on r4. +(p3) cmp.eq.unc p1, p2 = r1, r2 // p1,p2 imply p3 +(p1) mov r4 = 2 +(p3) br.cond.sptk L + mov r4 = 7 + rfi + +// An instance of cmp.rel.or should not affect an implies relation. +(p3) cmp.eq.unc p1, p2 = r1, r2 // p1,p2 imply p3 + cmp.eq.or p3, p4 = r5, r6 // doesn't affect implies rel +(p1) mov r4 = 2 +(p3) br.cond.sptk L + mov r4 = 7 + rfi + +// An instance of cmp.rel.and only affects imply targets + .pred.rel.imply p1,p3 + cmp.ne.and p1, p2 = r5, r6 // doesn't affect imply source +(p1) mov r4 = 2 +(p3) br.cond.sptk L + mov r4 = 7 + rfi + +// FIXME -- add tests for and.orcm and or.andcm +L: diff --git a/gas/testsuite/gas/ia64/dv-mutex-err.l b/gas/testsuite/gas/ia64/dv-mutex-err.l new file mode 100644 index 0000000..a6df710 --- /dev/null +++ b/gas/testsuite/gas/ia64/dv-mutex-err.l @@ -0,0 +1,4 @@ +.*: Assembler messages: +.*:9: Warning: Use of 'ld8' .* RAW dependency 'GR%, % in 1 - 127' \(impliedf\), specific resource number is 26 +.*:9: Warning: Only the first path encountering the conflict is reported +.*:8: Warning: This is the location of the conflicting usage diff --git a/gas/testsuite/gas/ia64/dv-mutex-err.s b/gas/testsuite/gas/ia64/dv-mutex-err.s new file mode 100644 index 0000000..e6eaaaa --- /dev/null +++ b/gas/testsuite/gas/ia64/dv-mutex-err.s @@ -0,0 +1,9 @@ +// +// Test mutex relation handling +// +.text + .explicit +start: + cmp.eq p6, p0 = r29, r0 + add r26 = r26, r29 + ld8 r29 = [r26] diff --git a/gas/testsuite/gas/ia64/dv-mutex.d b/gas/testsuite/gas/ia64/dv-mutex.d new file mode 100644 index 0000000..af84da6 --- /dev/null +++ b/gas/testsuite/gas/ia64/dv-mutex.d @@ -0,0 +1,27 @@ +# as: -xexplicit +# objdump: -d +# name ia64 dv-mutex + +.*: +file format .* + +Disassembly of section \.text: + +0000000000000000 <start>: + 0: 20 20 08 00 00 a1 \[MII\] \(p01\) mov r4=2 + 6: 40 28 00 00 c2 81 \(p02\) mov r4=5 + c: 70 00 00 84 \(p03\) mov r4=7 + 10: 11 00 00 00 01 00 \[MIB\] nop\.m 0x0 + 16: 00 00 00 02 00 00 nop\.i 0x0 + 1c: 00 00 20 00 rfi;; + 20: 00 08 04 04 02 78 \[MII\] cmp\.eq p1,p2=r1,r2 + 26: 40 10 00 00 42 81 \(p01\) mov r4=2 + 2c: 40 00 00 84 \(p02\) mov r4=4 + 30: 11 00 00 00 01 00 \[MIB\] nop\.m 0x0 + 36: 00 00 00 02 00 00 nop\.i 0x0 + 3c: 00 00 20 00 rfi;; + 40: 60 08 06 04 02 78 \[MII\] \(p03\) cmp\.eq\.unc p1,p2=r1,r2 + 46: 40 10 00 00 42 81 \(p01\) mov r4=2 + 4c: 40 00 00 84 \(p02\) mov r4=4 + 50: 11 00 00 00 01 00 \[MIB\] nop\.m 0x0 + 56: 00 00 00 02 00 00 nop\.i 0x0 + 5c: 00 00 20 00 rfi;; diff --git a/gas/testsuite/gas/ia64/dv-mutex.s b/gas/testsuite/gas/ia64/dv-mutex.s new file mode 100644 index 0000000..c62ae10 --- /dev/null +++ b/gas/testsuite/gas/ia64/dv-mutex.s @@ -0,0 +1,24 @@ +// +// Test mutex relation handling +// +.text +start: +// user annotation + .pred.rel.mutex p1, p2, p3 +(p1) mov r4 = 2 +(p2) mov r4 = 5 +(p3) mov r4 = 7 + rfi + +// non-predicated compares generate a mutex + cmp.eq p1, p2 = r1, r2 +(p1) mov r4 = 2 +(p2) mov r4 = 4 + rfi + +// unconditional compares generate a mutex +(p3) cmp.eq.unc p1, p2 = r1, r2 +(p1) mov r4 = 2 +(p2) mov r4 = 4 + rfi +L: diff --git a/gas/testsuite/gas/ia64/dv-raw-err.l b/gas/testsuite/gas/ia64/dv-raw-err.l new file mode 100644 index 0000000..9993418 --- /dev/null +++ b/gas/testsuite/gas/ia64/dv-raw-err.l @@ -0,0 +1,267 @@ +.*: Assembler messages: +.*:10: Warning: Use of 'mov\.m' .* RAW dependency 'AR\[BSP\]' \(impliedf\) +.*:9: Warning: This is the location of the conflicting usage +.*:10: Warning: Use of 'mov\.m' .* RAW dependency 'RSE' \(impliedf\) +.*:9: Warning: This is the location of the conflicting usage +.*:15: Warning: Use of 'mov\.m' .* RAW dependency 'AR\[BSPSTORE\]' \(impliedf\) +.*:14: Warning: This is the location of the conflicting usage +.*:15: Warning: Use of 'mov\.m' .* RAW dependency 'RSE' \(impliedf\) +.*:14: Warning: This is the location of the conflicting usage +.*:20: Warning: Use of 'cmpxchg8\.acq' .* RAW dependency 'AR\[CCV\]' \(impliedf\) +.*:19: Warning: This is the location of the conflicting usage +.*:25: Warning: Use of 'mov\.i' .* RAW dependency 'AR\[EC\]' \(impliedf\) +.*:24: Warning: This is the location of the conflicting usage +.*:30: Warning: Use of 'fpcmp\.eq\.s0' .* RAW dependency 'AR\[FPSR\]\.sf0\.controls' \(impliedf\) +.*:29: Warning: This is the location of the conflicting usage +.*:35: Warning: Use of 'fpcmp\.eq\.s1' .* RAW dependency 'AR\[FPSR\]\.sf1\.controls' \(impliedf\) +.*:34: Warning: This is the location of the conflicting usage +.*:40: Warning: Use of 'fpcmp\.eq\.s2' .* RAW dependency 'AR\[FPSR\]\.sf2\.controls' \(impliedf\) +.*:39: Warning: This is the location of the conflicting usage +.*:45: Warning: Use of 'fpcmp\.eq\.s3' .* RAW dependency 'AR\[FPSR\]\.sf3\.controls' \(impliedf\) +.*:44: Warning: This is the location of the conflicting usage +.*:50: Warning: Use of 'fchkf\.s0' .* RAW dependency 'AR\[FPSR\]\.sf0\.flags' \(impliedf\) +.*:49: Warning: This is the location of the conflicting usage +.*:55: Warning: Use of 'fchkf\.s1' .* RAW dependency 'AR\[FPSR\]\.sf1\.flags' \(impliedf\) +.*:54: Warning: This is the location of the conflicting usage +.*:60: Warning: Use of 'fchkf\.s2' .* RAW dependency 'AR\[FPSR\]\.sf2\.flags' \(impliedf\) +.*:59: Warning: This is the location of the conflicting usage +.*:65: Warning: Use of 'fchkf\.s3' .* RAW dependency 'AR\[FPSR\]\.sf3\.flags' \(impliedf\) +.*:64: Warning: This is the location of the conflicting usage +.*:70: Warning: Use of 'fcmp\.eq\.s3' .* RAW dependency 'AR\[FPSR\]\.sf3\.controls' \(impliedf\) +.*:69: Warning: This is the location of the conflicting usage +.*:70: Warning: Use of 'fcmp\.eq\.s3' .* RAW dependency 'AR\[FPSR\]\.traps' \(impliedf\) +.*:69: Warning: This is the location of the conflicting usage +.*:70: Warning: Use of 'fcmp\.eq\.s3' .* RAW dependency 'AR\[FPSR\]\.rv' \(impliedf\) +.*:69: Warning: This is the location of the conflicting usage +.*:70: Warning: Use of 'fcmp\.eq\.s3' .* WAW dependency 'AR\[FPSR\]\.sf3\.flags' \(impliedf\) +.*:69: Warning: This is the location of the conflicting usage +.*:75: Warning: Use of 'mov\.m' .* RAW dependency 'AR\[ITC\]' \(impliedf\) +.*:74: Warning: This is the location of the conflicting usage +.*:80: Warning: Use of 'br\.ia\.sptk' .* RAW dependency 'AR\[K%\], % in 0 - 7' \(impliedf\), specific resource number is 1 +.*:79: Warning: This is the location of the conflicting usage +.*:85: Warning: Use of 'mov\.i' .* RAW dependency 'AR\[LC\]' \(impliedf\) +.*:84: Warning: This is the location of the conflicting usage +.*:90: Warning: Use of 'epc' .* RAW dependency 'AR\[PFS\]' \(impliedf\) +.*:89: Warning: This is the location of the conflicting usage +.*:94: Warning: Use of 'mov\.m' .* RAW dependency 'AR\[RNAT\]' \(impliedf\) +.*:93: Warning: This is the location of the conflicting usage +.*:94: Warning: Use of 'mov\.m' .* RAW dependency 'RSE' \(impliedf\) +.*:93: Warning: This is the location of the conflicting usage +.*:99: Warning: Use of 'mov\.m' .* RAW dependency 'AR\[RSC\]' \(impliedf\) +.*:98: Warning: This is the location of the conflicting usage +.*:104: Warning: Use of 'ld8\.fill' .* RAW dependency 'AR\[UNAT\]{%}, % in 0 - 63' \(impliedf\) +.*:103: Warning: This is the location of the conflicting usage +.*:111: Warning: Use of 'mov' .* RAW dependency 'BR%, % in 0 - 7' \(impliedf\) +.*:110: Warning: This is the location of the conflicting usage +.*:116: Warning: Use of 'fadd' .* RAW dependency 'CFM' \(impliedf\) +.*:115: Warning: This is the location of the conflicting usage +.*:121: Warning: Use of 'mov' .* RAW dependency 'CR\[CMCV\]' \(data\) +.*:120: Warning: This is the location of the conflicting usage +.*:126: Warning: Use of 'ld8\.s' .* RAW dependency 'CR\[DCR\]' \(data\) +.*:125: Warning: This is the location of the conflicting usage +.*:133: Warning: Use of 'thash' .* RAW dependency 'CR\[GPTA\]' \(data\) +.*:132: Warning: This is the location of the conflicting usage +.*:139: Warning: Use of 'itc\.i' .* RAW dependency 'CR\[IFA\]' \(implied\) +.*:138: Warning: This is the location of the conflicting usage +.*:144: Warning: Use of 'mov' .* RAW dependency 'CR\[IFS\]' \(data\) +.*:143: Warning: This is the location of the conflicting usage +.*:149: Warning: Use of 'mov' .* RAW dependency 'CR\[IHA\]' \(data\) +.*:148: Warning: This is the location of the conflicting usage +.*:154: Warning: Use of 'mov' .* RAW dependency 'CR\[IIM\]' \(data\) +.*:153: Warning: This is the location of the conflicting usage +.*:159: Warning: Use of 'rfi' .* RAW dependency 'CR\[IIP\]' \(implied\) +.*:158: Warning: This is the location of the conflicting usage +.*:164: Warning: Use of 'mov' .* RAW dependency 'CR\[IIPA\]' \(data\) +.*:163: Warning: This is the location of the conflicting usage +.*:169: Warning: Use of 'rfi' .* RAW dependency 'CR\[IPSR\]' \(implied\) +.*:168: Warning: This is the location of the conflicting usage +.*:174: Warning: Use of 'mov' .* RAW dependency 'CR\[IRR%\], % in 0 - 3' \(data\), specific resource number is 68 +.*:173: Warning: This is the location of the conflicting usage +.*:179: Warning: Use of 'mov' .* RAW dependency 'CR\[ISR\]' \(data\) +.*:178: Warning: This is the location of the conflicting usage +.*:184: Warning: Use of 'itc\.d' .* RAW dependency 'CR\[ITIR\]' \(implied\) +.*:183: Warning: This is the location of the conflicting usage +.*:189: Warning: Use of 'mov' .* RAW dependency 'CR\[ITM\]' \(data\) +.*:188: Warning: This is the location of the conflicting usage +.*:194: Warning: Use of 'mov' .* RAW dependency 'CR\[ITV\]' \(data\) +.*:193: Warning: This is the location of the conflicting usage +.*:201: Warning: Use of 'mov' .* RAW dependency 'CR\[IVA\]' \(instr\) +.*:200: Warning: This is the location of the conflicting usage +.*:206: Warning: Use of 'mov' .* RAW dependency 'CR\[LID\]' \(other\) +.*:205: Warning: This is the location of the conflicting usage +.*:212: Warning: Use of 'mov' .* RAW dependency 'CR\[LRR%\], % in 0 - 1' \(data\), specific resource number is 80 +.*:211: Warning: This is the location of the conflicting usage +.*:217: Warning: Use of 'mov' .* RAW dependency 'CR\[PMV\]' \(data\) +.*:216: Warning: This is the location of the conflicting usage +.*:222: Warning: Use of 'thash' .* RAW dependency 'CR\[PTA\]' \(data\) +.*:221: Warning: This is the location of the conflicting usage +.*:227: Warning: Use of 'mov' .* RAW dependency 'CR\[TPR\]' \(data\) +.*:226: Warning: This is the location of the conflicting usage +.*:231: Warning: Use of 'mov' .* RAW dependency 'CR\[TPR\]' \(other\) +.*:230: Warning: This is the location of the conflicting usage +.*:237: Warning: Use of 'mov' .* RAW dependency 'DBR#' \(impliedf\) +.*:236: Warning: This is the location of the conflicting usage +.*:241: Warning: Use of 'probe\.r' .* RAW dependency 'DBR#' \(data\) +.*:240: Warning: This is the location of the conflicting usage +.*:247: Warning: Use of 'fc' .* RAW dependency 'DTC' \(data\) +.*:246: Warning: This is the location of the conflicting usage +.*:251: Warning: Use of 'ptc\.e' .* RAW dependency 'DTC' \(impliedf\) +.*:250: Warning: This is the location of the conflicting usage +.*:251: Warning: Use of 'ptc\.e' .* WAW dependency 'DTC' \(impliedf\) +.*:250: Warning: This is the location of the conflicting usage +.*:251: Warning: Use of 'ptc\.e' .* WAW dependency 'ITC' \(impliedf\) +.*:250: Warning: This is the location of the conflicting usage +.*:262: Warning: Use of 'tak' .* RAW dependency 'DTC' \(data\) +.*:261: Warning: This is the location of the conflicting usage +.*:262: Warning: Use of 'tak' .* RAW dependency 'DTR' \(data\) +.*:261: Warning: This is the location of the conflicting usage +.*:266: Warning: Use of 'tpa' .* RAW dependency 'DTC' \(data\) +.*:265: Warning: This is the location of the conflicting usage +.*:266: Warning: Use of 'tpa' .* RAW dependency 'DTR' \(data\) +.*:265: Warning: This is the location of the conflicting usage +.*:275: Warning: Use of 'mov' .* RAW dependency 'FR%, % in 2 - 127' \(impliedf\), specific resource number is 4 +.*:274: Warning: This is the location of the conflicting usage +.*:283: Warning: Use of 'mov' .* RAW dependency 'GR%, % in 1 - 127' \(impliedf\), specific resource number is 3 +.*:282: Warning: This is the location of the conflicting usage +.*:288: Warning: Use of 'mov' .* RAW dependency 'IBR#' \(impliedf\) +.*:287: Warning: This is the location of the conflicting usage +.*:293: Warning: Use of 'mov' .* RAW dependency 'InService\*' \(data\) +.*:292: Warning: This is the location of the conflicting usage +.*:293: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\) +.*:292: Warning: This is the location of the conflicting usage +.*:297: Warning: Use of 'mov' .* RAW dependency 'InService\*' \(impliedf\) +.*:296: Warning: This is the location of the conflicting usage +.*:297: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 71 +.*:296: Warning: This is the location of the conflicting usage +.*:297: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 70 +.*:296: Warning: This is the location of the conflicting usage +.*:297: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 69 +.*:296: Warning: This is the location of the conflicting usage +.*:297: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 68 +.*:296: Warning: This is the location of the conflicting usage +.*:297: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\) +.*:296: Warning: This is the location of the conflicting usage +.*:299: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\) +.*:297: Warning: This is the location of the conflicting usage +.*:299: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\) +.*:296: Warning: This is the location of the conflicting usage +.*:300: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\) +.*:297: Warning: This is the location of the conflicting usage +.*:300: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\) +.*:296: Warning: This is the location of the conflicting usage +.*:300: Warning: Use of 'mov' .* RAW dependency 'InService\*' \(impliedf\) +.*:299: Warning: This is the location of the conflicting usage +.*:300: Warning: Use of 'mov' .* WAW dependency 'CR\[EOI\]' \(other\) +.*:299: Warning: This is the location of the conflicting usage +.*:300: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\) +.*:299: Warning: This is the location of the conflicting usage +.*:305: Warning: Use of 'epc' .* RAW dependency 'ITC' \(instr\) +.*:304: Warning: This is the location of the conflicting usage +.*:314: Warning: Use of 'epc' .* RAW dependency 'ITC' \(instr\) +.*:313: Warning: This is the location of the conflicting usage +.*:314: Warning: Use of 'epc' .* RAW dependency 'ITR' \(instr\) +.*:313: Warning: This is the location of the conflicting usage +.*:321: Warning: Use of 'probe\.r' .* RAW dependency 'PKR#' \(data\) +.*:320: Warning: This is the location of the conflicting usage +.*:325: Warning: Use of 'mov' .* RAW dependency 'PKR#' \(data\) +.*:324: Warning: This is the location of the conflicting usage +.*:325: Warning: Use of 'mov' .* RAW dependency 'PKR#' \(impliedf\) +.*:324: Warning: This is the location of the conflicting usage +.*:331: Warning: Use of 'mov' .* RAW dependency 'PMC#' \(impliedf\) +.*:330: Warning: This is the location of the conflicting usage +.*:335: Warning: Use of 'mov' .* RAW dependency 'PMC#' \(other\) +.*:334: Warning: This is the location of the conflicting usage +.*:341: Warning: Use of 'mov' .* RAW dependency 'PMD#' \(impliedf\) +.*:340: Warning: This is the location of the conflicting usage +.*:346: Warning: Use of 'add' .* RAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 1 +.*:345: Warning: This is the location of the conflicting usage +.*:349: Warning: Use of 'add' .* RAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 2 +.*:348: Warning: This is the location of the conflicting usage +.*:352: Warning: Use of 'br\.cond\.sptk' .* RAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 5 +.*:351: Warning: This is the location of the conflicting usage +.*:360: Warning: Use of 'add' .* RAW dependency 'CFM' \(impliedf\) +.*:359: Warning: This is the location of the conflicting usage +.*:360: Warning: Use of 'add' .* RAW dependency 'PR63' \(impliedf\) +.*:359: Warning: This is the location of the conflicting usage +.*:363: Warning: Use of 'add' .* RAW dependency 'PR63' \(impliedf\) +.*:362: Warning: This is the location of the conflicting usage +.*:371: Warning: Use of 'ld8' .* RAW dependency 'PSR\.ac' \(implied\) +.*:370: Warning: This is the location of the conflicting usage +.*:376: Warning: Use of 'ld8' .* RAW dependency 'PSR\.be' \(implied\) +.*:375: Warning: This is the location of the conflicting usage +.*:389: Warning: Use of 'st8' .* RAW dependency 'PSR\.cpl' \(implied\) +.*:388: Warning: This is the location of the conflicting usage +.*:392: Warning: Use of 'mov\.m' .* RAW dependency 'PSR\.cpl' \(implied\) +.*:391: Warning: This is the location of the conflicting usage +.*:395: Warning: Use of 'mov\.m' .* RAW dependency 'PSR\.cpl' \(implied\) +.*:394: Warning: This is the location of the conflicting usage +.*:398: Warning: Use of 'mov\.m' .* RAW dependency 'PSR\.cpl' \(implied\) +.*:397: Warning: This is the location of the conflicting usage +.*:401: Warning: Use of 'mov\.m' .* RAW dependency 'PSR\.cpl' \(implied\) +.*:400: Warning: This is the location of the conflicting usage +.*:404: Warning: Use of 'mov' .* RAW dependency 'PSR\.cpl' \(implied\) +.*:403: Warning: This is the location of the conflicting usage +.*:413: Warning: Use of 'mov' .* RAW dependency 'PSR\.cpl' \(implied\) +.*:412: Warning: This is the location of the conflicting usage +.*:416: Warning: Use of 'mov' .* RAW dependency 'PSR\.cpl' \(implied\) +.*:415: Warning: This is the location of the conflicting usage +.*:422: Warning: Use of 'ld8' .* RAW dependency 'PSR\.ac' \(data\) +.*:421: Warning: This is the location of the conflicting usage +.*:422: Warning: Use of 'ld8' .* RAW dependency 'PSR\.be' \(data\) +.*:421: Warning: This is the location of the conflicting usage +.*:422: Warning: Use of 'ld8' .* RAW dependency 'PSR\.db' \(data\) +.*:421: Warning: This is the location of the conflicting usage +.*:422: Warning: Use of 'ld8' .* RAW dependency 'PSR\.dt' \(data\) +.*:421: Warning: This is the location of the conflicting usage +.*:422: Warning: Use of 'ld8' .* RAW dependency 'PSR\.pk' \(data\) +.*:421: Warning: This is the location of the conflicting usage +.*:430: Warning: Use of 'mov' .* RAW dependency 'PSR\.dfh' \(data\) +.*:429: Warning: This is the location of the conflicting usage +.*:430: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfh' \(impliedf\) +.*:429: Warning: This is the location of the conflicting usage +.*:436: Warning: Use of 'mov' .* RAW dependency 'PSR\.dfl' \(data\) +.*:435: Warning: This is the location of the conflicting usage +.*:436: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfl' \(impliedf\) +.*:435: Warning: This is the location of the conflicting usage +.*:442: Warning: Use of 'mov' .* RAW dependency 'PSR\.di' \(impliedf\) +.*:441: Warning: This is the location of the conflicting usage +.*:447: Warning: Use of 'ld8' .* RAW dependency 'PSR\.dt' \(data\) +.*:446: Warning: This is the location of the conflicting usage +.*:453: Warning: Use of 'mov' .* RAW dependency 'PSR\.i' \(impliedf\) +.*:452: Warning: This is the location of the conflicting usage +.*:459: Warning: Use of 'mov' .* RAW dependency 'PSR\.ic' \(impliedf\) +.*:458: Warning: This is the location of the conflicting usage +.*:463: Warning: Use of 'mov' .* RAW dependency 'PSR\.ic' \(data\) +.*:462: Warning: This is the location of the conflicting usage +.*:476: Warning: Use of 'br\.ret\.sptk' .* RAW dependency 'PSR\.lp' \(data\) +.*:475: Warning: This is the location of the conflicting usage +.*:476: Warning: Use of 'br\.ret\.sptk' .* RAW dependency 'PSR\.tb' \(data\) +.*:475: Warning: This is the location of the conflicting usage +.*:482: Warning: Use of 'mov' .* RAW dependency 'PSR\.mfh' \(impliedf\) +.*:481: Warning: This is the location of the conflicting usage +.*:487: Warning: Use of 'mov' .* RAW dependency 'PSR\.mfl' \(impliedf\) +.*:486: Warning: This is the location of the conflicting usage +.*:492: Warning: Use of 'ld8' .* RAW dependency 'PSR\.pk' \(data\) +.*:491: Warning: This is the location of the conflicting usage +.*:495: Warning: Use of 'mov' .* RAW dependency 'PSR\.pk' \(impliedf\) +.*:494: Warning: This is the location of the conflicting usage +.*:500: Warning: Use of 'mov' .* RAW dependency 'PSR\.pp' \(impliedf\) +.*:499: Warning: This is the location of the conflicting usage +.*:506: Warning: Use of 'flushrs' .* RAW dependency 'PSR\.rt' \(data\) +.*:505: Warning: This is the location of the conflicting usage +.*:512: Warning: Use of 'mov\.m' .* RAW dependency 'PSR\.si' \(data\) +.*:511: Warning: This is the location of the conflicting usage +.*:520: Warning: Use of 'mov' .* RAW dependency 'PSR\.sp' \(data\) +.*:519: Warning: This is the location of the conflicting usage +.*:523: Warning: Use of 'rum' .* RAW dependency 'PSR\.sp' \(data\) +.*:519: Warning: This is the location of the conflicting usage +.*:523: Warning: Use of 'rum' .* RAW dependency 'PSR\.sp' \(data\) +.*:522: Warning: This is the location of the conflicting usage +.*:532: Warning: Use of 'chk\.s' .* RAW dependency 'PSR\.tb' \(data\) +.*:531: Warning: This is the location of the conflicting usage +.*:537: Warning: Use of 'mov' .* RAW dependency 'PSR\.up' \(impliedf\) +.*:536: Warning: This is the location of the conflicting usage +.*:543: Warning: Use of 'ld8' .* RAW dependency 'RR#' \(data\) +.*:542: Warning: This is the location of the conflicting usage +.*:546: Warning: Use of 'mov' .* RAW dependency 'RR#' \(impliedf\) +.*:545: Warning: This is the location of the conflicting usage diff --git a/gas/testsuite/gas/ia64/dv-raw-err.s b/gas/testsuite/gas/ia64/dv-raw-err.s new file mode 100644 index 0000000..fde8a69 --- /dev/null +++ b/gas/testsuite/gas/ia64/dv-raw-err.s @@ -0,0 +1,549 @@ +// +// Detect RAW violations. Cases taken from DV tables. +// This test is by no means complete but tries to hit the things that are +// likely to be missed. +// +.text + .explicit +// AR[BSP] + mov ar.bspstore = r1 + mov r0 = ar.bsp + ;; + +// AR[BSPSTORE] + mov ar.bspstore = r2 + mov r3 = ar.bspstore + ;; + +// AR[CCV] + mov ar.ccv = r4 + cmpxchg8.acq r5 = [r6],r7,ar.ccv + ;; + +// AR[EC] + br.wtop.sptk L + mov r8 = ar.ec + ;; + +// AR[FPSR].sf0.controls + fsetc.s0 0x7f, 0x0f + fpcmp.eq.s0 f2 = f3, f4 + ;; + +// AR[FPSR].sf1.controls + fsetc.s1 0x7f, 0x0f + fpcmp.eq.s1 f2 = f3, f4 + ;; + +// AR[FPSR].sf2.controls + fsetc.s2 0x7f, 0x0f + fpcmp.eq.s2 f2 = f3, f4 + ;; + +// AR[FPSR].sf3.controls + fsetc.s3 0x7f, 0x0f + fpcmp.eq.s3 f2 = f3, f4 + ;; + +// AR[FPSR].sf0.flags + fpcmp.eq.s0 f2 = f3, f4 + fchkf.s0 L + ;; + +// AR[FPSR].sf1.flags + fpcmp.eq.s1 f2 = f3, f4 + fchkf.s1 L + ;; + +// AR[FPSR].sf2.flags + fpcmp.eq.s2 f2 = f3, f4 + fchkf.s2 L + ;; + +// AR[FPSR].sf3.flags + fpcmp.eq.s3 f2 = f3, f4 + fchkf.s3 L + ;; + +// AR[FPSR].traps/rv + mov ar.fpsr = r0 + fcmp.eq.s3 p1, p2 = f5, f6 + ;; + +// AR[ITC] + mov ar.itc = r1 + mov r2 = ar.itc + ;; + +// AR[K] + mov ar.k1 = r3 + br.ia.sptk b0 + ;; + +// AR[LC] + br.cloop.sptk L + mov r4 = ar.lc + ;; + +// AR[PFS] + mov ar.pfs = r5 + epc + +// AR[RNAT] + mov ar.bspstore = r8 + mov r9 = ar.rnat + ;; + +// AR[RSC] + mov ar.rsc = r10 + mov r11 = ar.rnat + ;; + +// AR[UNAT] + mov ar.unat = r12 + ld8.fill r13 = [r14] + ;; + +// AR% + +// BR% + mov b0 = r0 + mov r0 = b0 + ;; + +// CFM + br.wtop.sptk L + fadd f0 = f1, f32 // read from rotating register region + ;; + +// CR[CMCV] + mov cr.cmcv = r1 + mov r2 = cr.cmcv + ;; + +// CR[DCR] + mov cr.dcr = r3 + ld8.s r4 = [r5] + ;; + +// CR[EOI] + +// CR[GPTA] + mov cr.gpta = r6 + thash r7 = r8 + ;; + srlz.d + +// CR[IFA] + mov cr.ifa = r9 + itc.i r10 + ;; + +// CR[IFS] + mov cr.ifs = r11 + mov r12 = cr.ifs + ;; + +// CR[IHA] + mov cr.iha = r13 + mov r14 = cr.iha + ;; + +// CR[IIM] + mov cr.iim = r15 + mov r16 = cr.iim + ;; + +// CR[IIP] + mov cr.iip = r17 + rfi + ;; + +// CR[IIPA] + mov cr.iipa = r19 + mov r20 = cr.iipa + ;; + +// CR[IPSR] + mov cr.ipsr = r21 + rfi + ;; + +// CR[IRR%] + mov r22 = cr.ivr + mov r23 = cr.irr0 + ;; + +// CR[ISR] + mov cr.isr = r24 + mov r25 = cr.isr + ;; + +// CR[ITIR] + mov cr.itir = r26 + itc.d r27 + ;; + +// CR[ITM] + mov cr.itm = r28 + mov r29 = cr.itm + ;; + +// CR[ITV] + mov cr.itv = r0 + mov r1 = cr.itv + ;; + +// CR[IVR] (all writes are implicit in other resource usage) + +// CR[IVA] + mov cr.iva = r0 + mov r1 = cr.iva + ;; + +// CR[LID] + mov cr.lid = r0 + mov r1 = cr.lid + ;; + srlz.d + +// CR[LRR%] + mov cr.lrr0 = r0 + mov r1 = cr.lrr0 + ;; + +// CR[PMV] + mov cr.pmv = r0 + mov r1 = cr.pmv + ;; + +// CR[PTA] + mov cr.pta = r0 + thash r1 = r2 + ;; + +// CR[TPR] + mov cr.tpr = r0 + mov r1 = cr.ivr // data + ;; + srlz.d + mov cr.tpr = r2 + mov psr.l = r3 // other + ;; + srlz.d + +// DBR# + mov dbr[r0] = r1 + mov r2 = dbr[r3] + ;; + srlz.d + mov dbr[r4] = r5 + probe.r r6 = r7, r8 + ;; + srlz.d + +// DTC + ptc.e r0 + fc r1 + ;; + srlz.d + itr.i itr[r2] = r3 + ptc.e r4 + ;; + +// DTC_LIMIT/ITC_LIMIT + ptc.g r0, r1 // NOTE: GAS automatically emits stops after + ptc.ga r2, r3 // ptc.g/ptc.ga, so this conflict is no + ;; // longer possible in GAS-generated assembly + srlz.d + +// DTR + itr.d dtr[r0] = r1 + tak r2 = r3 + ;; + srlz.d + ptr.d r4, r5 + tpa r6 = r7 + ;; + srlz.d + +// FR% + ldfs.c.clr f2 = [r1] + mov f3 = f2 // no DV here + ;; + mov f4 = f5 + mov f6 = f4 + ;; + +// GR% + ld8.c.clr r0 = [r1] // no DV here + mov r2 = r0 + ;; + mov r3 = r4 + mov r5 = r3 + ;; + +// IBR# + mov ibr[r0] = r1 + mov r2 = ibr[r3] + ;; + +// InService + mov cr.eoi = r0 + mov r1 = cr.ivr + ;; + srlz.d + mov r2 = cr.ivr + mov r3 = cr.ivr // several DVs + ;; + mov cr.eoi = r4 + mov cr.eoi = r5 + ;; + +// ITC + ptc.e r0 + epc + ;; + srlz.i + ;; + +// ITC_LIMIT (see DTC_LIMIT) + +// ITR + itr.i itr[r0] = r1 + epc + ;; + srlz.i + ;; + +// PKR# + mov pkr[r0] = r1 + probe.r r2 = r3, r4 + ;; + srlz.d + mov pkr[r5] = r6 + mov r7 = pkr[r8] + ;; + srlz.d + +// PMC# + mov pmc[r0] = r1 + mov r2 = pmc[r3] + ;; + srlz.d + mov pmc[r4] = r5 + mov r6 = pmd[r7] + ;; + srlz.d + +// PMD# + mov pmd[r0] = r1 + mov r2 = pmd[r3] + ;; + +// PR% + cmp.eq p1, p2 = r0, r1 // pr-writer/pr-reader-nobr-nomovpr +(p1) add r2 = r3, r4 + ;; + mov pr = r5, 0xffff // mov-to-pr-allreg/pr-reader-nobr-nomovpr +(p2) add r6 = r7, r8 + ;; + fcmp.eq p5, p6 = f2, f3 // pr-writer-fp/pr-reader-br +(p5) br.cond.sptk b0 + ;; + cmp.eq p7, p8 = r11, r12 +(p7) br.cond.sptk b1 // no DV here + ;; + +// PR63 + br.wtop.sptk L +(p63) add r0 = r1, r2 + ;; + fcmp.eq p62, p63 = f2, f3 +(p63) add r3 = r4, r5 + ;; + cmp.eq p62, p63 = r6, r7 // no DV here +(p63) br.cond.sptk b0 + ;; + +// PSR.ac + rum (1<<3) + ld8 r0 = [r1] + ;; + +// PSR.be + rum (1<<1) + ld8 r0 = [r1] + ;; + +// PSR.bn + bsw.0 + mov r0 = r15 // no DV here, since gr < 16 + ;; + bsw.1 // GAS automatically emits a stop after bsw.n + mov r1 = r16 // so this conflict is avoided + ;; + +// PSR.cpl + epc + st8 [r0] = r1 + ;; + epc + mov r2 = ar.itc + ;; + epc + mov ar.itc = r3 + ;; + epc + mov ar.rsc = r4 + ;; + epc + mov ar.k0 = r5 + ;; + epc + mov r6 = pmd[r7] + ;; + epc + mov ar.bsp = r8 // no DV here + ;; + epc + mov r9 = ar.bsp // no DV here + ;; + epc + mov cr.ifa = r10 // any mov-to/from-cr is a DV + ;; + epc + mov r11 = cr.eoi // any mov-to/from-cr is a DV + ;; + +// PSR.da (rfi is the only writer) +// PSR.db (also ac,be,dt,pk) + mov psr.l = r0 + ld8 r1 = [r2] + ;; + srlz.d + +// PSR.dd (rfi is the only writer) + +// PSR.dfh + mov psr.l = r0 + mov f64 = f65 + ;; + srlz.d + +// PSR.dfl + mov psr.l = r0 + mov f3 = f4 + ;; + srlz.d + +// PSR.di + rsm (1<<22) + mov r0 = psr + ;; + +// PSR.dt + rsm (1<<17) + ld8 r0 = [r1] + ;; + +// PSR.ed (rfi is the only writer) +// PSR.i + ssm (1<<14) + mov r0 = psr + ;; + +// PSR.ia (no DV semantics) +// PSR.ic + ssm (1<<13) + mov r0 = psr + ;; + srlz.d + rsm (1<<13) + mov r1 = cr.itir + ;; + srlz.d + rsm (1<<13) + mov r1 = cr.irr0 // no DV here + ;; + srlz.d + +// PSR.id (rfi is the only writer) +// PSR.is (br.ia and rfi are the only writers) +// PSR.it (rfi is the only writer) +// PSR.lp + mov psr.l = r0 + br.ret.sptk b0 + ;; + +// PSR.mc (rfi is the only writer) +// PSR.mfh + mov f32 = f33 + mov r0 = psr + ;; + +// PSR.mfl + mov f2 = f3 + mov r0 = psr + ;; + +// PSR.pk + rsm (1<<15) + ld8 r0 = [r1] + ;; + rsm (1<<15) + mov r2 = psr + ;; + +// PSR.pp + rsm (1<<21) + mov r0 = psr + ;; + +// PSR.ri (no DV semantics) +// PSR.rt + mov psr.l = r0 + flushrs + ;; + srlz.d + +// PSR.si + rsm (1<<23) + mov r0 = ar.itc + ;; + ssm (1<<23) + mov r1 = ar.ec // no DV here + ;; + +// PSR.sp + ssm (1<<20) + mov r0 = pmd[r1] + ;; + ssm (1<<20) + rum 0xff + ;; + ssm (1<<20) + mov r0 = rr[r1] + ;; + +// PSR.ss (rfi is the only writer) +// PSR.tb + mov psr.l = r0 + chk.s r0, L + ;; + +// PSR.up + rsm (1<<2) + mov r0 = psr.um + ;; + srlz.d + +// RR# + mov rr[r0] = r1 + ld8 r2 = [r0] // data + ;; + mov rr[r4] = r5 + mov r6 = rr[r7] // impliedf + ;; +// RSE +L: diff --git a/gas/testsuite/gas/ia64/dv-safe.d b/gas/testsuite/gas/ia64/dv-safe.d new file mode 100644 index 0000000..32254f2 --- /dev/null +++ b/gas/testsuite/gas/ia64/dv-safe.d @@ -0,0 +1,21 @@ +# as: -xexplicit +# objdump: -d +# name ia64 dv-safe + +.*: +file format .* + +Disassembly of section \.text: + +0000000000000000 <start>: + 0: 02 08 04 04 02 38 \[MII\] cmp\.eq p1,p2=r1,r2 + 6: 30 18 10 08 70 00 cmp\.eq p3,p4=r3,r4;; + c: 00 00 04 00 nop\.i 0x0 + 10: 10 00 00 00 01 00 \[MIB\] nop\.m 0x0 + 16: 00 00 00 02 80 21 nop\.i 0x0 + 1c: 30 00 00 50 \(p03\) br\.call\.sptk\.few b1=40 <L> + 20: 20 20 08 00 00 a1 \[MII\] \(p01\) mov r4=2 + 26: 40 28 00 00 c2 a1 \(p02\) mov r4=5 + 2c: 00 30 00 84 \(p03\) mov r5=r6 + 30: 81 28 00 0e 00 21 \[MII\] \(p04\) mov r5=r7 + 36: 00 00 00 02 00 00 nop\.i 0x0 + 3c: 00 00 04 00 nop\.i 0x0;; diff --git a/gas/testsuite/gas/ia64/dv-safe.s b/gas/testsuite/gas/ia64/dv-safe.s new file mode 100644 index 0000000..5d92e63 --- /dev/null +++ b/gas/testsuite/gas/ia64/dv-safe.s @@ -0,0 +1,19 @@ +// +// Test predicate safety across calls +// +.text +start: +// user annotation + .pred.safe_across_calls p1-p4 + .pred.safe_across_calls p1,p2,p3,p4 + .pred.safe_across_calls p1-p2,p3-p4 + .pred.safe_across_calls p1-p3,p4 + cmp.eq p1, p2 = r1, r2 + cmp.eq p3, p4 = r3, r4 ;; + +(p3) br.call.sptk b1 = L +(p1) mov r4 = 2 +(p2) mov r4 = 5 +(p3) mov r5 = r6 +(p4) mov r5 = r7 +L: diff --git a/gas/testsuite/gas/ia64/dv-srlz.d b/gas/testsuite/gas/ia64/dv-srlz.d new file mode 100644 index 0000000..c332a47 --- /dev/null +++ b/gas/testsuite/gas/ia64/dv-srlz.d @@ -0,0 +1,24 @@ +# as: -xauto +# objdump: -d +# name ia64 dv-srlz + +.*: +file format .* + +Disassembly of section \.text: + +0000000000000000 <start>: + 0: 0a 00 00 02 34 04 \[MMI\] ptc\.e r1;; + 6: 00 00 00 60 00 00 srlz\.d + c: 00 00 04 00 nop\.i 0x0 + 10: 11 00 00 00 18 10 \[MIB\] ld8 r0=\[r0\] + 16: 00 00 00 02 00 00 nop\.i 0x0 + 1c: 00 00 20 00 rfi;; + 20: 0b 00 00 02 34 04 \[MMI\] ptc\.e r1;; + 26: 00 00 00 62 00 00 srlz\.i + 2c: 00 00 04 00 nop\.i 0x0;; + 30: 13 00 00 00 01 00 \[MBB\] nop\.m 0x0 + 36: 00 00 00 20 00 00 epc + 3c: 00 00 00 20 nop\.b 0x0;; + 40: 11 00 00 00 01 00 \[MIB\] nop\.m 0x0 + 46: 00 00 00 02 00 00 nop\.i 0x0 + 4c: 00 00 20 00 rfi;; diff --git a/gas/testsuite/gas/ia64/dv-srlz.s b/gas/testsuite/gas/ia64/dv-srlz.s new file mode 100644 index 0000000..273e51b --- /dev/null +++ b/gas/testsuite/gas/ia64/dv-srlz.s @@ -0,0 +1,13 @@ +// +// Auto-insertion of instruction and data serialization +// +.text +start: +// Requires data serialization + ptc.e r1 + ld8 r1 = [r2] + rfi +// Requires instruction serialization + ptc.e r1 + epc + rfi diff --git a/gas/testsuite/gas/ia64/dv-war-err.l b/gas/testsuite/gas/ia64/dv-war-err.l new file mode 100644 index 0000000..0f186c0 --- /dev/null +++ b/gas/testsuite/gas/ia64/dv-war-err.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*:8: Warning: Use of 'br.wtop.sptk' .* WAR dependency 'PR63' \(impliedf\) +.*:7: Warning: This is the location of the conflicting usage diff --git a/gas/testsuite/gas/ia64/dv-war-err.s b/gas/testsuite/gas/ia64/dv-war-err.s new file mode 100644 index 0000000..a226e96 --- /dev/null +++ b/gas/testsuite/gas/ia64/dv-war-err.s @@ -0,0 +1,9 @@ +// +// Detect WAR violations. Cases taken from DV tables. +// +.text + .explicit +// PR63 +(p63) br.cond.sptk b0 + br.wtop.sptk L +L: diff --git a/gas/testsuite/gas/ia64/dv-waw-err.l b/gas/testsuite/gas/ia64/dv-waw-err.l new file mode 100644 index 0000000..e446757 --- /dev/null +++ b/gas/testsuite/gas/ia64/dv-waw-err.l @@ -0,0 +1,353 @@ +.*: Assembler messages: +.*:8: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[BSP\]' \(impliedf\) +.*:7: Warning: This is the location of the conflicting usage +.*:12: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[BSP\]' \(impliedf\) +.*:11: Warning: This is the location of the conflicting usage +.*:12: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[BSPSTORE\]' \(impliedf\) +.*:11: Warning: This is the location of the conflicting usage +.*:12: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[RNAT\]' \(impliedf\) +.*:11: Warning: This is the location of the conflicting usage +.*:12: Warning: Use of 'mov\.m' .* RAW dependency 'RSE' \(impliedf\) +.*:11: Warning: This is the location of the conflicting usage +.*:12: Warning: Use of 'mov\.m' .* WAW dependency 'RSE' \(impliedf\) +.*:11: Warning: This is the location of the conflicting usage +.*:17: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[CCV\]' \(impliedf\) +.*:16: Warning: This is the location of the conflicting usage +.*:22: Warning: Use of 'mov\.i' .* WAW dependency 'AR\[EC\]' \(impliedf\) +.*:21: Warning: This is the location of the conflicting usage +.*:27: Warning: Use of 'fsetc\.s0' .* RAW dependency 'AR\[FPSR\]\.sf0\.controls' \(impliedf\) +.*:26: Warning: This is the location of the conflicting usage +.*:27: Warning: Use of 'fsetc\.s0' .* WAW dependency 'AR\[FPSR\]\.sf0\.controls' \(impliedf\) +.*:26: Warning: This is the location of the conflicting usage +.*:32: Warning: Use of 'fsetc\.s1' .* RAW dependency 'AR\[FPSR\]\.sf0\.controls' \(impliedf\) +.*:31: Warning: This is the location of the conflicting usage +.*:32: Warning: Use of 'fsetc\.s1' .* WAW dependency 'AR\[FPSR\]\.sf1\.controls' \(impliedf\) +.*:31: Warning: This is the location of the conflicting usage +.*:37: Warning: Use of 'fsetc\.s2' .* RAW dependency 'AR\[FPSR\]\.sf0\.controls' \(impliedf\) +.*:36: Warning: This is the location of the conflicting usage +.*:37: Warning: Use of 'fsetc\.s2' .* WAW dependency 'AR\[FPSR\]\.sf2\.controls' \(impliedf\) +.*:36: Warning: This is the location of the conflicting usage +.*:42: Warning: Use of 'fsetc\.s3' .* RAW dependency 'AR\[FPSR\]\.sf0\.controls' \(impliedf\) +.*:41: Warning: This is the location of the conflicting usage +.*:42: Warning: Use of 'fsetc\.s3' .* WAW dependency 'AR\[FPSR\]\.sf3\.controls' \(impliedf\) +.*:41: Warning: This is the location of the conflicting usage +.*:50: Warning: Use of 'fclrf\.s0' .* WAW dependency 'AR\[FPSR\]\.sf0\.flags' \(impliedf\) +.*:49: Warning: This is the location of the conflicting usage +.*:58: Warning: Use of 'fclrf\.s1' .* WAW dependency 'AR\[FPSR\]\.sf1\.flags' \(impliedf\) +.*:57: Warning: This is the location of the conflicting usage +.*:66: Warning: Use of 'fclrf\.s2' .* WAW dependency 'AR\[FPSR\]\.sf2\.flags' \(impliedf\) +.*:65: Warning: This is the location of the conflicting usage +.*:74: Warning: Use of 'fclrf\.s3' .* WAW dependency 'AR\[FPSR\]\.sf3\.flags' \(impliedf\) +.*:73: Warning: This is the location of the conflicting usage +.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf0\.controls' \(impliedf\) +.*:78: Warning: This is the location of the conflicting usage +.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf1\.controls' \(impliedf\) +.*:78: Warning: This is the location of the conflicting usage +.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf2\.controls' \(impliedf\) +.*:78: Warning: This is the location of the conflicting usage +.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf3\.controls' \(impliedf\) +.*:78: Warning: This is the location of the conflicting usage +.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf0\.flags' \(impliedf\) +.*:78: Warning: This is the location of the conflicting usage +.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf0\.flags' \(impliedf\) +.*:78: Warning: This is the location of the conflicting usage +.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf1\.flags' \(impliedf\) +.*:78: Warning: This is the location of the conflicting usage +.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf1\.flags' \(impliedf\) +.*:78: Warning: This is the location of the conflicting usage +.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf2\.flags' \(impliedf\) +.*:78: Warning: This is the location of the conflicting usage +.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf2\.flags' \(impliedf\) +.*:78: Warning: This is the location of the conflicting usage +.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf3\.flags' \(impliedf\) +.*:78: Warning: This is the location of the conflicting usage +.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf3\.flags' \(impliedf\) +.*:78: Warning: This is the location of the conflicting usage +.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.rv' \(impliedf\) +.*:78: Warning: This is the location of the conflicting usage +.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.traps' \(impliedf\) +.*:78: Warning: This is the location of the conflicting usage +.*:84: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[ITC\]' \(impliedf\) +.*:83: Warning: This is the location of the conflicting usage +.*:89: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[K%\], % in 0 - 7' \(impliedf\), specific resource number is 2 +.*:88: Warning: This is the location of the conflicting usage +.*:94: Warning: Use of 'mov\.i' .* WAW dependency 'AR\[LC\]' \(impliedf\) +.*:93: Warning: This is the location of the conflicting usage +.*:99: Warning: Use of 'br\.call\.sptk' .* WAW dependency 'AR\[PFS\]' \(impliedf\) +.*:98: Warning: This is the location of the conflicting usage +.*:104: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[RNAT\]' \(impliedf\) +.*:103: Warning: This is the location of the conflicting usage +.*:109: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[RSC\]' \(impliedf\) +.*:108: Warning: This is the location of the conflicting usage +.*:114: Warning: Use of 'st8\.spill' .* WAW dependency 'AR\[UNAT\]{%}, % in 0 - 63' \(impliedf\) +.*:113: Warning: This is the location of the conflicting usage +.*:119: Warning: Use of 'mov\.m' .* WAW dependency 'AR%, % in 48 - 63, 112-127' \(impliedf\), specific resource number is 48 +.*:118: Warning: This is the location of the conflicting usage +.*:124: Warning: Use of 'mov' .* WAW dependency 'BR%, % in 0 - 7' \(impliedf\), specific resource number is 1 +.*:123: Warning: This is the location of the conflicting usage +.*:129: Warning: Use of 'br\.wtop\.sptk' .* RAW dependency 'AR\[EC\]' \(impliedf\) +.*:128: Warning: This is the location of the conflicting usage +.*:129: Warning: Use of 'br\.wtop\.sptk' .* RAW dependency 'CFM' \(impliedf\) +.*:128: Warning: This is the location of the conflicting usage +.*:129: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'AR\[EC\]' \(impliedf\) +.*:128: Warning: This is the location of the conflicting usage +.*:129: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'CFM' \(impliedf\) +.*:128: Warning: This is the location of the conflicting usage +.*:129: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'PR63' \(impliedf\) +.*:128: Warning: This is the location of the conflicting usage +.*:129: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'PR63' \(impliedf\) +.*:128: Warning: This is the location of the conflicting usage +.*:134: Warning: Use of 'mov' .* WAW dependency 'CR\[CMCV\]' \(impliedf\) +.*:133: Warning: This is the location of the conflicting usage +.*:139: Warning: Use of 'mov' .* WAW dependency 'CR\[DCR\]' \(impliedf\) +.*:138: Warning: This is the location of the conflicting usage +.*:144: Warning: Use of 'mov' .* RAW dependency 'InService\*' \(impliedf\) +.*:143: Warning: This is the location of the conflicting usage +.*:144: Warning: Use of 'mov' .* WAW dependency 'CR\[EOI\]' \(other\) +.*:143: Warning: This is the location of the conflicting usage +.*:144: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\) +.*:143: Warning: This is the location of the conflicting usage +.*:150: Warning: Use of 'mov' .* WAW dependency 'CR\[GPTA\]' \(impliedf\) +.*:149: Warning: This is the location of the conflicting usage +.*:155: Warning: Use of 'mov' .* WAW dependency 'CR\[IFA\]' \(impliedf\) +.*:154: Warning: This is the location of the conflicting usage +.*:160: Warning: Use of 'cover' .* WAW dependency 'CR\[IFS\]' \(impliedf\) +.*:159: Warning: This is the location of the conflicting usage +.*:165: Warning: Use of 'mov' .* WAW dependency 'CR\[IHA\]' \(impliedf\) +.*:164: Warning: This is the location of the conflicting usage +.*:170: Warning: Use of 'mov' .* WAW dependency 'CR\[IIM\]' \(impliedf\) +.*:169: Warning: This is the location of the conflicting usage +.*:175: Warning: Use of 'mov' .* WAW dependency 'CR\[IIP\]' \(impliedf\) +.*:174: Warning: This is the location of the conflicting usage +.*:180: Warning: Use of 'mov' .* WAW dependency 'CR\[IIPA\]' \(impliedf\) +.*:179: Warning: This is the location of the conflicting usage +.*:185: Warning: Use of 'mov' .* WAW dependency 'CR\[IPSR\]' \(impliedf\) +.*:184: Warning: This is the location of the conflicting usage +.*:190: Warning: Use of 'mov' .* RAW dependency 'InService\*' \(impliedf\) +.*:189: Warning: This is the location of the conflicting usage +.*:190: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 71 +.*:189: Warning: This is the location of the conflicting usage +.*:190: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 70 +.*:189: Warning: This is the location of the conflicting usage +.*:190: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 69 +.*:189: Warning: This is the location of the conflicting usage +.*:190: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 68 +.*:189: Warning: This is the location of the conflicting usage +.*:190: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\) +.*:189: Warning: This is the location of the conflicting usage +.*:195: Warning: Use of 'mov' .* WAW dependency 'CR\[ISR\]' \(impliedf\) +.*:194: Warning: This is the location of the conflicting usage +.*:200: Warning: Use of 'mov' .* WAW dependency 'CR\[ITIR\]' \(impliedf\) +.*:199: Warning: This is the location of the conflicting usage +.*:205: Warning: Use of 'mov' .* WAW dependency 'CR\[ITM\]' \(impliedf\) +.*:204: Warning: This is the location of the conflicting usage +.*:210: Warning: Use of 'mov' .* WAW dependency 'CR\[ITV\]' \(impliedf\) +.*:209: Warning: This is the location of the conflicting usage +.*:215: Warning: Use of 'mov' .* WAW dependency 'CR\[IVA\]' \(impliedf\) +.*:214: Warning: This is the location of the conflicting usage +.*:222: Warning: Use of 'mov' .* WAW dependency 'CR\[LID\]' \(other\) +.*:221: Warning: This is the location of the conflicting usage +.*:230: Warning: Use of 'mov' .* WAW dependency 'CR\[LRR%\], % in 0 - 1' \(impliedf\), specific resource number is 80 +.*:229: Warning: This is the location of the conflicting usage +.*:235: Warning: Use of 'mov' .* WAW dependency 'CR\[PMV\]' \(impliedf\) +.*:234: Warning: This is the location of the conflicting usage +.*:240: Warning: Use of 'mov' .* WAW dependency 'CR\[PTA\]' \(impliedf\) +.*:239: Warning: This is the location of the conflicting usage +.*:245: Warning: Use of 'mov' .* WAW dependency 'CR\[TPR\]' \(impliedf\) +.*:244: Warning: This is the location of the conflicting usage +.*:250: Warning: Use of 'mov' .* WAW dependency 'DBR#' \(impliedf\) +.*:249: Warning: This is the location of the conflicting usage +.*:259: Warning: Use of 'itc\.i' .* RAW dependency 'DTC' \(impliedf\) +.*:258: Warning: This is the location of the conflicting usage +.*:259: Warning: Use of 'itc\.i' .* RAW dependency 'ITC' \(impliedf\) +.*:258: Warning: This is the location of the conflicting usage +.*:259: Warning: Use of 'itc\.i' .* WAW dependency 'DTC' \(impliedf\) +.*:258: Warning: This is the location of the conflicting usage +.*:259: Warning: Use of 'itc\.i' .* WAW dependency 'ITC' \(impliedf\) +.*:258: Warning: This is the location of the conflicting usage +.*:271: Warning: Use of 'ptr\.d' .* RAW dependency 'DTC' \(impliedf\) +.*:270: Warning: This is the location of the conflicting usage +.*:271: Warning: Use of 'ptr\.d' .* RAW dependency 'DTR' \(impliedf\) +.*:270: Warning: This is the location of the conflicting usage +.*:271: Warning: Use of 'ptr\.d' .* RAW dependency 'ITC' \(impliedf\) +.*:270: Warning: This is the location of the conflicting usage +.*:271: Warning: Use of 'ptr\.d' .* WAW dependency 'DTC' \(impliedf\) +.*:270: Warning: This is the location of the conflicting usage +.*:271: Warning: Use of 'ptr\.d' .* WAW dependency 'DTR' \(impliedf\) +.*:270: Warning: This is the location of the conflicting usage +.*:271: Warning: Use of 'ptr\.d' .* WAW dependency 'ITC' \(impliedf\) +.*:270: Warning: This is the location of the conflicting usage +.*:277: Warning: Use of 'ldfs\.c\.clr' .* WAW dependency 'FR%, % in 2 - 127' \(impliedf\), specific resource number is 3 +.*:276: Warning: This is the location of the conflicting usage +.*:282: Warning: Use of 'ld8\.c\.clr' .* WAW dependency 'GR%, % in 1 - 127' \(impliedf\), specific resource number is 2 +.*:281: Warning: This is the location of the conflicting usage +.*:287: Warning: Use of 'mov' .* WAW dependency 'IBR#' \(impliedf\) +.*:286: Warning: This is the location of the conflicting usage +.*:292: Warning: Use of 'mov' .* RAW dependency 'InService\*' \(data\) +.*:291: Warning: This is the location of the conflicting usage +.*:292: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\) +.*:291: Warning: This is the location of the conflicting usage +.*:298: Warning: Use of 'itc\.i' .* RAW dependency 'DTC' \(impliedf\) +.*:297: Warning: This is the location of the conflicting usage +.*:298: Warning: Use of 'itc\.i' .* RAW dependency 'ITC' \(impliedf\) +.*:297: Warning: This is the location of the conflicting usage +.*:298: Warning: Use of 'itc\.i' .* WAW dependency 'DTC' \(impliedf\) +.*:297: Warning: This is the location of the conflicting usage +.*:298: Warning: Use of 'itc\.i' .* WAW dependency 'ITC' \(impliedf\) +.*:297: Warning: This is the location of the conflicting usage +.*:305: Warning: Use of 'ptr\.i' .* RAW dependency 'DTC' \(impliedf\) +.*:304: Warning: This is the location of the conflicting usage +.*:305: Warning: Use of 'ptr\.i' .* RAW dependency 'ITC' \(impliedf\) +.*:304: Warning: This is the location of the conflicting usage +.*:305: Warning: Use of 'ptr\.i' .* RAW dependency 'ITR' \(impliedf\) +.*:304: Warning: This is the location of the conflicting usage +.*:305: Warning: Use of 'ptr\.i' .* WAW dependency 'DTC' \(impliedf\) +.*:304: Warning: This is the location of the conflicting usage +.*:305: Warning: Use of 'ptr\.i' .* WAW dependency 'ITC' \(impliedf\) +.*:304: Warning: This is the location of the conflicting usage +.*:305: Warning: Use of 'ptr\.i' .* WAW dependency 'ITR' \(impliedf\) +.*:304: Warning: This is the location of the conflicting usage +.*:317: Warning: Use of 'mov' .* WAW dependency 'PKR#' \(impliedf\), specific resource number is 1 +.*:316: Warning: This is the location of the conflicting usage +.*:322: Warning: Use of 'mov' .* WAW dependency 'PMC#' \(impliedf\) +.*:321: Warning: This is the location of the conflicting usage +.*:327: Warning: Use of 'mov' .* WAW dependency 'PMD#' \(impliedf\) +.*:326: Warning: This is the location of the conflicting usage +.*:332: Warning: Use of 'cmp\.eq' .* WAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 1 +.*:331: Warning: This is the location of the conflicting usage +.*:332: Warning: Use of 'cmp\.eq' .* WAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 1 +.*:331: Warning: This is the location of the conflicting usage +.*:335: Warning: Use of 'fcmp\.eq' .* WAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 1 +.*:334: Warning: This is the location of the conflicting usage +.*:335: Warning: Use of 'fcmp\.eq' .* WAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 1 +.*:334: Warning: This is the location of the conflicting usage +.*:338: Warning: Use of 'cmp\.eq\.or' .* WAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 1 +.*:337: Warning: This is the location of the conflicting usage +.*:341: Warning: Use of 'cmp\.eq\.and' .* WAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 1 +.*:340: Warning: This is the location of the conflicting usage +.*:352: Warning: Use of 'br\.wtop\.sptk' .* RAW dependency 'AR\[EC\]' \(impliedf\) +.*:351: Warning: This is the location of the conflicting usage +.*:352: Warning: Use of 'br\.wtop\.sptk' .* RAW dependency 'CFM' \(impliedf\) +.*:351: Warning: This is the location of the conflicting usage +.*:352: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'AR\[EC\]' \(impliedf\) +.*:351: Warning: This is the location of the conflicting usage +.*:352: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'CFM' \(impliedf\) +.*:351: Warning: This is the location of the conflicting usage +.*:352: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'PR63' \(impliedf\) +.*:351: Warning: This is the location of the conflicting usage +.*:352: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'PR63' \(impliedf\) +.*:351: Warning: This is the location of the conflicting usage +.*:355: Warning: Use of 'cmp\.eq' .* WAW dependency 'PR63' \(impliedf\) +.*:354: Warning: This is the location of the conflicting usage +.*:355: Warning: Use of 'cmp\.eq' .* WAW dependency 'PR63' \(impliedf\) +.*:354: Warning: This is the location of the conflicting usage +.*:358: Warning: Use of 'fcmp\.eq' .* WAW dependency 'PR63' \(impliedf\) +.*:357: Warning: This is the location of the conflicting usage +.*:358: Warning: Use of 'fcmp\.eq' .* WAW dependency 'PR63' \(impliedf\) +.*:357: Warning: This is the location of the conflicting usage +.*:361: Warning: Use of 'cmp\.eq\.or' .* WAW dependency 'PR63' \(impliedf\) +.*:360: Warning: This is the location of the conflicting usage +.*:364: Warning: Use of 'cmp\.eq\.and' .* WAW dependency 'PR63' \(impliedf\) +.*:363: Warning: This is the location of the conflicting usage +.*:375: Warning: Use of 'rum' .* WAW dependency 'PSR\.ac' \(impliedf\) +.*:374: Warning: This is the location of the conflicting usage +.*:380: Warning: Use of 'rum' .* WAW dependency 'PSR\.be' \(impliedf\) +.*:379: Warning: This is the location of the conflicting usage +.*:390: Warning: Use of 'br\.ret\.sptk' .* WAW dependency 'PSR\.cpl' \(impliedf\) +.*:389: Warning: This is the location of the conflicting usage +.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.ac' \(impliedf\) +.*:395: Warning: This is the location of the conflicting usage +.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.be' \(impliedf\) +.*:395: Warning: This is the location of the conflicting usage +.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.db' \(impliedf\) +.*:395: Warning: This is the location of the conflicting usage +.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.dfh' \(impliedf\) +.*:395: Warning: This is the location of the conflicting usage +.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.dfl' \(impliedf\) +.*:395: Warning: This is the location of the conflicting usage +.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.di' \(impliedf\) +.*:395: Warning: This is the location of the conflicting usage +.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.dt' \(impliedf\) +.*:395: Warning: This is the location of the conflicting usage +.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.i' \(impliedf\) +.*:395: Warning: This is the location of the conflicting usage +.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.ic' \(impliedf\) +.*:395: Warning: This is the location of the conflicting usage +.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.lp' \(impliedf\) +.*:395: Warning: This is the location of the conflicting usage +.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfh' \(impliedf\) +.*:395: Warning: This is the location of the conflicting usage +.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfh' \(impliedf\) +.*:395: Warning: This is the location of the conflicting usage +.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfl' \(impliedf\) +.*:395: Warning: This is the location of the conflicting usage +.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfl' \(impliedf\) +.*:395: Warning: This is the location of the conflicting usage +.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.pk' \(impliedf\) +.*:395: Warning: This is the location of the conflicting usage +.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.pp' \(impliedf\) +.*:395: Warning: This is the location of the conflicting usage +.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.rt' \(impliedf\) +.*:395: Warning: This is the location of the conflicting usage +.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.si' \(impliedf\) +.*:395: Warning: This is the location of the conflicting usage +.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.sp' \(impliedf\) +.*:395: Warning: This is the location of the conflicting usage +.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.tb' \(impliedf\) +.*:395: Warning: This is the location of the conflicting usage +.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.up' \(impliedf\) +.*:395: Warning: This is the location of the conflicting usage +.*:404: Warning: Use of 'ssm' .* WAW dependency 'PSR\.dfh' \(impliedf\) +.*:403: Warning: This is the location of the conflicting usage +.*:410: Warning: Use of 'ssm' .* WAW dependency 'PSR\.dfl' \(impliedf\) +.*:409: Warning: This is the location of the conflicting usage +.*:416: Warning: Use of 'rsm' .* WAW dependency 'PSR\.di' \(impliedf\) +.*:415: Warning: This is the location of the conflicting usage +.*:421: Warning: Use of 'rsm' .* WAW dependency 'PSR\.dt' \(impliedf\) +.*:420: Warning: This is the location of the conflicting usage +.*:427: Warning: Use of 'ssm' .* WAW dependency 'PSR\.i' \(impliedf\) +.*:426: Warning: This is the location of the conflicting usage +.*:433: Warning: Use of 'ssm' .* WAW dependency 'PSR\.ic' \(impliedf\) +.*:432: Warning: This is the location of the conflicting usage +.*:444: Warning: Use of 'mov' .* RAW dependency 'PSR\.mfh' \(impliedf\) +.*:443: Warning: This is the location of the conflicting usage +.*:447: Warning: Use of 'ssm' .* WAW dependency 'PSR\.mfh' \(impliedf\) +.*:446: Warning: This is the location of the conflicting usage +.*:447: Warning: Use of 'ssm' .* WAW dependency 'PSR\.mfh' \(impliedf\) +.*:446: Warning: This is the location of the conflicting usage +.*:450: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfh' \(impliedf\) +.*:449: Warning: This is the location of the conflicting usage +.*:450: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfh' \(impliedf\) +.*:449: Warning: This is the location of the conflicting usage +.*:453: Warning: Use of 'rum' .* WAW dependency 'PSR\.mfh' \(impliedf\) +.*:452: Warning: This is the location of the conflicting usage +.*:453: Warning: Use of 'rum' .* WAW dependency 'PSR\.mfh' \(impliedf\) +.*:452: Warning: This is the location of the conflicting usage +.*:461: Warning: Use of 'mov' .* RAW dependency 'PSR\.mfl' \(impliedf\) +.*:460: Warning: This is the location of the conflicting usage +.*:464: Warning: Use of 'ssm' .* WAW dependency 'PSR\.mfl' \(impliedf\) +.*:463: Warning: This is the location of the conflicting usage +.*:464: Warning: Use of 'ssm' .* WAW dependency 'PSR\.mfl' \(impliedf\) +.*:463: Warning: This is the location of the conflicting usage +.*:467: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfl' \(impliedf\) +.*:466: Warning: This is the location of the conflicting usage +.*:467: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfl' \(impliedf\) +.*:466: Warning: This is the location of the conflicting usage +.*:470: Warning: Use of 'rum' .* WAW dependency 'PSR\.mfl' \(impliedf\) +.*:469: Warning: This is the location of the conflicting usage +.*:470: Warning: Use of 'rum' .* WAW dependency 'PSR\.mfl' \(impliedf\) +.*:469: Warning: This is the location of the conflicting usage +.*:478: Warning: Use of 'rsm' .* WAW dependency 'PSR\.pk' \(impliedf\) +.*:477: Warning: This is the location of the conflicting usage +.*:483: Warning: Use of 'rsm' .* WAW dependency 'PSR\.pp' \(impliedf\) +.*:482: Warning: This is the location of the conflicting usage +.*:491: Warning: Use of 'ssm' .* WAW dependency 'PSR\.si' \(impliedf\) +.*:490: Warning: This is the location of the conflicting usage +.*:496: Warning: Use of 'rsm' .* WAW dependency 'PSR\.sp' \(impliedf\) +.*:495: Warning: This is the location of the conflicting usage +.*:505: Warning: Use of 'rsm' .* WAW dependency 'PSR\.up' \(impliedf\) +.*:504: Warning: This is the location of the conflicting usage +.*:508: Warning: Use of 'mov' .* WAW dependency 'PSR\.up' \(impliedf\) +.*:507: Warning: This is the location of the conflicting usage +.*:513: Warning: Use of 'mov' .* WAW dependency 'RR#' \(impliedf\) +.*:512: Warning: This is the location of the conflicting usage diff --git a/gas/testsuite/gas/ia64/dv-waw-err.s b/gas/testsuite/gas/ia64/dv-waw-err.s new file mode 100644 index 0000000..c6f4fe0 --- /dev/null +++ b/gas/testsuite/gas/ia64/dv-waw-err.s @@ -0,0 +1,516 @@ +// +// Detect WAW violations. Cases taken from DV tables. +// +.text + .explicit +// AR[BSP] + mov ar.bsp = r0 + mov ar.bsp = r1 + ;; +// AR[BSPSTORE] + mov ar.bspstore = r2 + mov ar.bspstore = r3 + ;; + +// AR[CCV] + mov ar.ccv = r4 + mov ar.ccv = r4 + ;; + +// AR[EC] + br.wtop.sptk L + mov ar.ec = r0 + ;; + +// AR[FPSR].sf0.controls + mov ar.fpsr = r0 + fsetc.s0 0x7f, 0x0f + ;; + +// AR[FPSR].sf1.controls + mov ar.fpsr = r0 + fsetc.s1 0x7f, 0x0f + ;; + +// AR[FPSR].sf2.controls + mov ar.fpsr = r0 + fsetc.s2 0x7f, 0x0f + ;; + +// AR[FPSR].sf3.controls + mov ar.fpsr = r0 + fsetc.s3 0x7f, 0x0f + ;; + +// AR[FPSR].sf0.flags + fcmp.eq.s0 p1, p2 = f3, f4 + fcmp.eq.s0 p3, p4 = f3, f4 // no DV here + ;; + fcmp.eq.s0 p1, p2 = f3, f4 + fclrf.s0 + ;; + +// AR[FPSR].sf1.flags + fcmp.eq.s1 p1, p2 = f3, f4 + fcmp.eq.s1 p3, p4 = f3, f4 // no DV here + ;; + fcmp.eq.s1 p1, p2 = f3, f4 + fclrf.s1 + ;; + +// AR[FPSR].sf2.flags + fcmp.eq.s2 p1, p2 = f3, f4 + fcmp.eq.s2 p3, p4 = f3, f4 // no DV here + ;; + fcmp.eq.s2 p1, p2 = f3, f4 + fclrf.s2 + ;; + +// AR[FPSR].sf3.flags + fcmp.eq.s3 p1, p2 = f3, f4 + fcmp.eq.s3 p3, p4 = f3, f4 // no DV here + ;; + fcmp.eq.s3 p1, p2 = f3, f4 + fclrf.s3 + ;; + +// AR[FPSR].traps/rv plus all controls/flags + mov ar.fpsr = r0 + mov ar.fpsr = r0 + ;; + +// AR[ITC] + mov ar.itc = r1 + mov ar.itc = r1 + ;; + +// AR[K] + mov ar.k2 = r3 + mov ar.k2 = r3 + ;; + +// AR[LC] + br.cloop.sptk L + mov ar.lc = r0 + ;; + +// AR[PFS] + mov ar.pfs = r0 + br.call.sptk b0 = L + ;; + +// AR[RNAT] (see also AR[BSPSTORE]) + mov ar.rnat = r8 + mov ar.rnat = r8 + ;; + +// AR[RSC] + mov ar.rsc = r10 + mov ar.rsc = r10 + ;; + +// AR[UNAT] + mov ar.unat = r12 + st8.spill [r0] = r1 + ;; + +// AR% + mov ar48 = r0 + mov ar48 = r0 + ;; + +// BR% + mov b1 = r0 + mov b1 = r1 + ;; + +// CFM (and others) + br.wtop.sptk L + br.wtop.sptk L + ;; + +// CR[CMCV] + mov cr.cmcv = r1 + mov cr.cmcv = r2 + ;; + +// CR[DCR] + mov cr.dcr = r3 + mov cr.dcr = r3 + ;; + +// CR[EOI] (and InService) + mov cr.eoi = r0 + mov cr.eoi = r0 + ;; + srlz.d + +// CR[GPTA] + mov cr.gpta = r6 + mov cr.gpta = r7 + ;; + +// CR[IFA] + mov cr.ifa = r9 + mov cr.ifa = r10 + ;; + +// CR[IFS] + mov cr.ifs = r11 + cover + ;; + +// CR[IHA] + mov cr.iha = r13 + mov cr.iha = r14 + ;; + +// CR[IIM] + mov cr.iim = r15 + mov cr.iim = r16 + ;; + +// CR[IIP] + mov cr.iip = r17 + mov cr.iip = r17 + ;; + +// CR[IIPA] + mov cr.iipa = r19 + mov cr.iipa = r20 + ;; + +// CR[IPSR] + mov cr.ipsr = r21 + mov cr.ipsr = r22 + ;; + +// CR[IRR%] (and others) + mov r0 = cr.ivr + mov r1 = cr.ivr + ;; + +// CR[ISR] + mov cr.isr = r24 + mov cr.isr = r25 + ;; + +// CR[ITIR] + mov cr.itir = r26 + mov cr.itir = r27 + ;; + +// CR[ITM] + mov cr.itm = r28 + mov cr.itm = r29 + ;; + +// CR[ITV] + mov cr.itv = r0 + mov cr.itv = r1 + ;; + +// CR[IVA] + mov cr.iva = r0 + mov cr.iva = r1 + ;; + +// CR[IVR] (no explicit writers) + +// CR[LID] + mov cr.lid = r0 + mov cr.lid = r1 + ;; + +// CR[LRR%] + mov cr.lrr0 = r0 + mov cr.lrr1 = r0 // no DV here + ;; + mov cr.lrr0 = r0 + mov cr.lrr0 = r0 + ;; + +// CR[PMV] + mov cr.pmv = r0 + mov cr.pmv = r1 + ;; + +// CR[PTA] + mov cr.pta = r0 + mov cr.pta = r1 + ;; + +// CR[TPR] + mov cr.tpr = r0 + mov cr.tpr = r1 + ;; + +// DBR# + mov dbr[r1] = r1 + mov dbr[r1] = r2 + ;; + srlz.d + +// DTC + ptc.e r0 + ptc.e r1 // no DVs here + ;; + ptc.e r0 // (and others) + itc.i r0 + ;; + srlz.d + +// DTC_LIMIT + ptc.g r0, r1 // NOTE: GAS automatically emits stops after + ptc.ga r2, r3 // ptc.g/ptc.ga, so this conflict is no + ;; // longer possible in GAS-generated assembly + srlz.d + +// DTR + itr.d dtr[r0] = r1 // (and others) + ptr.d r2, r3 + ;; + srlz.d + +// FR% + mov f3 = f2 + ldfs.c.clr f3 = [r1] + ;; + +// GR% + mov r2 = r0 + ld8.c.clr r2 = [r1] + ;; + +// IBR# + mov ibr[r0] = r2 + mov ibr[r1] = r2 + ;; + +// InService + mov cr.eoi = r0 + mov r1 = cr.ivr + ;; + srlz.d + +// ITC + ptc.e r0 + itc.i r1 + ;; + srlz.i + ;; + +// ITR + itr.i itr[r0] = r1 + ptr.i r2, r3 + ;; + srlz.i + ;; + +// PKR# + .reg.val r1, 0x1 + .reg.val r2, ~0x1 + mov pkr[r1] = r1 + mov pkr[r2] = r1 // no DV here + ;; + mov pkr[r1] = r1 + mov pkr[r1] = r1 + ;; + +// PMC# + mov pmc[r3] = r1 + mov pmc[r4] = r1 + ;; + +// PMD# + mov pmd[r3] = r1 + mov pmd[r4] = r1 + ;; + +// PR% + cmp.eq p1, p0 = r0, r1 + cmp.eq p1, p0 = r2, r3 + ;; + fcmp.eq p1, p2 = f2, f3 + fcmp.eq p1, p3 = f2, f3 + ;; + cmp.eq.and p1, p2 = r0, r1 + cmp.eq.or p1, p3 = r2, r3 + ;; + cmp.eq.or p1, p3 = r2, r3 + cmp.eq.and p1, p2 = r0, r1 + ;; + cmp.eq.and p1, p2 = r0, r1 + cmp.eq.and p1, p3 = r2, r3 // no DV here + ;; + cmp.eq.or p1, p2 = r0, r1 + cmp.eq.or p1, p3 = r2, r3 // no DV here + ;; + +// PR63 + br.wtop.sptk L + br.wtop.sptk L + ;; + cmp.eq p63, p0 = r0, r1 + cmp.eq p63, p0 = r2, r3 + ;; + fcmp.eq p63, p2 = f2, f3 + fcmp.eq p63, p3 = f2, f3 + ;; + cmp.eq.and p63, p2 = r0, r1 + cmp.eq.or p63, p3 = r2, r3 + ;; + cmp.eq.or p63, p3 = r2, r3 + cmp.eq.and p63, p2 = r0, r1 + ;; + cmp.eq.and p63, p2 = r0, r1 + cmp.eq.and p63, p3 = r2, r3 // no DV here + ;; + cmp.eq.or p63, p2 = r0, r1 + cmp.eq.or p63, p3 = r2, r3 // no DV here + ;; + +// PSR.ac + rum (1<<3) + rum (1<<3) + ;; + +// PSR.be + rum (1<<1) + rum (1<<1) + ;; + +// PSR.bn + bsw.0 // GAS automatically emits a stop after bsw.n + bsw.0 // so this conflict is avoided + ;; + +// PSR.cpl + epc + br.ret.sptk b0 + ;; + +// PSR.da (rfi is the only writer) +// PSR.db (and others) + mov psr.l = r0 + mov psr.l = r1 + ;; + srlz.d + +// PSR.dd (rfi is the only writer) + +// PSR.dfh + ssm (1<<19) + ssm (1<<19) + ;; + srlz.d + +// PSR.dfl + ssm (1<<18) + ssm (1<<18) + ;; + srlz.d + +// PSR.di + rsm (1<<22) + rsm (1<<22) + ;; + +// PSR.dt + rsm (1<<17) + rsm (1<<17) + ;; + +// PSR.ed (rfi is the only writer) +// PSR.i + ssm (1<<14) + ssm (1<<14) + ;; + +// PSR.ia (no DV semantics) +// PSR.ic + ssm (1<<13) + ssm (1<<13) + ;; + +// PSR.id (rfi is the only writer) +// PSR.is (br.ia and rfi are the only writers) +// PSR.it (rfi is the only writer) +// PSR.lp (see PSR.db) + +// PSR.mc (rfi is the only writer) +// PSR.mfh + mov f32 = f33 + mov r0 = psr + ;; + ssm (1<<5) + ssm (1<<5) + ;; + ssm (1<<5) + mov psr.um = r0 + ;; + rum (1<<5) + rum (1<<5) + ;; + mov f32 = f33 + mov f34 = f35 // no DV here + ;; + +// PSR.mfl + mov f2 = f3 + mov r0 = psr + ;; + ssm (1<<4) + ssm (1<<4) + ;; + ssm (1<<4) + mov psr.um = r0 + ;; + rum (1<<4) + rum (1<<4) + ;; + mov f2 = f3 + mov f4 = f5 // no DV here + ;; + +// PSR.pk + rsm (1<<15) + rsm (1<<15) + ;; + +// PSR.pp + rsm (1<<21) + rsm (1<<21) + ;; + +// PSR.ri (no DV semantics) +// PSR.rt (see PSR.db) + +// PSR.si + rsm (1<<23) + ssm (1<<23) + ;; + +// PSR.sp + ssm (1<<20) + rsm (1<<20) + ;; + srlz.d + +// PSR.ss (rfi is the only writer) +// PSR.tb (see PSR.db) + +// PSR.up + rsm (1<<2) + rsm (1<<2) + ;; + rum (1<<2) + mov psr.um = r0 + ;; + +// RR# + mov rr[r2] = r1 + mov rr[r2] = r3 + ;; +// RSE +L: diff --git a/gas/testsuite/gas/ia64/fixup-dump.pl b/gas/testsuite/gas/ia64/fixup-dump.pl new file mode 100644 index 0000000..73c218b --- /dev/null +++ b/gas/testsuite/gas/ia64/fixup-dump.pl @@ -0,0 +1,12 @@ +print "# objdump: -d\n"; +print "# name: ia64 $ARGV[0]\n"; +shift; + +while (<>) { + if (/.*file format.*/) { + $_ = ".*: +file format .*\n"; + } else { + s/([][().])/\\$1/g; + } + print; +} diff --git a/gas/testsuite/gas/ia64/ia64.exp b/gas/testsuite/gas/ia64/ia64.exp new file mode 100644 index 0000000..5c6db40 --- /dev/null +++ b/gas/testsuite/gas/ia64/ia64.exp @@ -0,0 +1,38 @@ +# +# ia64 tests +# +proc run_list_test { name opts } { + global srcdir subdir + set testname "ia64 $name" + set file $srcdir/$subdir/$name + gas_run ${name}.s $opts ">&dump.out" + if { [regexp_diff "dump.out" "${file}.l"] } then { + fail $testname + verbose "output is [file_contents "dump.out"]" 2 + return + } + pass $testname +} + +if [istarget "ia64-*"] then { + + run_dump_test "regs" + run_dump_test "opc-a" + run_list_test "opc-a-err" "" + run_dump_test "opc-b" + run_dump_test "opc-f" + run_dump_test "opc-i" + run_dump_test "opc-m" + run_dump_test "opc-x" + + run_list_test "dv-raw-err" "" + run_list_test "dv-waw-err" "" + run_list_test "dv-war-err" "" + run_list_test "dv-entry-err" "" + run_list_test "dv-mutex-err" "" + run_dump_test "dv-branch" + run_dump_test "dv-imply" + run_dump_test "dv-mutex" + run_dump_test "dv-safe" + run_dump_test "dv-srlz" +} diff --git a/gas/testsuite/gas/ia64/opc-a-err.l b/gas/testsuite/gas/ia64/opc-a-err.l new file mode 100644 index 0000000..571a825 --- /dev/null +++ b/gas/testsuite/gas/ia64/opc-a-err.l @@ -0,0 +1,18 @@ +.*: Assembler messages: +.*:1: Error: Operand 2 of `adds' should be a 14-bit .* +.*:2: Error: Operand 2 of `adds' should be a 14-bit .* +.*:4: Error: Operand 2 of `addl' should be a 22-bit .* +.*:5: Error: Operand 2 of `addl' should be a 22-bit .* +.*:6: Error: Operand 3 of `addl' should be a general register r0-r3 +.*:8: Error: Operand 2 of `sub' should be .* +.*:9: Error: Operand 2 of `sub' should be .* +.*:11: Error: Operand 2 of `and' should be .* +.*:12: Error: Operand 2 of `and' should be .* +.*:14: Error: Operand 2 of `or' should be .* +.*:15: Error: Operand 2 of `or' should be .* +.*:17: Error: Operand 2 of `xor' should be .* +.*:18: Error: Operand 2 of `xor' should be .* +.*:20: Error: Operand 2 of `andcm' should be .* +.*:21: Error: Operand 2 of `andcm' should be .* +.*:23: Error: Operand 3 of `cmp4.lt.or' should be r0 +.*:24: Error: Operand 3 of `cmp4.lt.or' should be r0 diff --git a/gas/testsuite/gas/ia64/opc-a-err.s b/gas/testsuite/gas/ia64/opc-a-err.s new file mode 100644 index 0000000..136fb26 --- /dev/null +++ b/gas/testsuite/gas/ia64/opc-a-err.s @@ -0,0 +1,24 @@ + adds r25 = -0x2001, r10 + adds r26 = 0x2000, r10 + + addl r37 = -0x200001, r1 + addl r38 = 0x200000, r1 + addl r30 = 0, r10 + + sub r2 = 128, r3 + sub r3 = -129, r4 + + and r8 = 129, r9 + and r3 = -129, r4 + + or r8 = 129, r9 + or r3 = -129, r4 + + xor r8 = 129, r9 + xor r3 = -129, r4 + + andcm r8 = 129, r9 + andcm r3 = -129, r4 + + cmp4.lt.or p2, p3 = r1, r4 + cmp4.lt.or p2, p3 = 1, r4 diff --git a/gas/testsuite/gas/ia64/opc-a.d b/gas/testsuite/gas/ia64/opc-a.d new file mode 100644 index 0000000..132900b --- /dev/null +++ b/gas/testsuite/gas/ia64/opc-a.d @@ -0,0 +1,290 @@ +# objdump: -d +# name: ia64 opc-a + +.*: +file format .* + +Disassembly of section \.text: + +0000000000000000 <_start>: + 0: 00 28 9b cf 00 60 \[MII\] add r101=r102,r103 + 6: 80 4e ab 01 40 60 \(p01\) add r104=r105,r106 + c: cd 6e 07 80 add r107=r108,r109,1 + 10: 40 70 bf e1 01 20 \[MII\] \(p02\) add r110=r111,r112,1 + 16: 40 01 28 00 c2 a0 mov r20=r10 + 1c: 12 50 00 84 \(p01\) adds r21=1,r10 + 20: 00 b0 fc 15 3f 23 \[MII\] adds r22=-1,r10 + 26: 70 01 28 00 46 01 adds r23=-8192,r10 + 2c: f3 57 fc 84 \(p02\) adds r24=8191,r10 + 30: 00 f0 00 02 00 24 \[MII\] addl r30=0,r1 + 36: f0 09 04 00 c8 00 addl r31=1,r1 + 3c: f4 ef ff 9f \(p01\) addl r32=-1,r1 + 40: 00 08 01 fa c0 27 \[MII\] addl r33=-8192,r1 + 46: 20 fa 07 7e 48 60 addl r34=8191,r1 + 4c: 04 08 00 98 addl r35=-2097152,r1 + 50: 00 20 fd fb ff 25 \[MII\] addl r36=2097151,r1 + 56: b0 00 28 00 42 80 mov r11=r10 + 5c: 41 53 90 84 adds r12=4660,r10 + 60: 00 68 d0 02 24 24 \[MII\] addl r13=4660,r1 + 66: e0 28 16 8c 48 80 addl r14=74565,r1 + 6c: 32 50 20 80 addp4 r20=r3,r10 + 70: 20 a8 04 14 80 21 \[MII\] \(p01\) addp4 r21=1,r10 + 76: 60 f9 2b 7e 47 a0 addp4 r22=-1,r10 + 7c: 6c 3e 17 80 sub r101=r102,r103 + 80: 40 70 bf e1 04 20 \[MII\] \(p02\) sub r110=r111,r112,1 + 86: 80 07 0c 4a 40 20 sub r120=0,r3 + 8c: 1f 18 94 80 sub r121=1,r3 + 90: 00 d0 ff 07 25 22 \[MII\] sub r122=-1,r3 + 96: b0 07 0c 4a 44 80 sub r123=-128,r3 + 9c: ff 1f 94 80 sub r124=127,r3 + a0: 00 40 24 14 0c e0 \[MII\] and r8=r9,r10 + a6: b0 00 30 58 44 02 \(p03\) and r11=-128,r12 + ac: 91 50 38 80 \(p04\) or r8=r9,r10 + b0: 00 58 00 18 2e 22 \[MII\] or r11=-128,r12 + b6: 80 48 28 1e 40 60 xor r8=r9,r10 + bc: 01 60 bc 88 xor r11=-128,r12 + c0: 00 40 24 14 0d 20 \[MII\] andcm r8=r9,r10 + c6: b0 00 30 5a 44 00 andcm r11=-128,r12 + cc: e1 f9 40 80 shladd r8=r30,1,r31 + d0: 00 48 78 3e 11 20 \[MII\] shladd r9=r30,2,r31 + d6: a0 f0 7c 24 40 60 shladd r10=r30,3,r31 + dc: e1 f9 4c 80 shladd r11=r30,4,r31 + e0: 00 40 78 3e 18 20 \[MII\] shladdp4 r8=r30,1,r31 + e6: 90 f0 7c 32 40 40 shladdp4 r9=r30,2,r31 + ec: e1 f9 68 80 shladdp4 r10=r30,3,r31 + f0: 00 58 78 3e 1b 20 \[MII\] shladdp4 r11=r30,4,r31 + f6: a0 f0 7c 00 41 60 padd1 r10=r30,r31 + fc: e1 f9 04 82 padd1\.sss r11=r30,r31 + 100: 00 60 78 3e 83 20 \[MII\] padd1\.uus r12=r30,r31 + 106: d0 f0 7c 04 41 c0 padd1\.uuu r13=r30,r31 + 10c: e1 f9 00 83 padd2 r14=r30,r31 + 110: 00 78 78 3e c1 20 \[MII\] padd2\.sss r15=r30,r31 + 116: 00 f1 7c 86 41 20 padd2\.uus r16=r30,r31 + 11c: e2 f9 08 83 padd2\.uuu r17=r30,r31 + 120: 00 90 78 3e 80 22 \[MII\] padd4 r18=r30,r31 + 126: a0 f0 7c 08 41 60 psub1 r10=r30,r31 + 12c: e1 f9 14 82 psub1\.sss r11=r30,r31 + 130: 00 60 78 3e 87 20 \[MII\] psub1\.uus r12=r30,r31 + 136: d0 f0 7c 0c 41 c0 psub1\.uuu r13=r30,r31 + 13c: e1 f9 10 83 psub2 r14=r30,r31 + 140: 00 78 78 3e c5 20 \[MII\] psub2\.sss r15=r30,r31 + 146: 00 f1 7c 8e 41 20 psub2\.uus r16=r30,r31 + 14c: e2 f9 18 83 psub2\.uuu r17=r30,r31 + 150: 00 90 78 3e 84 22 \[MII\] psub4 r18=r30,r31 + 156: a0 f0 7c 14 41 40 pavg1 r10=r30,r31 + 15c: e1 f9 2c 82 pavg1\.raz r10=r30,r31 + 160: 00 50 78 3e ca 20 \[MII\] pavg2 r10=r30,r31 + 166: a0 f0 7c 96 41 40 pavg2\.raz r10=r30,r31 + 16c: e1 f9 38 82 pavgsub1 r10=r30,r31 + 170: 00 50 78 3e ce 20 \[MII\] pavgsub2 r10=r30,r31 + 176: a0 f0 7c 48 41 40 pcmp1\.eq r10=r30,r31 + 17c: e1 f9 90 83 pcmp2\.eq r10=r30,r31 + 180: 00 50 78 3e a4 22 \[MII\] pcmp4\.eq r10=r30,r31 + 186: a0 f0 7c 4a 41 40 pcmp1\.gt r10=r30,r31 + 18c: e1 f9 94 83 pcmp2\.gt r10=r30,r31 + 190: 00 50 78 3e a5 22 \[MII\] pcmp4\.gt r10=r30,r31 + 196: a0 58 30 a0 41 40 pshladd2 r10=r11,1,r12 + 19c: b1 60 48 83 pshladd2 r10=r11,3,r12 + 1a0: 00 50 2c 18 d8 20 \[MII\] pshradd2 r10=r11,1,r12 + 1a6: a0 58 30 b2 41 40 pshradd2 r10=r11,2,r12 + 1ac: 30 20 0c e0 cmp\.eq p2,p3=r3,r4 + 1b0: 00 10 0c 08 03 39 \[MII\] cmp\.eq p2,p3=3,r4 + 1b6: 30 18 10 04 70 60 cmp\.eq p3,p2=r3,r4 + 1bc: 30 20 08 e4 cmp\.eq p3,p2=3,r4 + 1c0: 00 10 0c 08 03 30 \[MII\] cmp\.lt p2,p3=r3,r4 + 1c6: 20 18 10 06 62 60 cmp\.lt p2,p3=3,r4 + 1cc: 40 18 08 c0 cmp\.lt p3,p2=r4,r3 + 1d0: 00 10 08 08 03 31 \[MII\] cmp\.lt p2,p3=2,r4 + 1d6: 20 20 0c 06 60 60 cmp\.lt p2,p3=r4,r3 + 1dc: 20 20 08 c4 cmp\.lt p3,p2=2,r4 + 1e0: 00 18 0c 08 02 30 \[MII\] cmp\.lt p3,p2=r3,r4 + 1e6: 30 18 10 04 62 40 cmp\.lt p3,p2=3,r4 + 1ec: 30 20 0c d0 cmp\.ltu p2,p3=r3,r4 + 1f0: 00 10 0c 08 03 35 \[MII\] cmp\.ltu p2,p3=3,r4 + 1f6: 30 20 0c 04 68 40 cmp\.ltu p3,p2=r4,r3 + 1fc: 20 20 0c d4 cmp\.ltu p2,p3=2,r4 + 200: 00 10 10 06 03 34 \[MII\] cmp\.ltu p2,p3=r4,r3 + 206: 30 10 10 04 6a 60 cmp\.ltu p3,p2=2,r4 + 20c: 30 20 08 d0 cmp\.ltu p3,p2=r3,r4 + 210: 00 18 0c 08 02 35 \[MII\] cmp\.ltu p3,p2=3,r4 + 216: 20 1c 10 06 70 40 cmp\.eq\.unc p2,p3=r3,r4 + 21c: 38 20 0c e4 cmp\.eq\.unc p2,p3=3,r4 + 220: 00 18 0e 08 02 38 \[MII\] cmp\.eq\.unc p3,p2=r3,r4 + 226: 30 1c 10 04 72 40 cmp\.eq\.unc p3,p2=3,r4 + 22c: 38 20 0c c0 cmp\.lt\.unc p2,p3=r3,r4 + 230: 00 10 0e 08 03 31 \[MII\] cmp\.lt\.unc p2,p3=3,r4 + 236: 30 24 0c 04 60 40 cmp\.lt\.unc p3,p2=r4,r3 + 23c: 28 20 0c c4 cmp\.lt\.unc p2,p3=2,r4 + 240: 00 10 12 06 03 30 \[MII\] cmp\.lt\.unc p2,p3=r4,r3 + 246: 30 14 10 04 62 60 cmp\.lt\.unc p3,p2=2,r4 + 24c: 38 20 08 c0 cmp\.lt\.unc p3,p2=r3,r4 + 250: 00 18 0e 08 02 31 \[MII\] cmp\.lt\.unc p3,p2=3,r4 + 256: 20 1c 10 06 68 40 cmp\.ltu\.unc p2,p3=r3,r4 + 25c: 38 20 0c d4 cmp\.ltu\.unc p2,p3=3,r4 + 260: 00 18 12 06 02 34 \[MII\] cmp\.ltu\.unc p3,p2=r4,r3 + 266: 20 14 10 06 6a 40 cmp\.ltu\.unc p2,p3=2,r4 + 26c: 48 18 0c d0 cmp\.ltu\.unc p2,p3=r4,r3 + 270: 00 18 0a 08 02 35 \[MII\] cmp\.ltu\.unc p3,p2=2,r4 + 276: 30 1c 10 04 68 60 cmp\.ltu\.unc p3,p2=r3,r4 + 27c: 38 20 08 d4 cmp\.ltu\.unc p3,p2=3,r4 + 280: 00 10 0c 08 43 30 \[MII\] cmp\.eq\.and p2,p3=r3,r4 + 286: 20 18 10 86 62 40 cmp\.eq\.and p2,p3=3,r4 + 28c: 30 20 0c d1 cmp\.eq\.or p2,p3=r3,r4 + 290: 00 10 0c 08 43 35 \[MII\] cmp\.eq\.or p2,p3=3,r4 + 296: 20 18 10 86 70 40 cmp\.eq\.or\.andcm p2,p3=r3,r4 + 29c: 30 20 0c e5 cmp\.eq\.or\.andcm p2,p3=3,r4 + 2a0: 00 10 0e 08 43 34 \[MII\] cmp\.ne\.or p2,p3=r3,r4 + 2a6: 20 1c 10 86 6a 40 cmp\.ne\.or p2,p3=3,r4 + 2ac: 38 20 0c c1 cmp\.ne\.and p2,p3=r3,r4 + 2b0: 00 10 0e 08 43 31 \[MII\] cmp\.ne\.and p2,p3=3,r4 + 2b6: 30 1c 10 84 70 60 cmp\.ne\.or\.andcm p3,p2=r3,r4 + 2bc: 38 20 08 e5 cmp\.ne\.or\.andcm p3,p2=3,r4 + 2c0: 00 10 0e 08 43 30 \[MII\] cmp\.ne\.and p2,p3=r3,r4 + 2c6: 20 1c 10 86 62 40 cmp\.ne\.and p2,p3=3,r4 + 2cc: 38 20 0c d1 cmp\.ne\.or p2,p3=r3,r4 + 2d0: 00 10 0e 08 43 35 \[MII\] cmp\.ne\.or p2,p3=3,r4 + 2d6: 20 1c 10 86 70 40 cmp\.ne\.or\.andcm p2,p3=r3,r4 + 2dc: 38 20 0c e5 cmp\.ne\.or\.andcm p2,p3=3,r4 + 2e0: 00 10 0c 08 43 34 \[MII\] cmp\.eq\.or p2,p3=r3,r4 + 2e6: 20 18 10 86 6a 40 cmp\.eq\.or p2,p3=3,r4 + 2ec: 30 20 0c c1 cmp\.eq\.and p2,p3=r3,r4 + 2f0: 00 10 0c 08 43 31 \[MII\] cmp\.eq\.and p2,p3=3,r4 + 2f6: 30 18 10 84 70 60 cmp\.eq\.or\.andcm p3,p2=r3,r4 + 2fc: 30 20 08 e5 cmp\.eq\.or\.andcm p3,p2=3,r4 + 300: 00 10 00 08 43 30 \[MII\] cmp\.eq\.and p2,p3=r0,r4 + 306: 20 00 10 86 68 40 cmp\.eq\.or p2,p3=r0,r4 + 30c: 00 20 0c e1 cmp\.eq\.or\.andcm p2,p3=r0,r4 + 310: 00 10 02 08 43 34 \[MII\] cmp\.ne\.or p2,p3=r0,r4 + 316: 20 04 10 86 60 60 cmp\.ne\.and p2,p3=r0,r4 + 31c: 08 20 08 e1 cmp\.ne\.or\.andcm p3,p2=r0,r4 + 320: 00 10 02 08 43 30 \[MII\] cmp\.ne\.and p2,p3=r0,r4 + 326: 20 04 10 86 68 40 cmp\.ne\.or p2,p3=r0,r4 + 32c: 08 20 0c e1 cmp\.ne\.or\.andcm p2,p3=r0,r4 + 330: 00 10 00 08 43 34 \[MII\] cmp\.eq\.or p2,p3=r0,r4 + 336: 20 00 10 86 60 60 cmp\.eq\.and p2,p3=r0,r4 + 33c: 00 20 08 e1 cmp\.eq\.or\.andcm p3,p2=r0,r4 + 340: 00 10 02 08 43 32 \[MII\] cmp\.lt\.and p2,p3=r0,r4 + 346: 20 04 10 86 6c 40 cmp\.lt\.or p2,p3=r0,r4 + 34c: 08 20 0c e9 cmp\.lt\.or\.andcm p2,p3=r0,r4 + 350: 00 10 00 08 43 36 \[MII\] cmp\.ge\.or p2,p3=r0,r4 + 356: 20 00 10 86 64 60 cmp\.ge\.and p2,p3=r0,r4 + 35c: 00 20 08 e9 cmp\.ge\.or\.andcm p3,p2=r0,r4 + 360: 00 10 02 08 03 32 \[MII\] cmp\.le\.and p2,p3=r0,r4 + 366: 20 04 10 06 6c 40 cmp\.le\.or p2,p3=r0,r4 + 36c: 08 20 0c e8 cmp\.le\.or\.andcm p2,p3=r0,r4 + 370: 00 10 00 08 03 36 \[MII\] cmp\.gt\.or p2,p3=r0,r4 + 376: 20 00 10 06 64 60 cmp\.gt\.and p2,p3=r0,r4 + 37c: 00 20 08 e8 cmp\.gt\.or\.andcm p3,p2=r0,r4 + 380: 00 10 00 08 03 32 \[MII\] cmp\.gt\.and p2,p3=r0,r4 + 386: 20 00 10 06 6c 40 cmp\.gt\.or p2,p3=r0,r4 + 38c: 00 20 0c e8 cmp\.gt\.or\.andcm p2,p3=r0,r4 + 390: 00 10 02 08 03 36 \[MII\] cmp\.le\.or p2,p3=r0,r4 + 396: 20 04 10 06 64 60 cmp\.le\.and p2,p3=r0,r4 + 39c: 08 20 08 e8 cmp\.le\.or\.andcm p3,p2=r0,r4 + 3a0: 00 10 00 08 43 32 \[MII\] cmp\.ge\.and p2,p3=r0,r4 + 3a6: 20 00 10 86 6c 40 cmp\.ge\.or p2,p3=r0,r4 + 3ac: 00 20 0c e9 cmp\.ge\.or\.andcm p2,p3=r0,r4 + 3b0: 00 10 02 08 43 36 \[MII\] cmp\.lt\.or p2,p3=r0,r4 + 3b6: 20 04 10 86 64 60 cmp\.lt\.and p2,p3=r0,r4 + 3bc: 08 20 08 e9 cmp\.lt\.or\.andcm p3,p2=r0,r4 + 3c0: 00 10 0c 08 83 38 \[MII\] cmp4\.eq p2,p3=r3,r4 + 3c6: 20 18 10 06 73 60 cmp4\.eq p2,p3=3,r4 + 3cc: 30 20 08 e2 cmp4\.eq p3,p2=r3,r4 + 3d0: 00 18 0c 08 82 39 \[MII\] cmp4\.eq p3,p2=3,r4 + 3d6: 20 18 10 06 61 40 cmp4\.lt p2,p3=r3,r4 + 3dc: 30 20 0c c6 cmp4\.lt p2,p3=3,r4 + 3e0: 00 18 10 06 82 30 \[MII\] cmp4\.lt p3,p2=r4,r3 + 3e6: 20 10 10 06 63 40 cmp4\.lt p2,p3=2,r4 + 3ec: 40 18 0c c2 cmp4\.lt p2,p3=r4,r3 + 3f0: 00 18 08 08 82 31 \[MII\] cmp4\.lt p3,p2=2,r4 + 3f6: 30 18 10 04 61 60 cmp4\.lt p3,p2=r3,r4 + 3fc: 30 20 08 c6 cmp4\.lt p3,p2=3,r4 + 400: 00 10 0c 08 83 34 \[MII\] cmp4\.ltu p2,p3=r3,r4 + 406: 20 18 10 06 6b 60 cmp4\.ltu p2,p3=3,r4 + 40c: 40 18 08 d2 cmp4\.ltu p3,p2=r4,r3 + 410: 00 10 08 08 83 35 \[MII\] cmp4\.ltu p2,p3=2,r4 + 416: 20 20 0c 06 69 60 cmp4\.ltu p2,p3=r4,r3 + 41c: 20 20 08 d6 cmp4\.ltu p3,p2=2,r4 + 420: 00 18 0c 08 82 34 \[MII\] cmp4\.ltu p3,p2=r3,r4 + 426: 30 18 10 04 6b 40 cmp4\.ltu p3,p2=3,r4 + 42c: 38 20 0c e2 cmp4\.eq\.unc p2,p3=r3,r4 + 430: 00 10 0e 08 83 39 \[MII\] cmp4\.eq\.unc p2,p3=3,r4 + 436: 30 1c 10 04 71 60 cmp4\.eq\.unc p3,p2=r3,r4 + 43c: 38 20 08 e6 cmp4\.eq\.unc p3,p2=3,r4 + 440: 00 10 0e 08 83 30 \[MII\] cmp4\.lt\.unc p2,p3=r3,r4 + 446: 20 1c 10 06 63 60 cmp4\.lt\.unc p2,p3=3,r4 + 44c: 48 18 08 c2 cmp4\.lt\.unc p3,p2=r4,r3 + 450: 00 10 0a 08 83 31 \[MII\] cmp4\.lt\.unc p2,p3=2,r4 + 456: 20 24 0c 06 61 60 cmp4\.lt\.unc p2,p3=r4,r3 + 45c: 28 20 08 c6 cmp4\.lt\.unc p3,p2=2,r4 + 460: 00 18 0e 08 82 30 \[MII\] cmp4\.lt\.unc p3,p2=r3,r4 + 466: 30 1c 10 04 63 40 cmp4\.lt\.unc p3,p2=3,r4 + 46c: 38 20 0c d2 cmp4\.ltu\.unc p2,p3=r3,r4 + 470: 00 10 0e 08 83 35 \[MII\] cmp4\.ltu\.unc p2,p3=3,r4 + 476: 30 24 0c 04 69 40 cmp4\.ltu\.unc p3,p2=r4,r3 + 47c: 28 20 0c d6 cmp4\.ltu\.unc p2,p3=2,r4 + 480: 00 10 12 06 83 34 \[MII\] cmp4\.ltu\.unc p2,p3=r4,r3 + 486: 30 14 10 04 6b 60 cmp4\.ltu\.unc p3,p2=2,r4 + 48c: 38 20 08 d2 cmp4\.ltu\.unc p3,p2=r3,r4 + 490: 00 18 0e 08 82 35 \[MII\] cmp4\.ltu\.unc p3,p2=3,r4 + 496: 20 18 10 86 61 40 cmp4\.eq\.and p2,p3=r3,r4 + 49c: 30 20 0c c7 cmp4\.eq\.and p2,p3=3,r4 + 4a0: 00 10 0c 08 c3 34 \[MII\] cmp4\.eq\.or p2,p3=r3,r4 + 4a6: 20 18 10 86 6b 40 cmp4\.eq\.or p2,p3=3,r4 + 4ac: 30 20 0c e3 cmp4\.eq\.or\.andcm p2,p3=r3,r4 + 4b0: 00 10 0c 08 c3 39 \[MII\] cmp4\.eq\.or\.andcm p2,p3=3,r4 + 4b6: 20 1c 10 86 69 40 cmp4\.ne\.or p2,p3=r3,r4 + 4bc: 38 20 0c d7 cmp4\.ne\.or p2,p3=3,r4 + 4c0: 00 10 0e 08 c3 30 \[MII\] cmp4\.ne\.and p2,p3=r3,r4 + 4c6: 20 1c 10 86 63 60 cmp4\.ne\.and p2,p3=3,r4 + 4cc: 38 20 08 e3 cmp4\.ne\.or\.andcm p3,p2=r3,r4 + 4d0: 00 18 0e 08 c2 39 \[MII\] cmp4\.ne\.or\.andcm p3,p2=3,r4 + 4d6: 20 1c 10 86 61 40 cmp4\.ne\.and p2,p3=r3,r4 + 4dc: 38 20 0c c7 cmp4\.ne\.and p2,p3=3,r4 + 4e0: 00 10 0e 08 c3 34 \[MII\] cmp4\.ne\.or p2,p3=r3,r4 + 4e6: 20 1c 10 86 6b 40 cmp4\.ne\.or p2,p3=3,r4 + 4ec: 38 20 0c e3 cmp4\.ne\.or\.andcm p2,p3=r3,r4 + 4f0: 00 10 0e 08 c3 39 \[MII\] cmp4\.ne\.or\.andcm p2,p3=3,r4 + 4f6: 20 18 10 86 69 40 cmp4\.eq\.or p2,p3=r3,r4 + 4fc: 30 20 0c d7 cmp4\.eq\.or p2,p3=3,r4 + 500: 00 10 0c 08 c3 30 \[MII\] cmp4\.eq\.and p2,p3=r3,r4 + 506: 20 18 10 86 63 60 cmp4\.eq\.and p2,p3=3,r4 + 50c: 30 20 08 e3 cmp4\.eq\.or\.andcm p3,p2=r3,r4 + 510: 00 18 0c 08 c2 39 \[MII\] cmp4\.eq\.or\.andcm p3,p2=3,r4 + 516: 20 00 10 86 61 40 cmp4\.eq\.and p2,p3=r0,r4 + 51c: 00 20 0c d3 cmp4\.eq\.or p2,p3=r0,r4 + 520: 00 10 00 08 c3 38 \[MII\] cmp4\.eq\.or\.andcm p2,p3=r0,r4 + 526: 20 04 10 86 69 40 cmp4\.ne\.or p2,p3=r0,r4 + 52c: 08 20 0c c3 cmp4\.ne\.and p2,p3=r0,r4 + 530: 00 18 02 08 c2 38 \[MII\] cmp4\.ne\.or\.andcm p3,p2=r0,r4 + 536: 20 04 10 86 61 40 cmp4\.ne\.and p2,p3=r0,r4 + 53c: 08 20 0c d3 cmp4\.ne\.or p2,p3=r0,r4 + 540: 00 10 02 08 c3 38 \[MII\] cmp4\.ne\.or\.andcm p2,p3=r0,r4 + 546: 20 00 10 86 69 40 cmp4\.eq\.or p2,p3=r0,r4 + 54c: 00 20 0c c3 cmp4\.eq\.and p2,p3=r0,r4 + 550: 00 18 00 08 c2 38 \[MII\] cmp4\.eq\.or\.andcm p3,p2=r0,r4 + 556: 20 04 10 86 65 40 cmp4\.lt\.and p2,p3=r0,r4 + 55c: 08 20 0c db cmp4\.lt\.or p2,p3=r0,r4 + 560: 00 10 02 08 c3 3a \[MII\] cmp4\.lt\.or\.andcm p2,p3=r0,r4 + 566: 20 00 10 86 6d 40 cmp4\.ge\.or p2,p3=r0,r4 + 56c: 00 20 0c cb cmp4\.ge\.and p2,p3=r0,r4 + 570: 00 18 00 08 c2 3a \[MII\] cmp4\.ge\.or\.andcm p3,p2=r0,r4 + 576: 20 04 10 06 65 40 cmp4\.le\.and p2,p3=r0,r4 + 57c: 08 20 0c da cmp4\.le\.or p2,p3=r0,r4 + 580: 00 10 02 08 83 3a \[MII\] cmp4\.le\.or\.andcm p2,p3=r0,r4 + 586: 20 00 10 06 6d 40 cmp4\.gt\.or p2,p3=r0,r4 + 58c: 00 20 0c ca cmp4\.gt\.and p2,p3=r0,r4 + 590: 00 18 00 08 82 3a \[MII\] cmp4\.gt\.or\.andcm p3,p2=r0,r4 + 596: 20 00 10 06 65 40 cmp4\.gt\.and p2,p3=r0,r4 + 59c: 00 20 0c da cmp4\.gt\.or p2,p3=r0,r4 + 5a0: 00 10 00 08 83 3a \[MII\] cmp4\.gt\.or\.andcm p2,p3=r0,r4 + 5a6: 20 04 10 06 6d 40 cmp4\.le\.or p2,p3=r0,r4 + 5ac: 08 20 0c ca cmp4\.le\.and p2,p3=r0,r4 + 5b0: 00 18 02 08 82 3a \[MII\] cmp4\.le\.or\.andcm p3,p2=r0,r4 + 5b6: 20 00 10 86 65 40 cmp4\.ge\.and p2,p3=r0,r4 + 5bc: 00 20 0c db cmp4\.ge\.or p2,p3=r0,r4 + 5c0: 00 10 00 08 c3 3a \[MII\] cmp4\.ge\.or\.andcm p2,p3=r0,r4 + 5c6: 20 04 10 86 6d 40 cmp4\.lt\.or p2,p3=r0,r4 + 5cc: 08 20 0c cb cmp4\.lt\.and p2,p3=r0,r4 + 5d0: 01 18 02 08 c2 3a \[MII\] cmp4\.lt\.or\.andcm p3,p2=r0,r4 + 5d6: 00 00 00 02 00 00 nop\.i 0x0 + 5dc: 00 00 04 00 nop\.i 0x0;; diff --git a/gas/testsuite/gas/ia64/opc-a.pl b/gas/testsuite/gas/ia64/opc-a.pl new file mode 100644 index 0000000..afddf06 --- /dev/null +++ b/gas/testsuite/gas/ia64/opc-a.pl @@ -0,0 +1,141 @@ +$AT = '@'; +print <<END +.text + .type _start,${AT}function +_start: + + add r101 = r102, r103 +(p1) add r104 = r105, r106 + add r107 = r108, r109, 1 +(p2) add r110 = r111, r112, 1 + + adds r20 = 0, r10 +(p1) adds r21 = 1, r10 + adds r22 = -1, r10 + adds r23 = -0x2000, r10 +(p2) adds r24 = 0x1FFF, r10 + + addl r30 = 0, r1 + addl r31 = 1, r1 +(p1) addl r32 = -1, r1 + addl r33 = -0x2000, r1 + addl r34 = 0x1FFF, r1 + addl r35 = -0x200000, r1 + addl r36 = 0x1FFFFF, r1 + + add r11 = 0, r10 + add r12 = 0x1234, r10 + add r13 = 0x1234, r1 + add r14 = 0x12345, r1 + + addp4 r20 = r3, r10 +(p1) addp4 r21 = 1, r10 + addp4 r22 = -1, r10 + + sub r101 = r102, r103 +(p2) sub r110 = r111, r112, 1 + sub r120 = 0, r3 + sub r121 = 1, r3 + sub r122 = -1, r3 + sub r123 = -128, r3 + sub r124 = 127, r3 + + and r8 = r9, r10 +(p3) and r11 = -128, r12 + +(p4) or r8 = r9, r10 + or r11 = -128, r12 + + xor r8 = r9, r10 + xor r11 = -128, r12 + + andcm r8 = r9, r10 + andcm r11 = -128, r12 + + shladd r8 = r30, 1, r31 + shladd r9 = r30, 2, r31 + shladd r10 = r30, 3, r31 + shladd r11 = r30, 4, r31 + + shladdp4 r8 = r30, 1, r31 + shladdp4 r9 = r30, 2, r31 + shladdp4 r10 = r30, 3, r31 + shladdp4 r11 = r30, 4, r31 + + padd1 r10 = r30, r31 + padd1.sss r11 = r30, r31 + padd1.uus r12 = r30, r31 + padd1.uuu r13 = r30, r31 + padd2 r14 = r30, r31 + padd2.sss r15 = r30, r31 + padd2.uus r16 = r30, r31 + padd2.uuu r17 = r30, r31 + padd4 r18 = r30, r31 + + psub1 r10 = r30, r31 + psub1.sss r11 = r30, r31 + psub1.uus r12 = r30, r31 + psub1.uuu r13 = r30, r31 + psub2 r14 = r30, r31 + psub2.sss r15 = r30, r31 + psub2.uus r16 = r30, r31 + psub2.uuu r17 = r30, r31 + psub4 r18 = r30, r31 + + pavg1 r10 = r30, r31 + pavg1.raz r10 = r30, r31 + pavg2 r10 = r30, r31 + pavg2.raz r10 = r30, r31 + + pavgsub1 r10 = r30, r31 + pavgsub2 r10 = r30, r31 + + pcmp1.eq r10 = r30, r31 + pcmp2.eq r10 = r30, r31 + pcmp4.eq r10 = r30, r31 + pcmp1.gt r10 = r30, r31 + pcmp2.gt r10 = r30, r31 + pcmp4.gt r10 = r30, r31 + + pshladd2 r10 = r11, 1, r12 + pshladd2 r10 = r11, 3, r12 + + pshradd2 r10 = r11, 1, r12 + pshradd2 r10 = r11, 2, r12 + +END +; + +@cmp2 = ( ".eq", ".ne" ); +@cmp6 = ( @cmp2, ".lt", ".le", ".gt", ".ge" ); +@cmp10 = ( @cmp6, ".ltu", ".leu", ".gtu", ".geu" ); + +@ctype = ( ".and", ".or", ".or.andcm", ".orcm", ".andcm", ".and.orcm" ); + +foreach $C ( "cmp", "cmp4" ) { + foreach $u ( "", ".unc" ) { + foreach $i (@cmp10) { + print "\t${C}${i}${u} p2, p3 = r3, r4\n"; + print "\t${C}${i}${u} p2, p3 = 3, r4\n"; + } + print "\n"; + } + + foreach $i (@cmp2) { + foreach $c (@ctype) { + print "\t${C}${i}${c} p2, p3 = r3, r4\n"; + print "\t${C}${i}${c} p2, p3 = 3, r4\n"; + } + print "\n"; + } + + foreach $i (@cmp6) { + foreach $c (@ctype) { + print "\t${C}${i}${c} p2, p3 = r0, r4\n"; + } + print "\n"; + } +} + +# Pad to a bundle boundary with known nops. +print "nop.i 0; nop.i 0\n"; diff --git a/gas/testsuite/gas/ia64/opc-a.s b/gas/testsuite/gas/ia64/opc-a.s new file mode 100644 index 0000000..0074d9e --- /dev/null +++ b/gas/testsuite/gas/ia64/opc-a.s @@ -0,0 +1,324 @@ +.text + .type _start,@function +_start: + + add r101 = r102, r103 +(p1) add r104 = r105, r106 + add r107 = r108, r109, 1 +(p2) add r110 = r111, r112, 1 + + adds r20 = 0, r10 +(p1) adds r21 = 1, r10 + adds r22 = -1, r10 + adds r23 = -0x2000, r10 +(p2) adds r24 = 0x1FFF, r10 + + addl r30 = 0, r1 + addl r31 = 1, r1 +(p1) addl r32 = -1, r1 + addl r33 = -0x2000, r1 + addl r34 = 0x1FFF, r1 + addl r35 = -0x200000, r1 + addl r36 = 0x1FFFFF, r1 + + add r11 = 0, r10 + add r12 = 0x1234, r10 + add r13 = 0x1234, r1 + add r14 = 0x12345, r1 + + addp4 r20 = r3, r10 +(p1) addp4 r21 = 1, r10 + addp4 r22 = -1, r10 + + sub r101 = r102, r103 +(p2) sub r110 = r111, r112, 1 + sub r120 = 0, r3 + sub r121 = 1, r3 + sub r122 = -1, r3 + sub r123 = -128, r3 + sub r124 = 127, r3 + + and r8 = r9, r10 +(p3) and r11 = -128, r12 + +(p4) or r8 = r9, r10 + or r11 = -128, r12 + + xor r8 = r9, r10 + xor r11 = -128, r12 + + andcm r8 = r9, r10 + andcm r11 = -128, r12 + + shladd r8 = r30, 1, r31 + shladd r9 = r30, 2, r31 + shladd r10 = r30, 3, r31 + shladd r11 = r30, 4, r31 + + shladdp4 r8 = r30, 1, r31 + shladdp4 r9 = r30, 2, r31 + shladdp4 r10 = r30, 3, r31 + shladdp4 r11 = r30, 4, r31 + + padd1 r10 = r30, r31 + padd1.sss r11 = r30, r31 + padd1.uus r12 = r30, r31 + padd1.uuu r13 = r30, r31 + padd2 r14 = r30, r31 + padd2.sss r15 = r30, r31 + padd2.uus r16 = r30, r31 + padd2.uuu r17 = r30, r31 + padd4 r18 = r30, r31 + + psub1 r10 = r30, r31 + psub1.sss r11 = r30, r31 + psub1.uus r12 = r30, r31 + psub1.uuu r13 = r30, r31 + psub2 r14 = r30, r31 + psub2.sss r15 = r30, r31 + psub2.uus r16 = r30, r31 + psub2.uuu r17 = r30, r31 + psub4 r18 = r30, r31 + + pavg1 r10 = r30, r31 + pavg1.raz r10 = r30, r31 + pavg2 r10 = r30, r31 + pavg2.raz r10 = r30, r31 + + pavgsub1 r10 = r30, r31 + pavgsub2 r10 = r30, r31 + + pcmp1.eq r10 = r30, r31 + pcmp2.eq r10 = r30, r31 + pcmp4.eq r10 = r30, r31 + pcmp1.gt r10 = r30, r31 + pcmp2.gt r10 = r30, r31 + pcmp4.gt r10 = r30, r31 + + pshladd2 r10 = r11, 1, r12 + pshladd2 r10 = r11, 3, r12 + + pshradd2 r10 = r11, 1, r12 + pshradd2 r10 = r11, 2, r12 + + cmp.eq p2, p3 = r3, r4 + cmp.eq p2, p3 = 3, r4 + cmp.ne p2, p3 = r3, r4 + cmp.ne p2, p3 = 3, r4 + cmp.lt p2, p3 = r3, r4 + cmp.lt p2, p3 = 3, r4 + cmp.le p2, p3 = r3, r4 + cmp.le p2, p3 = 3, r4 + cmp.gt p2, p3 = r3, r4 + cmp.gt p2, p3 = 3, r4 + cmp.ge p2, p3 = r3, r4 + cmp.ge p2, p3 = 3, r4 + cmp.ltu p2, p3 = r3, r4 + cmp.ltu p2, p3 = 3, r4 + cmp.leu p2, p3 = r3, r4 + cmp.leu p2, p3 = 3, r4 + cmp.gtu p2, p3 = r3, r4 + cmp.gtu p2, p3 = 3, r4 + cmp.geu p2, p3 = r3, r4 + cmp.geu p2, p3 = 3, r4 + + cmp.eq.unc p2, p3 = r3, r4 + cmp.eq.unc p2, p3 = 3, r4 + cmp.ne.unc p2, p3 = r3, r4 + cmp.ne.unc p2, p3 = 3, r4 + cmp.lt.unc p2, p3 = r3, r4 + cmp.lt.unc p2, p3 = 3, r4 + cmp.le.unc p2, p3 = r3, r4 + cmp.le.unc p2, p3 = 3, r4 + cmp.gt.unc p2, p3 = r3, r4 + cmp.gt.unc p2, p3 = 3, r4 + cmp.ge.unc p2, p3 = r3, r4 + cmp.ge.unc p2, p3 = 3, r4 + cmp.ltu.unc p2, p3 = r3, r4 + cmp.ltu.unc p2, p3 = 3, r4 + cmp.leu.unc p2, p3 = r3, r4 + cmp.leu.unc p2, p3 = 3, r4 + cmp.gtu.unc p2, p3 = r3, r4 + cmp.gtu.unc p2, p3 = 3, r4 + cmp.geu.unc p2, p3 = r3, r4 + cmp.geu.unc p2, p3 = 3, r4 + + cmp.eq.and p2, p3 = r3, r4 + cmp.eq.and p2, p3 = 3, r4 + cmp.eq.or p2, p3 = r3, r4 + cmp.eq.or p2, p3 = 3, r4 + cmp.eq.or.andcm p2, p3 = r3, r4 + cmp.eq.or.andcm p2, p3 = 3, r4 + cmp.eq.orcm p2, p3 = r3, r4 + cmp.eq.orcm p2, p3 = 3, r4 + cmp.eq.andcm p2, p3 = r3, r4 + cmp.eq.andcm p2, p3 = 3, r4 + cmp.eq.and.orcm p2, p3 = r3, r4 + cmp.eq.and.orcm p2, p3 = 3, r4 + + cmp.ne.and p2, p3 = r3, r4 + cmp.ne.and p2, p3 = 3, r4 + cmp.ne.or p2, p3 = r3, r4 + cmp.ne.or p2, p3 = 3, r4 + cmp.ne.or.andcm p2, p3 = r3, r4 + cmp.ne.or.andcm p2, p3 = 3, r4 + cmp.ne.orcm p2, p3 = r3, r4 + cmp.ne.orcm p2, p3 = 3, r4 + cmp.ne.andcm p2, p3 = r3, r4 + cmp.ne.andcm p2, p3 = 3, r4 + cmp.ne.and.orcm p2, p3 = r3, r4 + cmp.ne.and.orcm p2, p3 = 3, r4 + + cmp.eq.and p2, p3 = r0, r4 + cmp.eq.or p2, p3 = r0, r4 + cmp.eq.or.andcm p2, p3 = r0, r4 + cmp.eq.orcm p2, p3 = r0, r4 + cmp.eq.andcm p2, p3 = r0, r4 + cmp.eq.and.orcm p2, p3 = r0, r4 + + cmp.ne.and p2, p3 = r0, r4 + cmp.ne.or p2, p3 = r0, r4 + cmp.ne.or.andcm p2, p3 = r0, r4 + cmp.ne.orcm p2, p3 = r0, r4 + cmp.ne.andcm p2, p3 = r0, r4 + cmp.ne.and.orcm p2, p3 = r0, r4 + + cmp.lt.and p2, p3 = r0, r4 + cmp.lt.or p2, p3 = r0, r4 + cmp.lt.or.andcm p2, p3 = r0, r4 + cmp.lt.orcm p2, p3 = r0, r4 + cmp.lt.andcm p2, p3 = r0, r4 + cmp.lt.and.orcm p2, p3 = r0, r4 + + cmp.le.and p2, p3 = r0, r4 + cmp.le.or p2, p3 = r0, r4 + cmp.le.or.andcm p2, p3 = r0, r4 + cmp.le.orcm p2, p3 = r0, r4 + cmp.le.andcm p2, p3 = r0, r4 + cmp.le.and.orcm p2, p3 = r0, r4 + + cmp.gt.and p2, p3 = r0, r4 + cmp.gt.or p2, p3 = r0, r4 + cmp.gt.or.andcm p2, p3 = r0, r4 + cmp.gt.orcm p2, p3 = r0, r4 + cmp.gt.andcm p2, p3 = r0, r4 + cmp.gt.and.orcm p2, p3 = r0, r4 + + cmp.ge.and p2, p3 = r0, r4 + cmp.ge.or p2, p3 = r0, r4 + cmp.ge.or.andcm p2, p3 = r0, r4 + cmp.ge.orcm p2, p3 = r0, r4 + cmp.ge.andcm p2, p3 = r0, r4 + cmp.ge.and.orcm p2, p3 = r0, r4 + + cmp4.eq p2, p3 = r3, r4 + cmp4.eq p2, p3 = 3, r4 + cmp4.ne p2, p3 = r3, r4 + cmp4.ne p2, p3 = 3, r4 + cmp4.lt p2, p3 = r3, r4 + cmp4.lt p2, p3 = 3, r4 + cmp4.le p2, p3 = r3, r4 + cmp4.le p2, p3 = 3, r4 + cmp4.gt p2, p3 = r3, r4 + cmp4.gt p2, p3 = 3, r4 + cmp4.ge p2, p3 = r3, r4 + cmp4.ge p2, p3 = 3, r4 + cmp4.ltu p2, p3 = r3, r4 + cmp4.ltu p2, p3 = 3, r4 + cmp4.leu p2, p3 = r3, r4 + cmp4.leu p2, p3 = 3, r4 + cmp4.gtu p2, p3 = r3, r4 + cmp4.gtu p2, p3 = 3, r4 + cmp4.geu p2, p3 = r3, r4 + cmp4.geu p2, p3 = 3, r4 + + cmp4.eq.unc p2, p3 = r3, r4 + cmp4.eq.unc p2, p3 = 3, r4 + cmp4.ne.unc p2, p3 = r3, r4 + cmp4.ne.unc p2, p3 = 3, r4 + cmp4.lt.unc p2, p3 = r3, r4 + cmp4.lt.unc p2, p3 = 3, r4 + cmp4.le.unc p2, p3 = r3, r4 + cmp4.le.unc p2, p3 = 3, r4 + cmp4.gt.unc p2, p3 = r3, r4 + cmp4.gt.unc p2, p3 = 3, r4 + cmp4.ge.unc p2, p3 = r3, r4 + cmp4.ge.unc p2, p3 = 3, r4 + cmp4.ltu.unc p2, p3 = r3, r4 + cmp4.ltu.unc p2, p3 = 3, r4 + cmp4.leu.unc p2, p3 = r3, r4 + cmp4.leu.unc p2, p3 = 3, r4 + cmp4.gtu.unc p2, p3 = r3, r4 + cmp4.gtu.unc p2, p3 = 3, r4 + cmp4.geu.unc p2, p3 = r3, r4 + cmp4.geu.unc p2, p3 = 3, r4 + + cmp4.eq.and p2, p3 = r3, r4 + cmp4.eq.and p2, p3 = 3, r4 + cmp4.eq.or p2, p3 = r3, r4 + cmp4.eq.or p2, p3 = 3, r4 + cmp4.eq.or.andcm p2, p3 = r3, r4 + cmp4.eq.or.andcm p2, p3 = 3, r4 + cmp4.eq.orcm p2, p3 = r3, r4 + cmp4.eq.orcm p2, p3 = 3, r4 + cmp4.eq.andcm p2, p3 = r3, r4 + cmp4.eq.andcm p2, p3 = 3, r4 + cmp4.eq.and.orcm p2, p3 = r3, r4 + cmp4.eq.and.orcm p2, p3 = 3, r4 + + cmp4.ne.and p2, p3 = r3, r4 + cmp4.ne.and p2, p3 = 3, r4 + cmp4.ne.or p2, p3 = r3, r4 + cmp4.ne.or p2, p3 = 3, r4 + cmp4.ne.or.andcm p2, p3 = r3, r4 + cmp4.ne.or.andcm p2, p3 = 3, r4 + cmp4.ne.orcm p2, p3 = r3, r4 + cmp4.ne.orcm p2, p3 = 3, r4 + cmp4.ne.andcm p2, p3 = r3, r4 + cmp4.ne.andcm p2, p3 = 3, r4 + cmp4.ne.and.orcm p2, p3 = r3, r4 + cmp4.ne.and.orcm p2, p3 = 3, r4 + + cmp4.eq.and p2, p3 = r0, r4 + cmp4.eq.or p2, p3 = r0, r4 + cmp4.eq.or.andcm p2, p3 = r0, r4 + cmp4.eq.orcm p2, p3 = r0, r4 + cmp4.eq.andcm p2, p3 = r0, r4 + cmp4.eq.and.orcm p2, p3 = r0, r4 + + cmp4.ne.and p2, p3 = r0, r4 + cmp4.ne.or p2, p3 = r0, r4 + cmp4.ne.or.andcm p2, p3 = r0, r4 + cmp4.ne.orcm p2, p3 = r0, r4 + cmp4.ne.andcm p2, p3 = r0, r4 + cmp4.ne.and.orcm p2, p3 = r0, r4 + + cmp4.lt.and p2, p3 = r0, r4 + cmp4.lt.or p2, p3 = r0, r4 + cmp4.lt.or.andcm p2, p3 = r0, r4 + cmp4.lt.orcm p2, p3 = r0, r4 + cmp4.lt.andcm p2, p3 = r0, r4 + cmp4.lt.and.orcm p2, p3 = r0, r4 + + cmp4.le.and p2, p3 = r0, r4 + cmp4.le.or p2, p3 = r0, r4 + cmp4.le.or.andcm p2, p3 = r0, r4 + cmp4.le.orcm p2, p3 = r0, r4 + cmp4.le.andcm p2, p3 = r0, r4 + cmp4.le.and.orcm p2, p3 = r0, r4 + + cmp4.gt.and p2, p3 = r0, r4 + cmp4.gt.or p2, p3 = r0, r4 + cmp4.gt.or.andcm p2, p3 = r0, r4 + cmp4.gt.orcm p2, p3 = r0, r4 + cmp4.gt.andcm p2, p3 = r0, r4 + cmp4.gt.and.orcm p2, p3 = r0, r4 + + cmp4.ge.and p2, p3 = r0, r4 + cmp4.ge.or p2, p3 = r0, r4 + cmp4.ge.or.andcm p2, p3 = r0, r4 + cmp4.ge.orcm p2, p3 = r0, r4 + cmp4.ge.andcm p2, p3 = r0, r4 + cmp4.ge.and.orcm p2, p3 = r0, r4 + +nop.i 0; nop.i 0 diff --git a/gas/testsuite/gas/ia64/opc-b.d b/gas/testsuite/gas/ia64/opc-b.d new file mode 100644 index 0000000..80fcfff --- /dev/null +++ b/gas/testsuite/gas/ia64/opc-b.d @@ -0,0 +1,1014 @@ +#objdump: -d +#name: ia64 opc-b + +.*: +file format .* + +Disassembly of section .text: + +0000000000000000 <.text>: + 0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 6: 00 f8 15 00 20 00 \(p02\) br\.cond\.sptk\.few 0x2bf0 + c: 00 00 00 40 br\.few 0x0;; + 10: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 16: 00 f0 15 00 22 00 \(p02\) br\.cond\.sptk\.few\.clr 0x2bf0 + 1c: f0 ff ff 4c br\.few\.clr 0x0;; + 20: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 26: 00 e8 15 00 20 00 \(p02\) br\.cond\.sptk\.few 0x2bf0 + 2c: e0 ff ff 48 br\.few 0x0;; + 30: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 36: 00 e0 15 00 22 00 \(p02\) br\.cond\.sptk\.few\.clr 0x2bf0 + 3c: d0 ff ff 4c br\.few\.clr 0x0;; + 40: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 46: 00 dc 15 00 20 00 \(p02\) br\.cond\.sptk\.many 0x2bf0 + 4c: c8 ff ff 48 br\.many 0x0;; + 50: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 56: 00 d4 15 00 22 00 \(p02\) br\.cond\.sptk\.many\.clr 0x2bf0 + 5c: b8 ff ff 4c br\.many\.clr 0x0;; + 60: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 66: 00 c8 15 80 20 00 \(p02\) br\.cond\.spnt\.few 0x2bf0 + 6c: a0 ff ff 49 br\.cond\.spnt\.few 0x0;; + 70: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 76: 00 c0 15 80 22 00 \(p02\) br\.cond\.spnt\.few\.clr 0x2bf0 + 7c: 90 ff ff 4d br\.cond\.spnt\.few\.clr 0x0;; + 80: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 86: 00 b8 15 80 20 00 \(p02\) br\.cond\.spnt\.few 0x2bf0 + 8c: 80 ff ff 49 br\.cond\.spnt\.few 0x0;; + 90: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 96: 00 b0 15 80 22 00 \(p02\) br\.cond\.spnt\.few\.clr 0x2bf0 + 9c: 70 ff ff 4d br\.cond\.spnt\.few\.clr 0x0;; + a0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + a6: 00 ac 15 80 20 00 \(p02\) br\.cond\.spnt\.many 0x2bf0 + ac: 68 ff ff 49 br\.cond\.spnt\.many 0x0;; + b0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + b6: 00 a4 15 80 22 00 \(p02\) br\.cond\.spnt\.many\.clr 0x2bf0 + bc: 58 ff ff 4d br\.cond\.spnt\.many\.clr 0x0;; + c0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + c6: 00 98 15 00 21 00 \(p02\) br\.cond\.dptk\.few 0x2bf0 + cc: 40 ff ff 4a br\.cond\.dptk\.few 0x0;; + d0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + d6: 00 90 15 00 23 00 \(p02\) br\.cond\.dptk\.few\.clr 0x2bf0 + dc: 30 ff ff 4e br\.cond\.dptk\.few\.clr 0x0;; + e0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + e6: 00 88 15 00 21 00 \(p02\) br\.cond\.dptk\.few 0x2bf0 + ec: 20 ff ff 4a br\.cond\.dptk\.few 0x0;; + f0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + f6: 00 80 15 00 23 00 \(p02\) br\.cond\.dptk\.few\.clr 0x2bf0 + fc: 10 ff ff 4e br\.cond\.dptk\.few\.clr 0x0;; + 100: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 106: 00 7c 15 00 21 00 \(p02\) br\.cond\.dptk\.many 0x2bf0 + 10c: 08 ff ff 4a br\.cond\.dptk\.many 0x0;; + 110: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 116: 00 74 15 00 23 00 \(p02\) br\.cond\.dptk\.many\.clr 0x2bf0 + 11c: f8 fe ff 4e br\.cond\.dptk\.many\.clr 0x0;; + 120: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 126: 00 68 15 80 21 00 \(p02\) br\.cond\.dpnt\.few 0x2bf0 + 12c: e0 fe ff 4b br\.cond\.dpnt\.few 0x0;; + 130: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 136: 00 60 15 80 23 00 \(p02\) br\.cond\.dpnt\.few\.clr 0x2bf0 + 13c: d0 fe ff 4f br\.cond\.dpnt\.few\.clr 0x0;; + 140: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 146: 00 58 15 80 21 00 \(p02\) br\.cond\.dpnt\.few 0x2bf0 + 14c: c0 fe ff 4b br\.cond\.dpnt\.few 0x0;; + 150: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 156: 00 50 15 80 23 00 \(p02\) br\.cond\.dpnt\.few\.clr 0x2bf0 + 15c: b0 fe ff 4f br\.cond\.dpnt\.few\.clr 0x0;; + 160: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 166: 00 4c 15 80 21 00 \(p02\) br\.cond\.dpnt\.many 0x2bf0 + 16c: a8 fe ff 4b br\.cond\.dpnt\.many 0x0;; + 170: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 176: 00 44 15 80 23 00 \(p02\) br\.cond\.dpnt\.many\.clr 0x2bf0 + 17c: 98 fe ff 4f br\.cond\.dpnt\.many\.clr 0x0;; + 180: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 186: 00 00 00 00 10 41 nop\.b 0x0 + 18c: 70 2a 00 40 \(p02\) br\.wexit\.sptk\.few 0x2bf0;; + 190: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 196: 00 00 00 00 10 40 nop\.b 0x0 + 19c: 60 2a 00 40 br\.wexit\.sptk\.few 0x2bf0;; + 1a0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 1a6: 00 00 00 00 10 41 nop\.b 0x0 + 1ac: 50 2a 00 44 \(p02\) br\.wexit\.sptk\.few\.clr 0x2bf0;; + 1b0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 1b6: 00 00 00 00 10 40 nop\.b 0x0 + 1bc: 40 2a 00 44 br\.wexit\.sptk\.few\.clr 0x2bf0;; + 1c0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 1c6: 00 00 00 00 10 41 nop\.b 0x0 + 1cc: 30 2a 00 40 \(p02\) br\.wexit\.sptk\.few 0x2bf0;; + 1d0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 1d6: 00 00 00 00 10 40 nop\.b 0x0 + 1dc: 20 2a 00 40 br\.wexit\.sptk\.few 0x2bf0;; + 1e0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 1e6: 00 00 00 00 10 41 nop\.b 0x0 + 1ec: 10 2a 00 44 \(p02\) br\.wexit\.sptk\.few\.clr 0x2bf0;; + 1f0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 1f6: 00 00 00 00 10 40 nop\.b 0x0 + 1fc: 00 2a 00 44 br\.wexit\.sptk\.few\.clr 0x2bf0;; + 200: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 206: 00 00 00 00 10 41 nop\.b 0x0 + 20c: f8 29 00 40 \(p02\) br\.wexit\.sptk\.many 0x2bf0;; + 210: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 216: 00 00 00 00 10 40 nop\.b 0x0 + 21c: e8 29 00 40 br\.wexit\.sptk\.many 0x2bf0;; + 220: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 226: 00 00 00 00 10 41 nop\.b 0x0 + 22c: d8 29 00 44 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08 \[BBB\] nop\.b 0x0 + fc6: 00 00 00 00 10 20 nop\.b 0x0 + fcc: 20 00 80 02 br\.ia\.dptk\.few b2;; + fd0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + fd6: 00 00 00 00 10 20 nop\.b 0x0 + fdc: 20 00 80 06 br\.ia\.dptk\.few\.clr b2;; + fe0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + fe6: 00 00 00 00 10 20 nop\.b 0x0 + fec: 20 00 80 02 br\.ia\.dptk\.few b2;; + ff0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + ff6: 00 00 00 00 10 20 nop\.b 0x0 + ffc: 20 00 80 06 br\.ia\.dptk\.few\.clr b2;; + 1000: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 1006: 00 00 00 00 10 20 nop\.b 0x0 + 100c: 28 00 80 02 br\.ia\.dptk\.many b2;; + 1010: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 1016: 00 00 00 00 10 20 nop\.b 0x0 + 101c: 28 00 80 06 br\.ia\.dptk\.many\.clr b2;; + 1020: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 1026: 00 00 00 00 10 20 nop\.b 0x0 + 102c: 20 00 80 03 br\.ia\.dpnt\.few b2;; + 1030: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 1036: 00 00 00 00 10 20 nop\.b 0x0 + 103c: 20 00 80 07 br\.ia\.dpnt\.few\.clr b2;; + 1040: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 1046: 00 00 00 00 10 20 nop\.b 0x0 + 104c: 20 00 80 03 br\.ia\.dpnt\.few b2;; + 1050: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 1056: 00 00 00 00 10 20 nop\.b 0x0 + 105c: 20 00 80 07 br\.ia\.dpnt\.few\.clr b2;; + 1060: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 1066: 00 00 00 00 10 20 nop\.b 0x0 + 106c: 28 00 80 03 br\.ia\.dpnt\.many b2;; + 1070: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 1076: 00 00 00 00 10 20 nop\.b 0x0 + 107c: 28 00 80 07 br\.ia\.dpnt\.many\.clr b2;; + 1080: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1086: 40 10 00 42 00 80 \(p02\) br\.ret\.sptk\.few b2 + 108c: 20 00 84 00 br\.ret\.sptk\.few b2;; + 1090: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1096: 40 10 00 42 02 80 \(p02\) br\.ret\.sptk\.few\.clr b2 + 109c: 20 00 84 04 br\.ret\.sptk\.few\.clr b2;; + 10a0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 10a6: 40 10 00 42 00 80 \(p02\) br\.ret\.sptk\.few b2 + 10ac: 20 00 84 00 br\.ret\.sptk\.few b2;; + 10b0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 10b6: 40 10 00 42 02 80 \(p02\) br\.ret\.sptk\.few\.clr b2 + 10bc: 20 00 84 04 br\.ret\.sptk\.few\.clr b2;; + 10c0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 10c6: 40 14 00 42 00 80 \(p02\) br\.ret\.sptk\.many b2 + 10cc: 28 00 84 00 br\.ret\.sptk\.many b2;; + 10d0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 10d6: 40 14 00 42 02 80 \(p02\) br\.ret\.sptk\.many\.clr b2 + 10dc: 28 00 84 04 br\.ret\.sptk\.many\.clr b2;; + 10e0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 10e6: 40 10 00 c2 00 80 \(p02\) br\.ret\.spnt\.few b2 + 10ec: 20 00 84 01 br\.ret\.spnt\.few b2;; + 10f0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 10f6: 40 10 00 c2 02 80 \(p02\) br\.ret\.spnt\.few\.clr b2 + 10fc: 20 00 84 05 br\.ret\.spnt\.few\.clr b2;; + 1100: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1106: 40 10 00 c2 00 80 \(p02\) br\.ret\.spnt\.few b2 + 110c: 20 00 84 01 br\.ret\.spnt\.few b2;; + 1110: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1116: 40 10 00 c2 02 80 \(p02\) br\.ret\.spnt\.few\.clr b2 + 111c: 20 00 84 05 br\.ret\.spnt\.few\.clr b2;; + 1120: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1126: 40 14 00 c2 00 80 \(p02\) br\.ret\.spnt\.many b2 + 112c: 28 00 84 01 br\.ret\.spnt\.many b2;; + 1130: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1136: 40 14 00 c2 02 80 \(p02\) br\.ret\.spnt\.many\.clr b2 + 113c: 28 00 84 05 br\.ret\.spnt\.many\.clr b2;; + 1140: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1146: 40 10 00 42 01 80 \(p02\) br\.ret\.dptk\.few b2 + 114c: 20 00 84 02 br\.ret\.dptk\.few b2;; + 1150: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1156: 40 10 00 42 03 80 \(p02\) br\.ret\.dptk\.few\.clr b2 + 115c: 20 00 84 06 br\.ret\.dptk\.few\.clr b2;; + 1160: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1166: 40 10 00 42 01 80 \(p02\) br\.ret\.dptk\.few b2 + 116c: 20 00 84 02 br\.ret\.dptk\.few b2;; + 1170: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1176: 40 10 00 42 03 80 \(p02\) br\.ret\.dptk\.few\.clr b2 + 117c: 20 00 84 06 br\.ret\.dptk\.few\.clr b2;; + 1180: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1186: 40 14 00 42 01 80 \(p02\) br\.ret\.dptk\.many b2 + 118c: 28 00 84 02 br\.ret\.dptk\.many b2;; + 1190: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1196: 40 14 00 42 03 80 \(p02\) br\.ret\.dptk\.many\.clr b2 + 119c: 28 00 84 06 br\.ret\.dptk\.many\.clr b2;; + 11a0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 11a6: 40 10 00 c2 01 80 \(p02\) br\.ret\.dpnt\.few b2 + 11ac: 20 00 84 03 br\.ret\.dpnt\.few b2;; + 11b0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 11b6: 40 10 00 c2 03 80 \(p02\) br\.ret\.dpnt\.few\.clr b2 + 11bc: 20 00 84 07 br\.ret\.dpnt\.few\.clr b2;; + 11c0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 11c6: 40 10 00 c2 01 80 \(p02\) br\.ret\.dpnt\.few b2 + 11cc: 20 00 84 03 br\.ret\.dpnt\.few b2;; + 11d0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 11d6: 40 10 00 c2 03 80 \(p02\) br\.ret\.dpnt\.few\.clr b2 + 11dc: 20 00 84 07 br\.ret\.dpnt\.few\.clr b2;; + 11e0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 11e6: 40 14 00 c2 01 80 \(p02\) br\.ret\.dpnt\.many b2 + 11ec: 28 00 84 03 br\.ret\.dpnt\.many b2;; + 11f0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 11f6: 40 14 00 c2 03 80 \(p02\) br\.ret\.dpnt\.many\.clr b2 + 11fc: 28 00 84 07 br\.ret\.dpnt\.many\.clr b2;; + 1200: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1206: 00 10 00 00 08 00 \(p02\) br\.call\.sptk\.few b0=b2 + 120c: 20 00 00 10 br\.call\.sptk\.few b0=b2;; + 1210: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1216: 00 10 00 00 0a 00 \(p02\) br\.call\.sptk\.few\.clr b0=b2 + 121c: 20 00 00 14 br\.call\.sptk\.few\.clr b0=b2;; + 1220: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1226: 00 10 00 00 08 00 \(p02\) br\.call\.sptk\.few b0=b2 + 122c: 20 00 00 10 br\.call\.sptk\.few b0=b2;; + 1230: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1236: 00 10 00 00 0a 00 \(p02\) br\.call\.sptk\.few\.clr b0=b2 + 123c: 20 00 00 14 br\.call\.sptk\.few\.clr b0=b2;; + 1240: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1246: 00 14 00 00 08 00 \(p02\) br\.call\.sptk\.many b0=b2 + 124c: 28 00 00 10 br\.call\.sptk\.many b0=b2;; + 1250: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1256: 00 14 00 00 0a 00 \(p02\) br\.call\.sptk\.many\.clr b0=b2 + 125c: 28 00 00 14 br\.call\.sptk\.many\.clr b0=b2;; + 1260: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1266: 00 10 00 80 08 00 \(p02\) br\.call\.spnt\.few b0=b2 + 126c: 20 00 00 11 br\.call\.spnt\.few b0=b2;; + 1270: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1276: 00 10 00 80 0a 00 \(p02\) br\.call\.spnt\.few\.clr b0=b2 + 127c: 20 00 00 15 br\.call\.spnt\.few\.clr b0=b2;; + 1280: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1286: 00 10 00 80 08 00 \(p02\) br\.call\.spnt\.few b0=b2 + 128c: 20 00 00 11 br\.call\.spnt\.few b0=b2;; + 1290: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1296: 00 10 00 80 0a 00 \(p02\) br\.call\.spnt\.few\.clr b0=b2 + 129c: 20 00 00 15 br\.call\.spnt\.few\.clr b0=b2;; + 12a0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 12a6: 00 14 00 80 08 00 \(p02\) br\.call\.spnt\.many b0=b2 + 12ac: 28 00 00 11 br\.call\.spnt\.many b0=b2;; + 12b0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 12b6: 00 14 00 80 0a 00 \(p02\) br\.call\.spnt\.many\.clr b0=b2 + 12bc: 28 00 00 15 br\.call\.spnt\.many\.clr b0=b2;; + 12c0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 12c6: 00 10 00 00 09 00 \(p02\) br\.call\.dptk\.few b0=b2 + 12cc: 20 00 00 12 br\.call\.dptk\.few b0=b2;; + 12d0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 12d6: 00 10 00 00 0b 00 \(p02\) br\.call\.dptk\.few\.clr b0=b2 + 12dc: 20 00 00 16 br\.call\.dptk\.few\.clr b0=b2;; + 12e0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 12e6: 00 10 00 00 09 00 \(p02\) br\.call\.dptk\.few b0=b2 + 12ec: 20 00 00 12 br\.call\.dptk\.few b0=b2;; + 12f0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 12f6: 00 10 00 00 0b 00 \(p02\) br\.call\.dptk\.few\.clr b0=b2 + 12fc: 20 00 00 16 br\.call\.dptk\.few\.clr b0=b2;; + 1300: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1306: 00 14 00 00 09 00 \(p02\) br\.call\.dptk\.many b0=b2 + 130c: 28 00 00 12 br\.call\.dptk\.many b0=b2;; + 1310: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1316: 00 14 00 00 0b 00 \(p02\) br\.call\.dptk\.many\.clr b0=b2 + 131c: 28 00 00 16 br\.call\.dptk\.many\.clr b0=b2;; + 1320: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1326: 00 10 00 80 09 00 \(p02\) br\.call\.dpnt\.few b0=b2 + 132c: 20 00 00 13 br\.call\.dpnt\.few b0=b2;; + 1330: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1336: 00 10 00 80 0b 00 \(p02\) br\.call\.dpnt\.few\.clr b0=b2 + 133c: 20 00 00 17 br\.call\.dpnt\.few\.clr b0=b2;; + 1340: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1346: 00 10 00 80 09 00 \(p02\) br\.call\.dpnt\.few b0=b2 + 134c: 20 00 00 13 br\.call\.dpnt\.few b0=b2;; + 1350: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1356: 00 10 00 80 0b 00 \(p02\) br\.call\.dpnt\.few\.clr b0=b2 + 135c: 20 00 00 17 br\.call\.dpnt\.few\.clr b0=b2;; + 1360: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1366: 00 14 00 80 09 00 \(p02\) br\.call\.dpnt\.many b0=b2 + 136c: 28 00 00 13 br\.call\.dpnt\.many b0=b2;; + 1370: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 + 1376: 00 14 00 80 0b 00 \(p02\) br\.call\.dpnt\.many\.clr b0=b2 + 137c: 28 00 00 17 br\.call\.dpnt\.many\.clr b0=b2;; + 1380: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 + 1386: 00 00 00 00 10 40 nop\.b 0x0 + 138c: 80 ec ff 78 brp\.sptk 0x0,0x13a0;; + 1390: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 + 1396: 00 00 00 00 10 20 nop\.b 0x0 + 139c: 70 ec ff 7c brp\.sptk\.imp 0x0,0x13a0;; + 13a0: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 + 13a6: 00 00 00 00 10 44 nop\.b 0x0 + 13ac: 60 ec ff 78 brp\.loop 0x0,0x13c0;; + 13b0: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 + 13b6: 00 00 00 00 10 24 nop\.b 0x0 + 13bc: 50 ec ff 7c brp\.loop\.imp 0x0,0x13c0;; + 13c0: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 + 13c6: 00 00 00 00 10 48 nop\.b 0x0 + 13cc: 40 ec ff 78 brp\.dptk 0x0,0x13e0;; + 13d0: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 + 13d6: 00 00 00 00 10 28 nop\.b 0x0 + 13dc: 30 ec ff 7c brp\.dptk\.imp 0x0,0x13e0;; + 13e0: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 + 13e6: 00 00 00 00 10 4c nop\.b 0x0 + 13ec: 20 ec ff 78 brp\.exit 0x0,0x1400;; + 13f0: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 + 13f6: 00 00 00 00 10 2c nop\.b 0x0 + 13fc: 10 ec ff 7c brp\.exit\.imp 0x0,0x1400;; + 1400: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 + 1406: 00 00 00 00 10 40 nop\.b 0x0 + 140c: 30 00 40 20 brp\.sptk b3,0x1420;; + 1410: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 + 1416: 00 00 00 00 10 20 nop\.b 0x0 + 141c: 30 00 40 24 brp\.sptk\.imp b3,0x1420;; + 1420: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 + 1426: 00 00 00 00 10 48 nop\.b 0x0 + 142c: 30 00 40 20 brp\.dptk b3,0x1440;; + 1430: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 + 1436: 00 00 00 00 10 28 nop\.b 0x0 + 143c: 30 00 40 24 brp\.dptk.imp b3,0x1440;; + 1440: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 + 1446: 00 00 00 00 10 40 nop\.b 0x0 + 144c: 30 00 44 20 brp\.ret\.sptk b3,0x1460;; + 1450: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 + 1456: 00 00 00 00 10 20 nop\.b 0x0 + 145c: 30 00 44 24 brp\.ret\.sptk\.imp b3,0x1460;; + 1460: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 + 1466: 00 00 00 00 10 48 nop\.b 0x0 + 146c: 30 00 44 20 brp\.ret\.dptk b3,0x1480;; + 1470: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 + 1476: 00 00 00 00 10 28 nop\.b 0x0 + 147c: 30 00 44 24 brp\.ret\.dptk.imp b3,0x1480;; + \.\.\. + 2b80: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 2b86: 00 00 00 00 10 00 nop\.b 0x0 + 2b8c: 00 00 08 00 cover;; + 2b90: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 2b96: 00 00 00 00 10 00 nop\.b 0x0 + 2b9c: 00 00 10 00 clrrrb;; + 2ba0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 2ba6: 00 00 00 00 10 00 nop\.b 0x0 + 2bac: 00 00 14 00 clrrrb\.pr;; + 2bb0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 2bb6: 00 00 00 00 10 00 nop\.b 0x0 + 2bbc: 00 00 20 00 rfi;; + 2bc0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 2bc6: 00 00 00 00 10 00 nop\.b 0x0 + 2bcc: 00 00 30 00 bsw\.0;; + 2bd0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 2bd6: 00 00 00 00 10 00 nop\.b 0x0 + 2bdc: 00 00 34 00 bsw\.1;; + 2be0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 + 2be6: 00 00 00 00 10 00 nop\.b 0x0 + 2bec: 00 00 40 00 epc;; diff --git a/gas/testsuite/gas/ia64/opc-b.pl b/gas/testsuite/gas/ia64/opc-b.pl new file mode 100644 index 0000000..bdfdd36 --- /dev/null +++ b/gas/testsuite/gas/ia64/opc-b.pl @@ -0,0 +1,95 @@ +@ph = ( "", ".few", ".many" ); +@bwh = ( ".sptk", ".spnt", ".dptk", ".dpnt" ); +@dh = ( "", ".clr" ); + +@iprel = ( ".cond", ".wexit", ".wtop", ".cloop", ".cexit", ".ctop", ".call" ); +@indir = ( ".cond", ".ia", ".ret", ".call" ); +%noqual = ( ".ia", 1, ".cloop", 1, ".ctop", 1, ".cexit", 1 ); +%slottwo = ( ".cloop", 1, ".ctop", 1, ".cexit", 1, ".wtop", 1, ".wexit", 1 ); + +print ".L0:\n\n"; + +foreach $i (@iprel) { + $call = ($i eq ".call" ? "b0 = " : ""); + foreach $b (@bwh) { + foreach $p (@ph) { + foreach $d (@dh) { + if ($slottwo{$i}) { + if (!$noqual{$i}) { + print ("\t{ .bbb; (p2) br${i}${b}${p}${d} ${call}.L1 ;; }\n"); + } + print ("\t{ .bbb; br${i}${b}${p}${d} ${call}.L1 ;; }\n"); + } else { + print ("\t{ .bbb; nop.b 0\n"); + if (!$noqual{$i}) { + print ("(p2)\tbr${i}${b}${p}${d} ${call}.L1\n"); + } else { + print ("\tnop.b 0\n"); + } + print ("\tbr${i}${b}${p}${d} ${call}.L0\n"); + print ("\t;; }\n"); + } + } + } + } + print "\n"; +} + +foreach $i (@indir) { + $call = ($i eq ".call" ? "b0 = " : ""); + foreach $b (@bwh) { + foreach $p (@ph) { + foreach $d (@dh) { + print ("\t{ .bbb; nop.b 0;\n"); + if (!$noqual{$i}) { + print ("(p2)\tbr${i}${b}${p}${d} ${call}b2\n"); + } else { + print ("\tnop.b 0\n"); + } + print ("\tbr${i}${b}${p}${d} ${call}b2\n"); + print ("\t;; }\n"); + } + } + } + print "\n"; +} + +@ih = ( "", ".imp" ); +@ipwh = ( ".sptk", ".loop", ".dptk", ".exit" ); +@indwh = ( ".sptk", ".dptk" ); + +$CTR = 2; + +foreach $w (@ipwh) { + foreach $i (@ih) { + print ("\t{ .bbb; break.b 0; nop.b 0\n"); + print ("\tbrp${w}${i} .L0, .L${CTR}\n"); + print ("\t;; }\n"); + } + print (".L${CTR}:\n"); + ++$CTR; +} + +print "\n"; + +foreach $b ("", ".ret") { + foreach $w (@indwh) { + foreach $i (@ih) { + print ("\t{ .bbb; break.b 0; nop.b 0\n"); + print ("\tbrp${b}${w}${i} b3, .L${CTR}\n"); + print ("\t;; }\n"); + } + print (".L${CTR}:\n"); + ++$CTR; + } + print "\n"; +} + +print ".space 5888\n"; + +@last = ( "cover", "clrrrb", "clrrrb.pr", "rfi", "bsw.0", "bsw.1", "epc" ); +foreach $i (@last) { + print "\t{ .bbb; nop.b 0; nop.b 0; $i ;; }\n"; +} + +print "\n.L1:\n"; diff --git a/gas/testsuite/gas/ia64/opc-b.s b/gas/testsuite/gas/ia64/opc-b.s new file mode 100644 index 0000000..00c7769 --- /dev/null +++ b/gas/testsuite/gas/ia64/opc-b.s @@ -0,0 +1,826 @@ +.L0: + + { .bbb; nop.b 0 +(p2) br.cond.sptk .L1 + br.cond.sptk .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.sptk.clr .L1 + br.cond.sptk.clr .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.sptk.few .L1 + br.cond.sptk.few .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.sptk.few.clr .L1 + br.cond.sptk.few.clr .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.sptk.many .L1 + br.cond.sptk.many .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.sptk.many.clr .L1 + br.cond.sptk.many.clr .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.spnt .L1 + br.cond.spnt .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.spnt.clr .L1 + br.cond.spnt.clr .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.spnt.few .L1 + br.cond.spnt.few .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.spnt.few.clr .L1 + br.cond.spnt.few.clr .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.spnt.many .L1 + br.cond.spnt.many .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.spnt.many.clr .L1 + br.cond.spnt.many.clr .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.dptk .L1 + br.cond.dptk .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.dptk.clr .L1 + br.cond.dptk.clr .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.dptk.few .L1 + br.cond.dptk.few .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.dptk.few.clr .L1 + br.cond.dptk.few.clr .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.dptk.many .L1 + br.cond.dptk.many .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.dptk.many.clr .L1 + br.cond.dptk.many.clr .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.dpnt .L1 + br.cond.dpnt .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.dpnt.clr .L1 + br.cond.dpnt.clr .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.dpnt.few .L1 + br.cond.dpnt.few .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.dpnt.few.clr .L1 + br.cond.dpnt.few.clr .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.dpnt.many .L1 + br.cond.dpnt.many .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.cond.dpnt.many.clr .L1 + br.cond.dpnt.many.clr .L0 + ;; } + + { .bbb; (p2) br.wexit.sptk .L1 ;; } + { .bbb; br.wexit.sptk .L1 ;; } + { .bbb; (p2) br.wexit.sptk.clr .L1 ;; } + { .bbb; br.wexit.sptk.clr .L1 ;; } + { .bbb; (p2) br.wexit.sptk.few .L1 ;; } + { .bbb; br.wexit.sptk.few .L1 ;; } + { .bbb; (p2) br.wexit.sptk.few.clr .L1 ;; } + { .bbb; br.wexit.sptk.few.clr .L1 ;; } + { .bbb; (p2) br.wexit.sptk.many .L1 ;; } + { .bbb; br.wexit.sptk.many .L1 ;; } + { .bbb; (p2) br.wexit.sptk.many.clr .L1 ;; } + { .bbb; br.wexit.sptk.many.clr .L1 ;; } + { .bbb; (p2) br.wexit.spnt .L1 ;; } + { .bbb; br.wexit.spnt .L1 ;; } + { .bbb; (p2) br.wexit.spnt.clr .L1 ;; } + { .bbb; br.wexit.spnt.clr .L1 ;; } + { .bbb; (p2) br.wexit.spnt.few .L1 ;; } + { .bbb; br.wexit.spnt.few .L1 ;; } + { .bbb; (p2) br.wexit.spnt.few.clr .L1 ;; } + { .bbb; br.wexit.spnt.few.clr .L1 ;; } + { .bbb; (p2) br.wexit.spnt.many .L1 ;; } + { .bbb; br.wexit.spnt.many .L1 ;; } + { .bbb; (p2) br.wexit.spnt.many.clr .L1 ;; } + { .bbb; br.wexit.spnt.many.clr .L1 ;; } + { .bbb; (p2) br.wexit.dptk .L1 ;; } + { .bbb; br.wexit.dptk .L1 ;; } + { .bbb; (p2) br.wexit.dptk.clr .L1 ;; } + { .bbb; br.wexit.dptk.clr .L1 ;; } + { .bbb; (p2) br.wexit.dptk.few .L1 ;; } + { .bbb; br.wexit.dptk.few .L1 ;; } + { .bbb; (p2) br.wexit.dptk.few.clr .L1 ;; } + { .bbb; br.wexit.dptk.few.clr .L1 ;; } + { .bbb; (p2) br.wexit.dptk.many .L1 ;; } + { .bbb; br.wexit.dptk.many .L1 ;; } + { .bbb; (p2) br.wexit.dptk.many.clr .L1 ;; } + { .bbb; br.wexit.dptk.many.clr .L1 ;; } + { .bbb; (p2) br.wexit.dpnt .L1 ;; } + { .bbb; br.wexit.dpnt .L1 ;; } + { .bbb; (p2) br.wexit.dpnt.clr .L1 ;; } + { .bbb; br.wexit.dpnt.clr .L1 ;; } + { .bbb; (p2) br.wexit.dpnt.few .L1 ;; } + { .bbb; br.wexit.dpnt.few .L1 ;; } + { .bbb; (p2) br.wexit.dpnt.few.clr .L1 ;; } + { .bbb; br.wexit.dpnt.few.clr .L1 ;; } + { .bbb; (p2) br.wexit.dpnt.many .L1 ;; } + { .bbb; br.wexit.dpnt.many .L1 ;; } + { .bbb; (p2) br.wexit.dpnt.many.clr .L1 ;; } + { .bbb; br.wexit.dpnt.many.clr .L1 ;; } + + { .bbb; (p2) br.wtop.sptk .L1 ;; } + { .bbb; br.wtop.sptk .L1 ;; } + { .bbb; (p2) br.wtop.sptk.clr .L1 ;; } + { .bbb; br.wtop.sptk.clr .L1 ;; } + { .bbb; (p2) br.wtop.sptk.few .L1 ;; } + { .bbb; br.wtop.sptk.few .L1 ;; } + { .bbb; (p2) br.wtop.sptk.few.clr .L1 ;; } + { .bbb; br.wtop.sptk.few.clr .L1 ;; } + { .bbb; (p2) br.wtop.sptk.many .L1 ;; } + { .bbb; br.wtop.sptk.many .L1 ;; } + { .bbb; (p2) br.wtop.sptk.many.clr .L1 ;; } + { .bbb; br.wtop.sptk.many.clr .L1 ;; } + { .bbb; (p2) br.wtop.spnt .L1 ;; } + { .bbb; br.wtop.spnt .L1 ;; } + { .bbb; (p2) br.wtop.spnt.clr .L1 ;; } + { .bbb; br.wtop.spnt.clr .L1 ;; } + { .bbb; (p2) br.wtop.spnt.few .L1 ;; } + { .bbb; br.wtop.spnt.few .L1 ;; } + { .bbb; (p2) br.wtop.spnt.few.clr .L1 ;; } + { .bbb; br.wtop.spnt.few.clr .L1 ;; } + { .bbb; (p2) br.wtop.spnt.many .L1 ;; } + { .bbb; br.wtop.spnt.many .L1 ;; } + { .bbb; (p2) br.wtop.spnt.many.clr .L1 ;; } + { .bbb; br.wtop.spnt.many.clr .L1 ;; } + { .bbb; (p2) br.wtop.dptk .L1 ;; } + { .bbb; br.wtop.dptk .L1 ;; } + { .bbb; (p2) br.wtop.dptk.clr .L1 ;; } + { .bbb; br.wtop.dptk.clr .L1 ;; } + { .bbb; (p2) br.wtop.dptk.few .L1 ;; } + { .bbb; br.wtop.dptk.few .L1 ;; } + { .bbb; (p2) br.wtop.dptk.few.clr .L1 ;; } + { .bbb; br.wtop.dptk.few.clr .L1 ;; } + { .bbb; (p2) br.wtop.dptk.many .L1 ;; } + { .bbb; br.wtop.dptk.many .L1 ;; } + { .bbb; (p2) br.wtop.dptk.many.clr .L1 ;; } + { .bbb; br.wtop.dptk.many.clr .L1 ;; } + { .bbb; (p2) br.wtop.dpnt .L1 ;; } + { .bbb; br.wtop.dpnt .L1 ;; } + { .bbb; (p2) br.wtop.dpnt.clr .L1 ;; } + { .bbb; br.wtop.dpnt.clr .L1 ;; } + { .bbb; (p2) br.wtop.dpnt.few .L1 ;; } + { .bbb; br.wtop.dpnt.few .L1 ;; } + { .bbb; (p2) br.wtop.dpnt.few.clr .L1 ;; } + { .bbb; br.wtop.dpnt.few.clr .L1 ;; } + { .bbb; (p2) br.wtop.dpnt.many .L1 ;; } + { .bbb; br.wtop.dpnt.many .L1 ;; } + { .bbb; (p2) br.wtop.dpnt.many.clr .L1 ;; } + { .bbb; br.wtop.dpnt.many.clr .L1 ;; } + + { .bbb; br.cloop.sptk .L1 ;; } + { .bbb; br.cloop.sptk.clr .L1 ;; } + { .bbb; br.cloop.sptk.few .L1 ;; } + { .bbb; br.cloop.sptk.few.clr .L1 ;; } + { .bbb; br.cloop.sptk.many .L1 ;; } + { .bbb; br.cloop.sptk.many.clr .L1 ;; } + { .bbb; br.cloop.spnt .L1 ;; } + { .bbb; br.cloop.spnt.clr .L1 ;; } + { .bbb; br.cloop.spnt.few .L1 ;; } + { .bbb; br.cloop.spnt.few.clr .L1 ;; } + { .bbb; br.cloop.spnt.many .L1 ;; } + { .bbb; br.cloop.spnt.many.clr .L1 ;; } + { .bbb; br.cloop.dptk .L1 ;; } + { .bbb; br.cloop.dptk.clr .L1 ;; } + { .bbb; br.cloop.dptk.few .L1 ;; } + { .bbb; br.cloop.dptk.few.clr .L1 ;; } + { .bbb; br.cloop.dptk.many .L1 ;; } + { .bbb; br.cloop.dptk.many.clr .L1 ;; } + { .bbb; br.cloop.dpnt .L1 ;; } + { .bbb; br.cloop.dpnt.clr .L1 ;; } + { .bbb; br.cloop.dpnt.few .L1 ;; } + { .bbb; br.cloop.dpnt.few.clr .L1 ;; } + { .bbb; br.cloop.dpnt.many .L1 ;; } + { .bbb; br.cloop.dpnt.many.clr .L1 ;; } + + { .bbb; br.cexit.sptk .L1 ;; } + { .bbb; br.cexit.sptk.clr .L1 ;; } + { .bbb; br.cexit.sptk.few .L1 ;; } + { .bbb; br.cexit.sptk.few.clr .L1 ;; } + { .bbb; br.cexit.sptk.many .L1 ;; } + { .bbb; br.cexit.sptk.many.clr .L1 ;; } + { .bbb; br.cexit.spnt .L1 ;; } + { .bbb; br.cexit.spnt.clr .L1 ;; } + { .bbb; br.cexit.spnt.few .L1 ;; } + { .bbb; br.cexit.spnt.few.clr .L1 ;; } + { .bbb; br.cexit.spnt.many .L1 ;; } + { .bbb; br.cexit.spnt.many.clr .L1 ;; } + { .bbb; br.cexit.dptk .L1 ;; } + { .bbb; br.cexit.dptk.clr .L1 ;; } + { .bbb; br.cexit.dptk.few .L1 ;; } + { .bbb; br.cexit.dptk.few.clr .L1 ;; } + { .bbb; br.cexit.dptk.many .L1 ;; } + { .bbb; br.cexit.dptk.many.clr .L1 ;; } + { .bbb; br.cexit.dpnt .L1 ;; } + { .bbb; br.cexit.dpnt.clr .L1 ;; } + { .bbb; br.cexit.dpnt.few .L1 ;; } + { .bbb; br.cexit.dpnt.few.clr .L1 ;; } + { .bbb; br.cexit.dpnt.many .L1 ;; } + { .bbb; br.cexit.dpnt.many.clr .L1 ;; } + + { .bbb; br.ctop.sptk .L1 ;; } + { .bbb; br.ctop.sptk.clr .L1 ;; } + { .bbb; br.ctop.sptk.few .L1 ;; } + { .bbb; br.ctop.sptk.few.clr .L1 ;; } + { .bbb; br.ctop.sptk.many .L1 ;; } + { .bbb; br.ctop.sptk.many.clr .L1 ;; } + { .bbb; br.ctop.spnt .L1 ;; } + { .bbb; br.ctop.spnt.clr .L1 ;; } + { .bbb; br.ctop.spnt.few .L1 ;; } + { .bbb; br.ctop.spnt.few.clr .L1 ;; } + { .bbb; br.ctop.spnt.many .L1 ;; } + { .bbb; br.ctop.spnt.many.clr .L1 ;; } + { .bbb; br.ctop.dptk .L1 ;; } + { .bbb; br.ctop.dptk.clr .L1 ;; } + { .bbb; br.ctop.dptk.few .L1 ;; } + { .bbb; br.ctop.dptk.few.clr .L1 ;; } + { .bbb; br.ctop.dptk.many .L1 ;; } + { .bbb; br.ctop.dptk.many.clr .L1 ;; } + { .bbb; br.ctop.dpnt .L1 ;; } + { .bbb; br.ctop.dpnt.clr .L1 ;; } + { .bbb; br.ctop.dpnt.few .L1 ;; } + { .bbb; br.ctop.dpnt.few.clr .L1 ;; } + { .bbb; br.ctop.dpnt.many .L1 ;; } + { .bbb; br.ctop.dpnt.many.clr .L1 ;; } + + { .bbb; nop.b 0 +(p2) br.call.sptk b0 = .L1 + br.call.sptk b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.sptk.clr b0 = .L1 + br.call.sptk.clr b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.sptk.few b0 = .L1 + br.call.sptk.few b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.sptk.few.clr b0 = .L1 + br.call.sptk.few.clr b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.sptk.many b0 = .L1 + br.call.sptk.many b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.sptk.many.clr b0 = .L1 + br.call.sptk.many.clr b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.spnt b0 = .L1 + br.call.spnt b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.spnt.clr b0 = .L1 + br.call.spnt.clr b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.spnt.few b0 = .L1 + br.call.spnt.few b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.spnt.few.clr b0 = .L1 + br.call.spnt.few.clr b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.spnt.many b0 = .L1 + br.call.spnt.many b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.spnt.many.clr b0 = .L1 + br.call.spnt.many.clr b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.dptk b0 = .L1 + br.call.dptk b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.dptk.clr b0 = .L1 + br.call.dptk.clr b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.dptk.few b0 = .L1 + br.call.dptk.few b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.dptk.few.clr b0 = .L1 + br.call.dptk.few.clr b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.dptk.many b0 = .L1 + br.call.dptk.many b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.dptk.many.clr b0 = .L1 + br.call.dptk.many.clr b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.dpnt b0 = .L1 + br.call.dpnt b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.dpnt.clr b0 = .L1 + br.call.dpnt.clr b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.dpnt.few b0 = .L1 + br.call.dpnt.few b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.dpnt.few.clr b0 = .L1 + br.call.dpnt.few.clr b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.dpnt.many b0 = .L1 + br.call.dpnt.many b0 = .L0 + ;; } + { .bbb; nop.b 0 +(p2) br.call.dpnt.many.clr b0 = .L1 + br.call.dpnt.many.clr b0 = .L0 + ;; } + + { .bbb; nop.b 0; +(p2) br.cond.sptk b2 + br.cond.sptk b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.sptk.clr b2 + br.cond.sptk.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.sptk.few b2 + br.cond.sptk.few b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.sptk.few.clr b2 + br.cond.sptk.few.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.sptk.many b2 + br.cond.sptk.many b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.sptk.many.clr b2 + br.cond.sptk.many.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.spnt b2 + br.cond.spnt b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.spnt.clr b2 + br.cond.spnt.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.spnt.few b2 + br.cond.spnt.few b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.spnt.few.clr b2 + br.cond.spnt.few.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.spnt.many b2 + br.cond.spnt.many b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.spnt.many.clr b2 + br.cond.spnt.many.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.dptk b2 + br.cond.dptk b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.dptk.clr b2 + br.cond.dptk.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.dptk.few b2 + br.cond.dptk.few b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.dptk.few.clr b2 + br.cond.dptk.few.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.dptk.many b2 + br.cond.dptk.many b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.dptk.many.clr b2 + br.cond.dptk.many.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.dpnt b2 + br.cond.dpnt b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.dpnt.clr b2 + br.cond.dpnt.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.dpnt.few b2 + br.cond.dpnt.few b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.dpnt.few.clr b2 + br.cond.dpnt.few.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.dpnt.many b2 + br.cond.dpnt.many b2 + ;; } + { .bbb; nop.b 0; +(p2) br.cond.dpnt.many.clr b2 + br.cond.dpnt.many.clr b2 + ;; } + + { .bbb; nop.b 0; + nop.b 0 + br.ia.sptk b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.sptk.clr b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.sptk.few b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.sptk.few.clr b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.sptk.many b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.sptk.many.clr b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.spnt b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.spnt.clr b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.spnt.few b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.spnt.few.clr b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.spnt.many b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.spnt.many.clr b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.dptk b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.dptk.clr b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.dptk.few b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.dptk.few.clr b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.dptk.many b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.dptk.many.clr b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.dpnt b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.dpnt.clr b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.dpnt.few b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.dpnt.few.clr b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.dpnt.many b2 + ;; } + { .bbb; nop.b 0; + nop.b 0 + br.ia.dpnt.many.clr b2 + ;; } + + { .bbb; nop.b 0; +(p2) br.ret.sptk b2 + br.ret.sptk b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.sptk.clr b2 + br.ret.sptk.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.sptk.few b2 + br.ret.sptk.few b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.sptk.few.clr b2 + br.ret.sptk.few.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.sptk.many b2 + br.ret.sptk.many b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.sptk.many.clr b2 + br.ret.sptk.many.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.spnt b2 + br.ret.spnt b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.spnt.clr b2 + br.ret.spnt.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.spnt.few b2 + br.ret.spnt.few b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.spnt.few.clr b2 + br.ret.spnt.few.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.spnt.many b2 + br.ret.spnt.many b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.spnt.many.clr b2 + br.ret.spnt.many.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.dptk b2 + br.ret.dptk b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.dptk.clr b2 + br.ret.dptk.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.dptk.few b2 + br.ret.dptk.few b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.dptk.few.clr b2 + br.ret.dptk.few.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.dptk.many b2 + br.ret.dptk.many b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.dptk.many.clr b2 + br.ret.dptk.many.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.dpnt b2 + br.ret.dpnt b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.dpnt.clr b2 + br.ret.dpnt.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.dpnt.few b2 + br.ret.dpnt.few b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.dpnt.few.clr b2 + br.ret.dpnt.few.clr b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.dpnt.many b2 + br.ret.dpnt.many b2 + ;; } + { .bbb; nop.b 0; +(p2) br.ret.dpnt.many.clr b2 + br.ret.dpnt.many.clr b2 + ;; } + + { .bbb; nop.b 0; +(p2) br.call.sptk b0 = b2 + br.call.sptk b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.sptk.clr b0 = b2 + br.call.sptk.clr b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.sptk.few b0 = b2 + br.call.sptk.few b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.sptk.few.clr b0 = b2 + br.call.sptk.few.clr b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.sptk.many b0 = b2 + br.call.sptk.many b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.sptk.many.clr b0 = b2 + br.call.sptk.many.clr b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.spnt b0 = b2 + br.call.spnt b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.spnt.clr b0 = b2 + br.call.spnt.clr b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.spnt.few b0 = b2 + br.call.spnt.few b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.spnt.few.clr b0 = b2 + br.call.spnt.few.clr b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.spnt.many b0 = b2 + br.call.spnt.many b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.spnt.many.clr b0 = b2 + br.call.spnt.many.clr b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.dptk b0 = b2 + br.call.dptk b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.dptk.clr b0 = b2 + br.call.dptk.clr b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.dptk.few b0 = b2 + br.call.dptk.few b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.dptk.few.clr b0 = b2 + br.call.dptk.few.clr b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.dptk.many b0 = b2 + br.call.dptk.many b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.dptk.many.clr b0 = b2 + br.call.dptk.many.clr b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.dpnt b0 = b2 + br.call.dpnt b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.dpnt.clr b0 = b2 + br.call.dpnt.clr b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.dpnt.few b0 = b2 + br.call.dpnt.few b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.dpnt.few.clr b0 = b2 + br.call.dpnt.few.clr b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.dpnt.many b0 = b2 + br.call.dpnt.many b0 = b2 + ;; } + { .bbb; nop.b 0; +(p2) br.call.dpnt.many.clr b0 = b2 + br.call.dpnt.many.clr b0 = b2 + ;; } + + { .bbb; break.b 0; nop.b 0 + brp.sptk .L0, .L2 + ;; } + { .bbb; break.b 0; nop.b 0 + brp.sptk.imp .L0, .L2 + ;; } +.L2: + { .bbb; break.b 0; nop.b 0 + brp.loop .L0, .L3 + ;; } + { .bbb; break.b 0; nop.b 0 + brp.loop.imp .L0, .L3 + ;; } +.L3: + { .bbb; break.b 0; nop.b 0 + brp.dptk .L0, .L4 + ;; } + { .bbb; break.b 0; nop.b 0 + brp.dptk.imp .L0, .L4 + ;; } +.L4: + { .bbb; break.b 0; nop.b 0 + brp.exit .L0, .L5 + ;; } + { .bbb; break.b 0; nop.b 0 + brp.exit.imp .L0, .L5 + ;; } +.L5: + + { .bbb; break.b 0; nop.b 0 + brp.sptk b3, .L6 + ;; } + { .bbb; break.b 0; nop.b 0 + brp.sptk.imp b3, .L6 + ;; } +.L6: + { .bbb; break.b 0; nop.b 0 + brp.dptk b3, .L7 + ;; } + { .bbb; break.b 0; nop.b 0 + brp.dptk.imp b3, .L7 + ;; } +.L7: + + { .bbb; break.b 0; nop.b 0 + brp.ret.sptk b3, .L8 + ;; } + { .bbb; break.b 0; nop.b 0 + brp.ret.sptk.imp b3, .L8 + ;; } +.L8: + { .bbb; break.b 0; nop.b 0 + brp.ret.dptk b3, .L9 + ;; } + { .bbb; break.b 0; nop.b 0 + brp.ret.dptk.imp b3, .L9 + ;; } +.L9: + +.space 5888 + { .bbb; nop.b 0; nop.b 0; cover ;; } + { .bbb; nop.b 0; nop.b 0; clrrrb ;; } + { .bbb; nop.b 0; nop.b 0; clrrrb.pr ;; } + { .bbb; nop.b 0; nop.b 0; rfi ;; } + { .bbb; nop.b 0; nop.b 0; bsw.0 ;; } + { .bbb; nop.b 0; nop.b 0; bsw.1 ;; } + { .bbb; nop.b 0; nop.b 0; epc ;; } + +.L1: diff --git a/gas/testsuite/gas/ia64/opc-f.d b/gas/testsuite/gas/ia64/opc-f.d new file mode 100644 index 0000000..0e69d3f --- /dev/null +++ b/gas/testsuite/gas/ia64/opc-f.d @@ -0,0 +1,1217 @@ +# objdump: -d +# name: ia64 opc-f + +.*: +file format .* + +Disassembly of section \.text: + +0000000000000000 <_start>: + 0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 6: 40 38 14 0c 40 00 fma\.s0 f4=f5,f6,f7 + c: 00 00 04 00 nop\.i 0x0 + 10: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 16: 40 38 14 0c 40 00 fma\.s0 f4=f5,f6,f7 + 1c: 00 00 04 00 nop\.i 0x0 + 20: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 26: 40 38 14 0c 41 00 fma\.s1 f4=f5,f6,f7 + 2c: 00 00 04 00 nop\.i 0x0 + 30: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 36: 40 38 14 0c 42 00 fma\.s2 f4=f5,f6,f7 + 3c: 00 00 04 00 nop\.i 0x0 + 40: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 46: 40 38 14 0c 43 00 fma\.s3 f4=f5,f6,f7 + 4c: 00 00 04 00 nop\.i 0x0 + 50: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 56: 40 38 14 0c 44 00 fma\.s\.s0 f4=f5,f6,f7 + 5c: 00 00 04 00 nop\.i 0x0 + 60: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 66: 40 38 14 0c 44 00 fma\.s\.s0 f4=f5,f6,f7 + 6c: 00 00 04 00 nop\.i 0x0 + 70: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 76: 40 38 14 0c 45 00 fma\.s\.s1 f4=f5,f6,f7 + 7c: 00 00 04 00 nop\.i 0x0 + 80: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 86: 40 38 14 0c 46 00 fma\.s\.s2 f4=f5,f6,f7 + 8c: 00 00 04 00 nop\.i 0x0 + 90: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 96: 40 38 14 0c 47 00 fma\.s\.s3 f4=f5,f6,f7 + 9c: 00 00 04 00 nop\.i 0x0 + a0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + a6: 40 38 14 0c 48 00 fma\.d\.s0 f4=f5,f6,f7 + ac: 00 00 04 00 nop\.i 0x0 + b0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + b6: 40 38 14 0c 48 00 fma\.d\.s0 f4=f5,f6,f7 + bc: 00 00 04 00 nop\.i 0x0 + c0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + c6: 40 38 14 0c 49 00 fma\.d\.s1 f4=f5,f6,f7 + cc: 00 00 04 00 nop\.i 0x0 + d0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + d6: 40 38 14 0c 4a 00 fma\.d\.s2 f4=f5,f6,f7 + dc: 00 00 04 00 nop\.i 0x0 + e0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + e6: 40 38 14 0c 4b 00 fma\.d\.s3 f4=f5,f6,f7 + ec: 00 00 04 00 nop\.i 0x0 + f0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + f6: 40 38 14 0c 4c 00 fpma\.s0 f4=f5,f6,f7 + fc: 00 00 04 00 nop\.i 0x0 + 100: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 106: 40 38 14 0c 4c 00 fpma\.s0 f4=f5,f6,f7 + 10c: 00 00 04 00 nop\.i 0x0 + 110: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 116: 40 38 14 0c 4d 00 fpma\.s1 f4=f5,f6,f7 + 11c: 00 00 04 00 nop\.i 0x0 + 120: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 126: 40 38 14 0c 4e 00 fpma\.s2 f4=f5,f6,f7 + 12c: 00 00 04 00 nop\.i 0x0 + 130: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 136: 40 38 14 0c 4f 00 fpma\.s3 f4=f5,f6,f7 + 13c: 00 00 04 00 nop\.i 0x0 + 140: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 146: 40 38 14 0c 50 00 fms\.s0 f4=f5,f6,f7 + 14c: 00 00 04 00 nop\.i 0x0 + 150: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 156: 40 38 14 0c 50 00 fms\.s0 f4=f5,f6,f7 + 15c: 00 00 04 00 nop\.i 0x0 + 160: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 166: 40 38 14 0c 51 00 fms\.s1 f4=f5,f6,f7 + 16c: 00 00 04 00 nop\.i 0x0 + 170: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 176: 40 38 14 0c 52 00 fms\.s2 f4=f5,f6,f7 + 17c: 00 00 04 00 nop\.i 0x0 + 180: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 186: 40 38 14 0c 53 00 fms\.s3 f4=f5,f6,f7 + 18c: 00 00 04 00 nop\.i 0x0 + 190: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 196: 40 38 14 0c 54 00 fms\.s\.s0 f4=f5,f6,f7 + 19c: 00 00 04 00 nop\.i 0x0 + 1a0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1a6: 40 38 14 0c 54 00 fms\.s\.s0 f4=f5,f6,f7 + 1ac: 00 00 04 00 nop\.i 0x0 + 1b0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1b6: 40 38 14 0c 55 00 fms\.s\.s1 f4=f5,f6,f7 + 1bc: 00 00 04 00 nop\.i 0x0 + 1c0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1c6: 40 38 14 0c 56 00 fms\.s\.s2 f4=f5,f6,f7 + 1cc: 00 00 04 00 nop\.i 0x0 + 1d0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1d6: 40 38 14 0c 57 00 fms\.s\.s3 f4=f5,f6,f7 + 1dc: 00 00 04 00 nop\.i 0x0 + 1e0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1e6: 40 38 14 0c 58 00 fms\.d\.s0 f4=f5,f6,f7 + 1ec: 00 00 04 00 nop\.i 0x0 + 1f0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1f6: 40 38 14 0c 58 00 fms\.d\.s0 f4=f5,f6,f7 + 1fc: 00 00 04 00 nop\.i 0x0 + 200: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 206: 40 38 14 0c 59 00 fms\.d\.s1 f4=f5,f6,f7 + 20c: 00 00 04 00 nop\.i 0x0 + 210: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 216: 40 38 14 0c 5a 00 fms\.d\.s2 f4=f5,f6,f7 + 21c: 00 00 04 00 nop\.i 0x0 + 220: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 226: 40 38 14 0c 5b 00 fms\.d\.s3 f4=f5,f6,f7 + 22c: 00 00 04 00 nop\.i 0x0 + 230: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 236: 40 38 14 0c 5c 00 fpms\.s0 f4=f5,f6,f7 + 23c: 00 00 04 00 nop\.i 0x0 + 240: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 246: 40 38 14 0c 5c 00 fpms\.s0 f4=f5,f6,f7 + 24c: 00 00 04 00 nop\.i 0x0 + 250: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 256: 40 38 14 0c 5d 00 fpms\.s1 f4=f5,f6,f7 + 25c: 00 00 04 00 nop\.i 0x0 + 260: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 266: 40 38 14 0c 5e 00 fpms\.s2 f4=f5,f6,f7 + 26c: 00 00 04 00 nop\.i 0x0 + 270: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 276: 40 38 14 0c 5f 00 fpms\.s3 f4=f5,f6,f7 + 27c: 00 00 04 00 nop\.i 0x0 + 280: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 286: 40 38 14 0c 60 00 fnma\.s0 f4=f5,f6,f7 + 28c: 00 00 04 00 nop\.i 0x0 + 290: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 296: 40 38 14 0c 60 00 fnma\.s0 f4=f5,f6,f7 + 29c: 00 00 04 00 nop\.i 0x0 + 2a0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2a6: 40 38 14 0c 61 00 fnma\.s1 f4=f5,f6,f7 + 2ac: 00 00 04 00 nop\.i 0x0 + 2b0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2b6: 40 38 14 0c 62 00 fnma\.s2 f4=f5,f6,f7 + 2bc: 00 00 04 00 nop\.i 0x0 + 2c0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2c6: 40 38 14 0c 63 00 fnma\.s3 f4=f5,f6,f7 + 2cc: 00 00 04 00 nop\.i 0x0 + 2d0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2d6: 40 38 14 0c 64 00 fnma\.s\.s0 f4=f5,f6,f7 + 2dc: 00 00 04 00 nop\.i 0x0 + 2e0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2e6: 40 38 14 0c 64 00 fnma\.s\.s0 f4=f5,f6,f7 + 2ec: 00 00 04 00 nop\.i 0x0 + 2f0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2f6: 40 38 14 0c 65 00 fnma\.s\.s1 f4=f5,f6,f7 + 2fc: 00 00 04 00 nop\.i 0x0 + 300: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 306: 40 38 14 0c 66 00 fnma\.s\.s2 f4=f5,f6,f7 + 30c: 00 00 04 00 nop\.i 0x0 + 310: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 316: 40 38 14 0c 67 00 fnma\.s\.s3 f4=f5,f6,f7 + 31c: 00 00 04 00 nop\.i 0x0 + 320: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 326: 40 38 14 0c 68 00 fnma\.d\.s0 f4=f5,f6,f7 + 32c: 00 00 04 00 nop\.i 0x0 + 330: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 336: 40 38 14 0c 68 00 fnma\.d\.s0 f4=f5,f6,f7 + 33c: 00 00 04 00 nop\.i 0x0 + 340: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 346: 40 38 14 0c 69 00 fnma\.d\.s1 f4=f5,f6,f7 + 34c: 00 00 04 00 nop\.i 0x0 + 350: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 356: 40 38 14 0c 6a 00 fnma\.d\.s2 f4=f5,f6,f7 + 35c: 00 00 04 00 nop\.i 0x0 + 360: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 366: 40 38 14 0c 6b 00 fnma\.d\.s3 f4=f5,f6,f7 + 36c: 00 00 04 00 nop\.i 0x0 + 370: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 376: 40 38 14 0c 6c 00 fpnma\.s0 f4=f5,f6,f7 + 37c: 00 00 04 00 nop\.i 0x0 + 380: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 386: 40 38 14 0c 6c 00 fpnma\.s0 f4=f5,f6,f7 + 38c: 00 00 04 00 nop\.i 0x0 + 390: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 396: 40 38 14 0c 6d 00 fpnma\.s1 f4=f5,f6,f7 + 39c: 00 00 04 00 nop\.i 0x0 + 3a0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 3a6: 40 38 14 0c 6e 00 fpnma\.s2 f4=f5,f6,f7 + 3ac: 00 00 04 00 nop\.i 0x0 + 3b0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 3b6: 40 38 14 0c 6f 00 fpnma\.s3 f4=f5,f6,f7 + 3bc: 00 00 04 00 nop\.i 0x0 + 3c0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 3c6: 40 00 14 0c 40 00 fmpy\.s0 f4=f5,f6 + 3cc: 00 00 04 00 nop\.i 0x0 + 3d0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 3d6: 40 00 14 0c 40 00 fmpy\.s0 f4=f5,f6 + 3dc: 00 00 04 00 nop\.i 0x0 + 3e0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 3e6: 40 00 14 0c 41 00 fmpy\.s1 f4=f5,f6 + 3ec: 00 00 04 00 nop\.i 0x0 + 3f0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 3f6: 40 00 14 0c 42 00 fmpy\.s2 f4=f5,f6 + 3fc: 00 00 04 00 nop\.i 0x0 + 400: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 406: 40 00 14 0c 43 00 fmpy\.s3 f4=f5,f6 + 40c: 00 00 04 00 nop\.i 0x0 + 410: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 416: 40 00 14 0c 44 00 fmpy\.s\.s0 f4=f5,f6 + 41c: 00 00 04 00 nop\.i 0x0 + 420: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 426: 40 00 14 0c 44 00 fmpy\.s\.s0 f4=f5,f6 + 42c: 00 00 04 00 nop\.i 0x0 + 430: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 436: 40 00 14 0c 45 00 fmpy\.s\.s1 f4=f5,f6 + 43c: 00 00 04 00 nop\.i 0x0 + 440: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 446: 40 00 14 0c 46 00 fmpy\.s\.s2 f4=f5,f6 + 44c: 00 00 04 00 nop\.i 0x0 + 450: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 456: 40 00 14 0c 47 00 fmpy\.s\.s3 f4=f5,f6 + 45c: 00 00 04 00 nop\.i 0x0 + 460: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 466: 40 00 14 0c 48 00 fmpy\.d\.s0 f4=f5,f6 + 46c: 00 00 04 00 nop\.i 0x0 + 470: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 476: 40 00 14 0c 48 00 fmpy\.d\.s0 f4=f5,f6 + 47c: 00 00 04 00 nop\.i 0x0 + 480: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 486: 40 00 14 0c 49 00 fmpy\.d\.s1 f4=f5,f6 + 48c: 00 00 04 00 nop\.i 0x0 + 490: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 496: 40 00 14 0c 4a 00 fmpy\.d\.s2 f4=f5,f6 + 49c: 00 00 04 00 nop\.i 0x0 + 4a0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 4a6: 40 00 14 0c 4b 00 fmpy\.d\.s3 f4=f5,f6 + 4ac: 00 00 04 00 nop\.i 0x0 + 4b0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 4b6: 40 00 14 0c 4c 00 fpmpy\.s0 f4=f5,f6 + 4bc: 00 00 04 00 nop\.i 0x0 + 4c0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 4c6: 40 00 14 0c 4c 00 fpmpy\.s0 f4=f5,f6 + 4cc: 00 00 04 00 nop\.i 0x0 + 4d0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 4d6: 40 00 14 0c 4d 00 fpmpy\.s1 f4=f5,f6 + 4dc: 00 00 04 00 nop\.i 0x0 + 4e0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 4e6: 40 00 14 0c 4e 00 fpmpy\.s2 f4=f5,f6 + 4ec: 00 00 04 00 nop\.i 0x0 + 4f0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 4f6: 40 00 14 0c 4f 00 fpmpy\.s3 f4=f5,f6 + 4fc: 00 00 04 00 nop\.i 0x0 + 500: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 506: 40 30 14 02 40 00 fadd\.s0 f4=f5,f6 + 50c: 00 00 04 00 nop\.i 0x0 + 510: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 516: 40 30 14 02 40 00 fadd\.s0 f4=f5,f6 + 51c: 00 00 04 00 nop\.i 0x0 + 520: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 526: 40 30 14 02 41 00 fadd\.s1 f4=f5,f6 + 52c: 00 00 04 00 nop\.i 0x0 + 530: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 536: 40 30 14 02 42 00 fadd\.s2 f4=f5,f6 + 53c: 00 00 04 00 nop\.i 0x0 + 540: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 546: 40 30 14 02 43 00 fadd\.s3 f4=f5,f6 + 54c: 00 00 04 00 nop\.i 0x0 + 550: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 556: 40 30 14 02 44 00 fadd\.s\.s0 f4=f5,f6 + 55c: 00 00 04 00 nop\.i 0x0 + 560: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 566: 40 30 14 02 44 00 fadd\.s\.s0 f4=f5,f6 + 56c: 00 00 04 00 nop\.i 0x0 + 570: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 576: 40 30 14 02 45 00 fadd\.s\.s1 f4=f5,f6 + 57c: 00 00 04 00 nop\.i 0x0 + 580: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 586: 40 30 14 02 46 00 fadd\.s\.s2 f4=f5,f6 + 58c: 00 00 04 00 nop\.i 0x0 + 590: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 596: 40 30 14 02 47 00 fadd\.s\.s3 f4=f5,f6 + 59c: 00 00 04 00 nop\.i 0x0 + 5a0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 5a6: 40 30 14 02 48 00 fadd\.d\.s0 f4=f5,f6 + 5ac: 00 00 04 00 nop\.i 0x0 + 5b0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 5b6: 40 30 14 02 48 00 fadd\.d\.s0 f4=f5,f6 + 5bc: 00 00 04 00 nop\.i 0x0 + 5c0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 5c6: 40 30 14 02 49 00 fadd\.d\.s1 f4=f5,f6 + 5cc: 00 00 04 00 nop\.i 0x0 + 5d0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 5d6: 40 30 14 02 4a 00 fadd\.d\.s2 f4=f5,f6 + 5dc: 00 00 04 00 nop\.i 0x0 + 5e0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 5e6: 40 30 14 02 4b 00 fadd\.d\.s3 f4=f5,f6 + 5ec: 00 00 04 00 nop\.i 0x0 + 5f0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 5f6: 40 30 14 02 50 00 fsub\.s0 f4=f5,f6 + 5fc: 00 00 04 00 nop\.i 0x0 + 600: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 606: 40 30 14 02 50 00 fsub\.s0 f4=f5,f6 + 60c: 00 00 04 00 nop\.i 0x0 + 610: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 616: 40 30 14 02 51 00 fsub\.s1 f4=f5,f6 + 61c: 00 00 04 00 nop\.i 0x0 + 620: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 626: 40 30 14 02 52 00 fsub\.s2 f4=f5,f6 + 62c: 00 00 04 00 nop\.i 0x0 + 630: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 636: 40 30 14 02 53 00 fsub\.s3 f4=f5,f6 + 63c: 00 00 04 00 nop\.i 0x0 + 640: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 646: 40 30 14 02 54 00 fsub\.s\.s0 f4=f5,f6 + 64c: 00 00 04 00 nop\.i 0x0 + 650: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 656: 40 30 14 02 54 00 fsub\.s\.s0 f4=f5,f6 + 65c: 00 00 04 00 nop\.i 0x0 + 660: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 666: 40 30 14 02 55 00 fsub\.s\.s1 f4=f5,f6 + 66c: 00 00 04 00 nop\.i 0x0 + 670: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 676: 40 30 14 02 56 00 fsub\.s\.s2 f4=f5,f6 + 67c: 00 00 04 00 nop\.i 0x0 + 680: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 686: 40 30 14 02 57 00 fsub\.s\.s3 f4=f5,f6 + 68c: 00 00 04 00 nop\.i 0x0 + 690: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 696: 40 30 14 02 58 00 fsub\.d\.s0 f4=f5,f6 + 69c: 00 00 04 00 nop\.i 0x0 + 6a0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 6a6: 40 30 14 02 58 00 fsub\.d\.s0 f4=f5,f6 + 6ac: 00 00 04 00 nop\.i 0x0 + 6b0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 6b6: 40 30 14 02 59 00 fsub\.d\.s1 f4=f5,f6 + 6bc: 00 00 04 00 nop\.i 0x0 + 6c0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 6c6: 40 30 14 02 5a 00 fsub\.d\.s2 f4=f5,f6 + 6cc: 00 00 04 00 nop\.i 0x0 + 6d0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 6d6: 40 30 14 02 5b 00 fsub\.d\.s3 f4=f5,f6 + 6dc: 00 00 04 00 nop\.i 0x0 + 6e0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 6e6: 40 30 14 02 5c 00 fpms\.s0 f4=f5,f1,f6 + 6ec: 00 00 04 00 nop\.i 0x0 + 6f0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 6f6: 40 30 14 02 5c 00 fpms\.s0 f4=f5,f1,f6 + 6fc: 00 00 04 00 nop\.i 0x0 + 700: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 706: 40 30 14 02 5d 00 fpms\.s1 f4=f5,f1,f6 + 70c: 00 00 04 00 nop\.i 0x0 + 710: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 716: 40 30 14 02 5e 00 fpms\.s2 f4=f5,f1,f6 + 71c: 00 00 04 00 nop\.i 0x0 + 720: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 726: 40 30 14 02 5f 00 fpms\.s3 f4=f5,f1,f6 + 72c: 00 00 04 00 nop\.i 0x0 + 730: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 736: 40 00 14 0c 60 00 fnmpy\.s0 f4=f5,f6 + 73c: 00 00 04 00 nop\.i 0x0 + 740: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 746: 40 00 14 0c 60 00 fnmpy\.s0 f4=f5,f6 + 74c: 00 00 04 00 nop\.i 0x0 + 750: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 756: 40 00 14 0c 61 00 fnmpy\.s1 f4=f5,f6 + 75c: 00 00 04 00 nop\.i 0x0 + 760: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 766: 40 00 14 0c 62 00 fnmpy\.s2 f4=f5,f6 + 76c: 00 00 04 00 nop\.i 0x0 + 770: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 776: 40 00 14 0c 63 00 fnmpy\.s3 f4=f5,f6 + 77c: 00 00 04 00 nop\.i 0x0 + 780: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 786: 40 00 14 0c 64 00 fnmpy\.s\.s0 f4=f5,f6 + 78c: 00 00 04 00 nop\.i 0x0 + 790: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 796: 40 00 14 0c 64 00 fnmpy\.s\.s0 f4=f5,f6 + 79c: 00 00 04 00 nop\.i 0x0 + 7a0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 7a6: 40 00 14 0c 65 00 fnmpy\.s\.s1 f4=f5,f6 + 7ac: 00 00 04 00 nop\.i 0x0 + 7b0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 7b6: 40 00 14 0c 66 00 fnmpy\.s\.s2 f4=f5,f6 + 7bc: 00 00 04 00 nop\.i 0x0 + 7c0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 7c6: 40 00 14 0c 67 00 fnmpy\.s\.s3 f4=f5,f6 + 7cc: 00 00 04 00 nop\.i 0x0 + 7d0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 7d6: 40 00 14 0c 68 00 fnmpy\.d\.s0 f4=f5,f6 + 7dc: 00 00 04 00 nop\.i 0x0 + 7e0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 7e6: 40 00 14 0c 68 00 fnmpy\.d\.s0 f4=f5,f6 + 7ec: 00 00 04 00 nop\.i 0x0 + 7f0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 7f6: 40 00 14 0c 69 00 fnmpy\.d\.s1 f4=f5,f6 + 7fc: 00 00 04 00 nop\.i 0x0 + 800: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 806: 40 00 14 0c 6a 00 fnmpy\.d\.s2 f4=f5,f6 + 80c: 00 00 04 00 nop\.i 0x0 + 810: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 816: 40 00 14 0c 6b 00 fnmpy\.d\.s3 f4=f5,f6 + 81c: 00 00 04 00 nop\.i 0x0 + 820: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 826: 40 00 14 0c 6c 00 fpnmpy\.s0 f4=f5,f6 + 82c: 00 00 04 00 nop\.i 0x0 + 830: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 836: 40 00 14 0c 6c 00 fpnmpy\.s0 f4=f5,f6 + 83c: 00 00 04 00 nop\.i 0x0 + 840: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 846: 40 00 14 0c 6d 00 fpnmpy\.s1 f4=f5,f6 + 84c: 00 00 04 00 nop\.i 0x0 + 850: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 856: 40 00 14 0c 6e 00 fpnmpy\.s2 f4=f5,f6 + 85c: 00 00 04 00 nop\.i 0x0 + 860: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 866: 40 00 14 0c 6f 00 fpnmpy\.s3 f4=f5,f6 + 86c: 00 00 04 00 nop\.i 0x0 + 870: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 876: 40 00 14 02 40 00 fnorm\.s0 f4=f5 + 87c: 00 00 04 00 nop\.i 0x0 + 880: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 886: 40 00 14 02 40 00 fnorm\.s0 f4=f5 + 88c: 00 00 04 00 nop\.i 0x0 + 890: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 896: 40 00 14 02 41 00 fnorm\.s1 f4=f5 + 89c: 00 00 04 00 nop\.i 0x0 + 8a0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 8a6: 40 00 14 02 42 00 fnorm\.s2 f4=f5 + 8ac: 00 00 04 00 nop\.i 0x0 + 8b0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 8b6: 40 00 14 02 43 00 fnorm\.s3 f4=f5 + 8bc: 00 00 04 00 nop\.i 0x0 + 8c0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 8c6: 40 00 14 02 44 00 fnorm\.s\.s0 f4=f5 + 8cc: 00 00 04 00 nop\.i 0x0 + 8d0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 8d6: 40 00 14 02 44 00 fnorm\.s\.s0 f4=f5 + 8dc: 00 00 04 00 nop\.i 0x0 + 8e0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 8e6: 40 00 14 02 45 00 fnorm\.s\.s1 f4=f5 + 8ec: 00 00 04 00 nop\.i 0x0 + 8f0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 8f6: 40 00 14 02 46 00 fnorm\.s\.s2 f4=f5 + 8fc: 00 00 04 00 nop\.i 0x0 + 900: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 906: 40 00 14 02 47 00 fnorm\.s\.s3 f4=f5 + 90c: 00 00 04 00 nop\.i 0x0 + 910: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 916: 40 00 14 02 48 00 fnorm\.d\.s0 f4=f5 + 91c: 00 00 04 00 nop\.i 0x0 + 920: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 926: 40 00 14 02 48 00 fnorm\.d\.s0 f4=f5 + 92c: 00 00 04 00 nop\.i 0x0 + 930: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 936: 40 00 14 02 49 00 fnorm\.d\.s1 f4=f5 + 93c: 00 00 04 00 nop\.i 0x0 + 940: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 946: 40 00 14 02 4a 00 fnorm\.d\.s2 f4=f5 + 94c: 00 00 04 00 nop\.i 0x0 + 950: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 956: 40 00 14 02 4b 00 fnorm\.d\.s3 f4=f5 + 95c: 00 00 04 00 nop\.i 0x0 + 960: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 966: 40 38 14 0c 74 00 xma\.l f4=f5,f6,f7 + 96c: 00 00 04 00 nop\.i 0x0 + 970: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 976: 40 38 14 0c 74 00 xma\.l f4=f5,f6,f7 + 97c: 00 00 04 00 nop\.i 0x0 + 980: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 986: 40 38 14 0c 77 00 xma\.h f4=f5,f6,f7 + 98c: 00 00 04 00 nop\.i 0x0 + 990: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 996: 40 38 14 0c 76 00 xma\.hu f4=f5,f6,f7 + 99c: 00 00 04 00 nop\.i 0x0 + 9a0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 9a6: 40 00 14 0c 74 00 xma\.l f4=f5,f6,f0 + 9ac: 00 00 04 00 nop\.i 0x0 + 9b0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 9b6: 40 00 14 0c 74 00 xma\.l f4=f5,f6,f0 + 9bc: 00 00 04 00 nop\.i 0x0 + 9c0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 9c6: 40 00 14 0c 77 00 xma\.h f4=f5,f6,f0 + 9cc: 00 00 04 00 nop\.i 0x0 + 9d0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 9d6: 40 00 14 0c 76 00 xma\.hu f4=f5,f6,f0 + 9dc: 00 00 04 00 nop\.i 0x0 + 9e0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 9e6: 40 38 14 0c 70 00 fselect f4=f5,f6,f7 + 9ec: 00 00 04 00 nop\.i 0x0 + 9f0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 9f6: 30 20 00 09 28 00 fclass\.m p3,p4=f4,0x100 + 9fc: 00 00 04 00 nop\.i 0x0 + a00: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + a06: 40 20 00 07 28 00 fclass\.m p4,p3=f4,0x100 + a0c: 00 00 04 00 nop\.i 0x0 + a10: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + a16: 30 20 80 08 28 00 fclass\.m p3,p4=f4,0x80 + a1c: 00 00 04 00 nop\.i 0x0 + a20: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + a26: 40 20 80 06 28 00 fclass\.m p4,p3=f4,0x80 + a2c: 00 00 04 00 nop\.i 0x0 + a30: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + a36: 30 20 40 08 28 00 fclass\.m p3,p4=f4,0x40 + a3c: 00 00 04 00 nop\.i 0x0 + a40: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + a46: 40 20 40 06 28 00 fclass\.m p4,p3=f4,0x40 + a4c: 00 00 04 00 nop\.i 0x0 + a50: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + a56: 30 20 00 88 28 00 fclass\.m p3,p4=f4,0x1 + a5c: 00 00 04 00 nop\.i 0x0 + a60: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + a66: 40 20 00 86 28 00 fclass\.m p4,p3=f4,0x1 + a6c: 00 00 04 00 nop\.i 0x0 + a70: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + a76: 30 20 00 08 29 00 fclass\.m p3,p4=f4,0x2 + a7c: 00 00 04 00 nop\.i 0x0 + a80: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + a86: 40 20 00 06 29 00 fclass\.m p4,p3=f4,0x2 + a8c: 00 00 04 00 nop\.i 0x0 + a90: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + a96: 30 20 08 88 29 00 fclass\.m p3,p4=f4,0xb + a9c: 00 00 04 00 nop\.i 0x0 + aa0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + aa6: 40 20 08 86 29 00 fclass\.m p4,p3=f4,0xb + aac: 00 00 04 00 nop\.i 0x0 + ab0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + ab6: 30 20 10 88 29 00 fclass\.m p3,p4=f4,0x13 + abc: 00 00 04 00 nop\.i 0x0 + ac0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + ac6: 40 20 10 86 29 00 fclass\.m p4,p3=f4,0x13 + acc: 00 00 04 00 nop\.i 0x0 + ad0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + ad6: 30 20 20 88 29 00 fclass\.m p3,p4=f4,0x23 + adc: 00 00 04 00 nop\.i 0x0 + ae0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + ae6: 40 20 20 86 29 00 fclass\.m p4,p3=f4,0x23 + aec: 00 00 04 00 nop\.i 0x0 + af0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + af6: 30 20 fc 89 29 00 fclass\.m p3,p4=f4,0x1ff + afc: 00 00 04 00 nop\.i 0x0 + b00: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + b06: 40 20 fc 87 29 00 fclass\.m p4,p3=f4,0x1ff + b0c: 00 00 04 00 nop\.i 0x0 + b10: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + b16: 30 24 00 09 28 00 fclass\.m\.unc p3,p4=f4,0x100 + b1c: 00 00 04 00 nop\.i 0x0 + b20: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + b26: 40 24 00 07 28 00 fclass\.m\.unc p4,p3=f4,0x100 + b2c: 00 00 04 00 nop\.i 0x0 + b30: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + b36: 30 24 80 08 28 00 fclass\.m\.unc p3,p4=f4,0x80 + b3c: 00 00 04 00 nop\.i 0x0 + b40: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + b46: 40 24 80 06 28 00 fclass\.m\.unc p4,p3=f4,0x80 + b4c: 00 00 04 00 nop\.i 0x0 + b50: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + b56: 30 24 40 08 28 00 fclass\.m\.unc p3,p4=f4,0x40 + b5c: 00 00 04 00 nop\.i 0x0 + b60: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + b66: 40 24 40 06 28 00 fclass\.m\.unc p4,p3=f4,0x40 + b6c: 00 00 04 00 nop\.i 0x0 + b70: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + b76: 30 24 00 88 28 00 fclass\.m\.unc p3,p4=f4,0x1 + b7c: 00 00 04 00 nop\.i 0x0 + b80: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + b86: 40 24 00 86 28 00 fclass\.m\.unc p4,p3=f4,0x1 + b8c: 00 00 04 00 nop\.i 0x0 + b90: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + b96: 30 24 00 08 29 00 fclass\.m\.unc p3,p4=f4,0x2 + b9c: 00 00 04 00 nop\.i 0x0 + ba0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + ba6: 40 24 00 06 29 00 fclass\.m\.unc p4,p3=f4,0x2 + bac: 00 00 04 00 nop\.i 0x0 + bb0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + bb6: 30 24 08 88 29 00 fclass\.m\.unc p3,p4=f4,0xb + bbc: 00 00 04 00 nop\.i 0x0 + bc0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + bc6: 40 24 08 86 29 00 fclass\.m\.unc p4,p3=f4,0xb + bcc: 00 00 04 00 nop\.i 0x0 + bd0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + bd6: 30 24 10 88 29 00 fclass\.m\.unc p3,p4=f4,0x13 + bdc: 00 00 04 00 nop\.i 0x0 + be0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + be6: 40 24 10 86 29 00 fclass\.m\.unc p4,p3=f4,0x13 + bec: 00 00 04 00 nop\.i 0x0 + bf0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + bf6: 30 24 20 88 29 00 fclass\.m\.unc p3,p4=f4,0x23 + bfc: 00 00 04 00 nop\.i 0x0 + c00: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + c06: 40 24 20 86 29 00 fclass\.m\.unc p4,p3=f4,0x23 + c0c: 00 00 04 00 nop\.i 0x0 + c10: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + c16: 30 24 fc 89 29 00 fclass\.m\.unc p3,p4=f4,0x1ff + c1c: 00 00 04 00 nop\.i 0x0 + c20: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + c26: 40 24 fc 87 29 00 fclass\.m\.unc p4,p3=f4,0x1ff + c2c: 00 00 04 00 nop\.i 0x0 + c30: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + c36: 40 30 1c 8a 00 00 frcpa\.s0 f4,p5=f6,f7 + c3c: 00 00 04 00 nop\.i 0x0 + c40: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + c46: 40 30 1c 8a 00 00 frcpa\.s0 f4,p5=f6,f7 + c4c: 00 00 04 00 nop\.i 0x0 + c50: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + c56: 40 30 1c 8a 01 00 frcpa\.s1 f4,p5=f6,f7 + c5c: 00 00 04 00 nop\.i 0x0 + c60: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + c66: 40 30 1c 8a 02 00 frcpa\.s2 f4,p5=f6,f7 + c6c: 00 00 04 00 nop\.i 0x0 + c70: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + c76: 40 30 1c 8a 03 00 frcpa\.s3 f4,p5=f6,f7 + c7c: 00 00 04 00 nop\.i 0x0 + c80: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + c86: 40 30 1c 8a 08 00 fprcpa\.s0 f4,p5=f6,f7 + c8c: 00 00 04 00 nop\.i 0x0 + c90: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + c96: 40 30 1c 8a 08 00 fprcpa\.s0 f4,p5=f6,f7 + c9c: 00 00 04 00 nop\.i 0x0 + ca0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + ca6: 40 30 1c 8a 09 00 fprcpa\.s1 f4,p5=f6,f7 + cac: 00 00 04 00 nop\.i 0x0 + cb0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + cb6: 40 30 1c 8a 0a 00 fprcpa\.s2 f4,p5=f6,f7 + cbc: 00 00 04 00 nop\.i 0x0 + cc0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + cc6: 40 30 1c 8a 0b 00 fprcpa\.s3 f4,p5=f6,f7 + ccc: 00 00 04 00 nop\.i 0x0 + cd0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + cd6: 40 00 18 8a 04 00 frsqrta\.s0 f4,p5=f6 + cdc: 00 00 04 00 nop\.i 0x0 + ce0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + ce6: 40 00 18 8a 04 00 frsqrta\.s0 f4,p5=f6 + cec: 00 00 04 00 nop\.i 0x0 + cf0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + cf6: 40 00 18 8a 05 00 frsqrta\.s1 f4,p5=f6 + cfc: 00 00 04 00 nop\.i 0x0 + d00: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + d06: 40 00 18 8a 06 00 frsqrta\.s2 f4,p5=f6 + d0c: 00 00 04 00 nop\.i 0x0 + d10: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + d16: 40 00 18 8a 07 00 frsqrta\.s3 f4,p5=f6 + d1c: 00 00 04 00 nop\.i 0x0 + d20: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + d26: 40 00 18 8a 0c 00 fprsqrta\.s0 f4,p5=f6 + d2c: 00 00 04 00 nop\.i 0x0 + d30: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + d36: 40 00 18 8a 0c 00 fprsqrta\.s0 f4,p5=f6 + d3c: 00 00 04 00 nop\.i 0x0 + d40: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + d46: 40 00 18 8a 0d 00 fprsqrta\.s1 f4,p5=f6 + d4c: 00 00 04 00 nop\.i 0x0 + d50: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + d56: 40 00 18 8a 0e 00 fprsqrta\.s2 f4,p5=f6 + d5c: 00 00 04 00 nop\.i 0x0 + d60: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + d66: 40 00 18 8a 0f 00 fprsqrta\.s3 f4,p5=f6 + d6c: 00 00 04 00 nop\.i 0x0 + d70: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + d76: 40 28 18 28 00 00 fmin\.s0 f4=f5,f6 + d7c: 00 00 04 00 nop\.i 0x0 + d80: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + d86: 40 28 18 28 00 00 fmin\.s0 f4=f5,f6 + d8c: 00 00 04 00 nop\.i 0x0 + d90: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + d96: 40 28 18 28 01 00 fmin\.s1 f4=f5,f6 + d9c: 00 00 04 00 nop\.i 0x0 + da0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + da6: 40 28 18 28 02 00 fmin\.s2 f4=f5,f6 + dac: 00 00 04 00 nop\.i 0x0 + db0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + db6: 40 28 18 28 03 00 fmin\.s3 f4=f5,f6 + dbc: 00 00 04 00 nop\.i 0x0 + dc0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + dc6: 40 28 18 2a 00 00 fmax\.s0 f4=f5,f6 + dcc: 00 00 04 00 nop\.i 0x0 + dd0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + dd6: 40 28 18 2a 00 00 fmax\.s0 f4=f5,f6 + ddc: 00 00 04 00 nop\.i 0x0 + de0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + de6: 40 28 18 2a 01 00 fmax\.s1 f4=f5,f6 + dec: 00 00 04 00 nop\.i 0x0 + df0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + df6: 40 28 18 2a 02 00 fmax\.s2 f4=f5,f6 + dfc: 00 00 04 00 nop\.i 0x0 + e00: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + e06: 40 28 18 2a 03 00 fmax\.s3 f4=f5,f6 + e0c: 00 00 04 00 nop\.i 0x0 + e10: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + e16: 40 28 18 2c 00 00 famin\.s0 f4=f5,f6 + e1c: 00 00 04 00 nop\.i 0x0 + e20: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + e26: 40 28 18 2c 00 00 famin\.s0 f4=f5,f6 + e2c: 00 00 04 00 nop\.i 0x0 + e30: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + e36: 40 28 18 2c 01 00 famin\.s1 f4=f5,f6 + e3c: 00 00 04 00 nop\.i 0x0 + e40: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + e46: 40 28 18 2c 02 00 famin\.s2 f4=f5,f6 + e4c: 00 00 04 00 nop\.i 0x0 + e50: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + e56: 40 28 18 2c 03 00 famin\.s3 f4=f5,f6 + e5c: 00 00 04 00 nop\.i 0x0 + e60: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + e66: 40 28 18 2e 00 00 famax\.s0 f4=f5,f6 + e6c: 00 00 04 00 nop\.i 0x0 + e70: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + e76: 40 28 18 2e 00 00 famax\.s0 f4=f5,f6 + e7c: 00 00 04 00 nop\.i 0x0 + e80: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + e86: 40 28 18 2e 01 00 famax\.s1 f4=f5,f6 + e8c: 00 00 04 00 nop\.i 0x0 + e90: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + e96: 40 28 18 2e 02 00 famax\.s2 f4=f5,f6 + e9c: 00 00 04 00 nop\.i 0x0 + ea0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + ea6: 40 28 18 2e 03 00 famax\.s3 f4=f5,f6 + eac: 00 00 04 00 nop\.i 0x0 + eb0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + eb6: 40 28 18 28 08 00 fpmin\.s0 f4=f5,f6 + ebc: 00 00 04 00 nop\.i 0x0 + ec0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + ec6: 40 28 18 28 08 00 fpmin\.s0 f4=f5,f6 + ecc: 00 00 04 00 nop\.i 0x0 + ed0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + ed6: 40 28 18 28 09 00 fpmin\.s1 f4=f5,f6 + edc: 00 00 04 00 nop\.i 0x0 + ee0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + ee6: 40 28 18 28 0a 00 fpmin\.s2 f4=f5,f6 + eec: 00 00 04 00 nop\.i 0x0 + ef0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + ef6: 40 28 18 28 0b 00 fpmin\.s3 f4=f5,f6 + efc: 00 00 04 00 nop\.i 0x0 + f00: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + f06: 40 28 18 2a 08 00 fpmax\.s0 f4=f5,f6 + f0c: 00 00 04 00 nop\.i 0x0 + f10: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + f16: 40 28 18 2a 08 00 fpmax\.s0 f4=f5,f6 + f1c: 00 00 04 00 nop\.i 0x0 + f20: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + f26: 40 28 18 2a 09 00 fpmax\.s1 f4=f5,f6 + f2c: 00 00 04 00 nop\.i 0x0 + f30: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + f36: 40 28 18 2a 0a 00 fpmax\.s2 f4=f5,f6 + f3c: 00 00 04 00 nop\.i 0x0 + f40: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + f46: 40 28 18 2a 0b 00 fpmax\.s3 f4=f5,f6 + f4c: 00 00 04 00 nop\.i 0x0 + f50: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + f56: 40 28 18 2c 08 00 fpamin\.s0 f4=f5,f6 + f5c: 00 00 04 00 nop\.i 0x0 + f60: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + f66: 40 28 18 2c 08 00 fpamin\.s0 f4=f5,f6 + f6c: 00 00 04 00 nop\.i 0x0 + f70: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + f76: 40 28 18 2c 09 00 fpamin\.s1 f4=f5,f6 + f7c: 00 00 04 00 nop\.i 0x0 + f80: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + f86: 40 28 18 2c 0a 00 fpamin\.s2 f4=f5,f6 + f8c: 00 00 04 00 nop\.i 0x0 + f90: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + f96: 40 28 18 2c 0b 00 fpamin\.s3 f4=f5,f6 + f9c: 00 00 04 00 nop\.i 0x0 + fa0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + fa6: 40 28 18 2e 08 00 fpamax\.s0 f4=f5,f6 + fac: 00 00 04 00 nop\.i 0x0 + fb0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + fb6: 40 28 18 2e 08 00 fpamax\.s0 f4=f5,f6 + fbc: 00 00 04 00 nop\.i 0x0 + fc0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + fc6: 40 28 18 2e 09 00 fpamax\.s1 f4=f5,f6 + fcc: 00 00 04 00 nop\.i 0x0 + fd0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + fd6: 40 28 18 2e 0a 00 fpamax\.s2 f4=f5,f6 + fdc: 00 00 04 00 nop\.i 0x0 + fe0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + fe6: 40 28 18 2e 0b 00 fpamax\.s3 f4=f5,f6 + fec: 00 00 04 00 nop\.i 0x0 + ff0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + ff6: 30 20 14 08 20 00 fcmp\.eq\.s0 p3,p4=f4,f5 + ffc: 00 00 04 00 nop\.i 0x0 + 1000: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1006: 30 20 14 08 20 00 fcmp\.eq\.s0 p3,p4=f4,f5 + 100c: 00 00 04 00 nop\.i 0x0 + 1010: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1016: 30 20 14 08 21 00 fcmp\.eq\.s1 p3,p4=f4,f5 + 101c: 00 00 04 00 nop\.i 0x0 + 1020: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1026: 30 20 14 08 22 00 fcmp\.eq\.s2 p3,p4=f4,f5 + 102c: 00 00 04 00 nop\.i 0x0 + 1030: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1036: 30 20 14 08 23 00 fcmp\.eq\.s3 p3,p4=f4,f5 + 103c: 00 00 04 00 nop\.i 0x0 + 1040: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1046: 30 20 14 08 24 00 fcmp\.lt\.s0 p3,p4=f4,f5 + 104c: 00 00 04 00 nop\.i 0x0 + 1050: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1056: 30 20 14 08 24 00 fcmp\.lt\.s0 p3,p4=f4,f5 + 105c: 00 00 04 00 nop\.i 0x0 + 1060: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1066: 30 20 14 08 25 00 fcmp\.lt\.s1 p3,p4=f4,f5 + 106c: 00 00 04 00 nop\.i 0x0 + 1070: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1076: 30 20 14 08 26 00 fcmp\.lt\.s2 p3,p4=f4,f5 + 107c: 00 00 04 00 nop\.i 0x0 + 1080: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1086: 30 20 14 08 27 00 fcmp\.lt\.s3 p3,p4=f4,f5 + 108c: 00 00 04 00 nop\.i 0x0 + 1090: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1096: 30 20 14 88 20 00 fcmp\.le\.s0 p3,p4=f4,f5 + 109c: 00 00 04 00 nop\.i 0x0 + 10a0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 10a6: 30 20 14 88 20 00 fcmp\.le\.s0 p3,p4=f4,f5 + 10ac: 00 00 04 00 nop\.i 0x0 + 10b0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 10b6: 30 20 14 88 21 00 fcmp\.le\.s1 p3,p4=f4,f5 + 10bc: 00 00 04 00 nop\.i 0x0 + 10c0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 10c6: 30 20 14 88 22 00 fcmp\.le\.s2 p3,p4=f4,f5 + 10cc: 00 00 04 00 nop\.i 0x0 + 10d0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 10d6: 30 20 14 88 23 00 fcmp\.le\.s3 p3,p4=f4,f5 + 10dc: 00 00 04 00 nop\.i 0x0 + 10e0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 10e6: 30 20 14 88 24 00 fcmp\.unord\.s0 p3,p4=f4,f5 + 10ec: 00 00 04 00 nop\.i 0x0 + 10f0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 10f6: 30 20 14 88 24 00 fcmp\.unord\.s0 p3,p4=f4,f5 + 10fc: 00 00 04 00 nop\.i 0x0 + 1100: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1106: 30 20 14 88 25 00 fcmp\.unord\.s1 p3,p4=f4,f5 + 110c: 00 00 04 00 nop\.i 0x0 + 1110: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1116: 30 20 14 88 26 00 fcmp\.unord\.s2 p3,p4=f4,f5 + 111c: 00 00 04 00 nop\.i 0x0 + 1120: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1126: 30 20 14 88 27 00 fcmp\.unord\.s3 p3,p4=f4,f5 + 112c: 00 00 04 00 nop\.i 0x0 + 1130: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1136: 30 28 10 08 24 00 fcmp\.lt\.s0 p3,p4=f5,f4 + 113c: 00 00 04 00 nop\.i 0x0 + 1140: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1146: 30 28 10 08 24 00 fcmp\.lt\.s0 p3,p4=f5,f4 + 114c: 00 00 04 00 nop\.i 0x0 + 1150: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1156: 30 28 10 08 25 00 fcmp\.lt\.s1 p3,p4=f5,f4 + 115c: 00 00 04 00 nop\.i 0x0 + 1160: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1166: 30 28 10 08 26 00 fcmp\.lt\.s2 p3,p4=f5,f4 + 116c: 00 00 04 00 nop\.i 0x0 + 1170: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1176: 30 28 10 08 27 00 fcmp\.lt\.s3 p3,p4=f5,f4 + 117c: 00 00 04 00 nop\.i 0x0 + 1180: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1186: 30 28 10 88 20 00 fcmp\.le\.s0 p3,p4=f5,f4 + 118c: 00 00 04 00 nop\.i 0x0 + 1190: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1196: 30 28 10 88 20 00 fcmp\.le\.s0 p3,p4=f5,f4 + 119c: 00 00 04 00 nop\.i 0x0 + 11a0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 11a6: 30 28 10 88 21 00 fcmp\.le\.s1 p3,p4=f5,f4 + 11ac: 00 00 04 00 nop\.i 0x0 + 11b0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 11b6: 30 28 10 88 22 00 fcmp\.le\.s2 p3,p4=f5,f4 + 11bc: 00 00 04 00 nop\.i 0x0 + 11c0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 11c6: 30 28 10 88 23 00 fcmp\.le\.s3 p3,p4=f5,f4 + 11cc: 00 00 04 00 nop\.i 0x0 + 11d0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 11d6: 40 20 14 06 20 00 fcmp\.eq\.s0 p4,p3=f4,f5 + 11dc: 00 00 04 00 nop\.i 0x0 + 11e0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 11e6: 40 20 14 06 20 00 fcmp\.eq\.s0 p4,p3=f4,f5 + 11ec: 00 00 04 00 nop\.i 0x0 + 11f0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 11f6: 40 20 14 06 21 00 fcmp\.eq\.s1 p4,p3=f4,f5 + 11fc: 00 00 04 00 nop\.i 0x0 + 1200: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1206: 40 20 14 06 22 00 fcmp\.eq\.s2 p4,p3=f4,f5 + 120c: 00 00 04 00 nop\.i 0x0 + 1210: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1216: 40 20 14 06 23 00 fcmp\.eq\.s3 p4,p3=f4,f5 + 121c: 00 00 04 00 nop\.i 0x0 + 1220: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1226: 40 20 14 06 24 00 fcmp\.lt\.s0 p4,p3=f4,f5 + 122c: 00 00 04 00 nop\.i 0x0 + 1230: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1236: 40 20 14 06 24 00 fcmp\.lt\.s0 p4,p3=f4,f5 + 123c: 00 00 04 00 nop\.i 0x0 + 1240: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1246: 40 20 14 06 25 00 fcmp\.lt\.s1 p4,p3=f4,f5 + 124c: 00 00 04 00 nop\.i 0x0 + 1250: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1256: 40 20 14 06 26 00 fcmp\.lt\.s2 p4,p3=f4,f5 + 125c: 00 00 04 00 nop\.i 0x0 + 1260: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1266: 40 20 14 06 27 00 fcmp\.lt\.s3 p4,p3=f4,f5 + 126c: 00 00 04 00 nop\.i 0x0 + 1270: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1276: 40 20 14 86 20 00 fcmp\.le\.s0 p4,p3=f4,f5 + 127c: 00 00 04 00 nop\.i 0x0 + 1280: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1286: 40 20 14 86 20 00 fcmp\.le\.s0 p4,p3=f4,f5 + 128c: 00 00 04 00 nop\.i 0x0 + 1290: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1296: 40 20 14 86 21 00 fcmp\.le\.s1 p4,p3=f4,f5 + 129c: 00 00 04 00 nop\.i 0x0 + 12a0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 12a6: 40 20 14 86 22 00 fcmp\.le\.s2 p4,p3=f4,f5 + 12ac: 00 00 04 00 nop\.i 0x0 + 12b0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 12b6: 40 20 14 86 23 00 fcmp\.le\.s3 p4,p3=f4,f5 + 12bc: 00 00 04 00 nop\.i 0x0 + 12c0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 12c6: 40 28 10 06 24 00 fcmp\.lt\.s0 p4,p3=f5,f4 + 12cc: 00 00 04 00 nop\.i 0x0 + 12d0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 12d6: 40 28 10 06 24 00 fcmp\.lt\.s0 p4,p3=f5,f4 + 12dc: 00 00 04 00 nop\.i 0x0 + 12e0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 12e6: 40 28 10 06 25 00 fcmp\.lt\.s1 p4,p3=f5,f4 + 12ec: 00 00 04 00 nop\.i 0x0 + 12f0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 12f6: 40 28 10 06 26 00 fcmp\.lt\.s2 p4,p3=f5,f4 + 12fc: 00 00 04 00 nop\.i 0x0 + 1300: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1306: 40 28 10 06 27 00 fcmp\.lt\.s3 p4,p3=f5,f4 + 130c: 00 00 04 00 nop\.i 0x0 + 1310: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1316: 40 28 10 86 20 00 fcmp\.le\.s0 p4,p3=f5,f4 + 131c: 00 00 04 00 nop\.i 0x0 + 1320: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1326: 40 28 10 86 20 00 fcmp\.le\.s0 p4,p3=f5,f4 + 132c: 00 00 04 00 nop\.i 0x0 + 1330: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1336: 40 28 10 86 21 00 fcmp\.le\.s1 p4,p3=f5,f4 + 133c: 00 00 04 00 nop\.i 0x0 + 1340: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1346: 40 28 10 86 22 00 fcmp\.le\.s2 p4,p3=f5,f4 + 134c: 00 00 04 00 nop\.i 0x0 + 1350: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1356: 40 28 10 86 23 00 fcmp\.le\.s3 p4,p3=f5,f4 + 135c: 00 00 04 00 nop\.i 0x0 + 1360: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1366: 40 20 14 86 24 00 fcmp\.unord\.s0 p4,p3=f4,f5 + 136c: 00 00 04 00 nop\.i 0x0 + 1370: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1376: 40 20 14 86 24 00 fcmp\.unord\.s0 p4,p3=f4,f5 + 137c: 00 00 04 00 nop\.i 0x0 + 1380: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1386: 40 20 14 86 25 00 fcmp\.unord\.s1 p4,p3=f4,f5 + 138c: 00 00 04 00 nop\.i 0x0 + 1390: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1396: 40 20 14 86 26 00 fcmp\.unord\.s2 p4,p3=f4,f5 + 139c: 00 00 04 00 nop\.i 0x0 + 13a0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 13a6: 40 20 14 86 27 00 fcmp\.unord\.s3 p4,p3=f4,f5 + 13ac: 00 00 04 00 nop\.i 0x0 + 13b0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 13b6: 40 28 18 20 00 00 fmerge\.s f4=f5,f6 + 13bc: 00 00 04 00 nop\.i 0x0 + 13c0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 13c6: 40 28 18 22 00 00 fmerge\.ns f4=f5,f6 + 13cc: 00 00 04 00 nop\.i 0x0 + 13d0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 13d6: 40 28 18 24 00 00 fmerge\.se f4=f5,f6 + 13dc: 00 00 04 00 nop\.i 0x0 + 13e0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 13e6: 40 28 18 72 00 00 fmix\.lr f4=f5,f6 + 13ec: 00 00 04 00 nop\.i 0x0 + 13f0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 13f6: 40 28 18 74 00 00 fmix\.r f4=f5,f6 + 13fc: 00 00 04 00 nop\.i 0x0 + 1400: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1406: 40 28 18 76 00 00 fmix\.l f4=f5,f6 + 140c: 00 00 04 00 nop\.i 0x0 + 1410: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1416: 40 28 18 7a 00 00 fsxt\.l f4=f5,f6 + 141c: 00 00 04 00 nop\.i 0x0 + 1420: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1426: 40 28 18 50 00 00 fpack f4=f5,f6 + 142c: 00 00 04 00 nop\.i 0x0 + 1430: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1436: 40 28 18 68 00 00 fswap f4=f5,f6 + 143c: 00 00 04 00 nop\.i 0x0 + 1440: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1446: 40 28 18 6a 00 00 fswap\.nl f4=f5,f6 + 144c: 00 00 04 00 nop\.i 0x0 + 1450: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1456: 40 28 18 6c 00 00 fswap\.nr f4=f5,f6 + 145c: 00 00 04 00 nop\.i 0x0 + 1460: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1466: 40 28 18 58 00 00 fand f4=f5,f6 + 146c: 00 00 04 00 nop\.i 0x0 + 1470: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1476: 40 28 18 5a 00 00 fandcm f4=f5,f6 + 147c: 00 00 04 00 nop\.i 0x0 + 1480: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1486: 40 28 18 5c 00 00 for f4=f5,f6 + 148c: 00 00 04 00 nop\.i 0x0 + 1490: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1496: 40 28 18 5e 00 00 fxor f4=f5,f6 + 149c: 00 00 04 00 nop\.i 0x0 + 14a0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 14a6: 40 28 18 20 08 00 fpmerge\.s f4=f5,f6 + 14ac: 00 00 04 00 nop\.i 0x0 + 14b0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 14b6: 40 28 18 22 08 00 fpmerge\.ns f4=f5,f6 + 14bc: 00 00 04 00 nop\.i 0x0 + 14c0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 14c6: 40 28 18 24 08 00 fpmerge\.se f4=f5,f6 + 14cc: 00 00 04 00 nop\.i 0x0 + 14d0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 14d6: 40 00 14 20 00 00 fabs f4=f5 + 14dc: 00 00 04 00 nop\.i 0x0 + 14e0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 14e6: 40 28 14 22 00 00 fneg f4=f5 + 14ec: 00 00 04 00 nop\.i 0x0 + 14f0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 14f6: 40 00 14 22 00 00 fnegabs f4=f5 + 14fc: 00 00 04 00 nop\.i 0x0 + 1500: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1506: 40 00 14 20 08 00 fpabs f4=f5 + 150c: 00 00 04 00 nop\.i 0x0 + 1510: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1516: 40 28 14 22 08 00 fpneg f4=f5 + 151c: 00 00 04 00 nop\.i 0x0 + 1520: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1526: 40 00 14 22 08 00 fpnegabs f4=f5 + 152c: 00 00 04 00 nop\.i 0x0 + 1530: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1536: 40 28 00 30 00 00 fcvt\.fx\.s0 f4=f5 + 153c: 00 00 04 00 nop\.i 0x0 + 1540: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1546: 40 28 00 30 00 00 fcvt\.fx\.s0 f4=f5 + 154c: 00 00 04 00 nop\.i 0x0 + 1550: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1556: 40 28 00 30 01 00 fcvt\.fx\.s1 f4=f5 + 155c: 00 00 04 00 nop\.i 0x0 + 1560: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1566: 40 28 00 30 02 00 fcvt\.fx\.s2 f4=f5 + 156c: 00 00 04 00 nop\.i 0x0 + 1570: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1576: 40 28 00 30 03 00 fcvt\.fx\.s3 f4=f5 + 157c: 00 00 04 00 nop\.i 0x0 + 1580: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1586: 40 28 00 34 00 00 fcvt\.fx\.trunc\.s0 f4=f5 + 158c: 00 00 04 00 nop\.i 0x0 + 1590: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1596: 40 28 00 34 00 00 fcvt\.fx\.trunc\.s0 f4=f5 + 159c: 00 00 04 00 nop\.i 0x0 + 15a0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 15a6: 40 28 00 34 01 00 fcvt\.fx\.trunc\.s1 f4=f5 + 15ac: 00 00 04 00 nop\.i 0x0 + 15b0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 15b6: 40 28 00 34 02 00 fcvt\.fx\.trunc\.s2 f4=f5 + 15bc: 00 00 04 00 nop\.i 0x0 + 15c0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 15c6: 40 28 00 34 03 00 fcvt\.fx\.trunc\.s3 f4=f5 + 15cc: 00 00 04 00 nop\.i 0x0 + 15d0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 15d6: 40 28 00 32 00 00 fcvt\.fxu\.s0 f4=f5 + 15dc: 00 00 04 00 nop\.i 0x0 + 15e0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 15e6: 40 28 00 32 00 00 fcvt\.fxu\.s0 f4=f5 + 15ec: 00 00 04 00 nop\.i 0x0 + 15f0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 15f6: 40 28 00 32 01 00 fcvt\.fxu\.s1 f4=f5 + 15fc: 00 00 04 00 nop\.i 0x0 + 1600: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1606: 40 28 00 32 02 00 fcvt\.fxu\.s2 f4=f5 + 160c: 00 00 04 00 nop\.i 0x0 + 1610: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1616: 40 28 00 32 03 00 fcvt\.fxu\.s3 f4=f5 + 161c: 00 00 04 00 nop\.i 0x0 + 1620: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1626: 40 28 00 36 00 00 fcvt\.fxu\.trunc\.s0 f4=f5 + 162c: 00 00 04 00 nop\.i 0x0 + 1630: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1636: 40 28 00 36 00 00 fcvt\.fxu\.trunc\.s0 f4=f5 + 163c: 00 00 04 00 nop\.i 0x0 + 1640: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1646: 40 28 00 36 01 00 fcvt\.fxu\.trunc\.s1 f4=f5 + 164c: 00 00 04 00 nop\.i 0x0 + 1650: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1656: 40 28 00 36 02 00 fcvt\.fxu\.trunc\.s2 f4=f5 + 165c: 00 00 04 00 nop\.i 0x0 + 1660: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1666: 40 28 00 36 03 00 fcvt\.fxu\.trunc\.s3 f4=f5 + 166c: 00 00 04 00 nop\.i 0x0 + 1670: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1676: 40 28 00 30 08 00 fpcvt\.fx\.s0 f4=f5 + 167c: 00 00 04 00 nop\.i 0x0 + 1680: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1686: 40 28 00 30 08 00 fpcvt\.fx\.s0 f4=f5 + 168c: 00 00 04 00 nop\.i 0x0 + 1690: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1696: 40 28 00 30 09 00 fpcvt\.fx\.s1 f4=f5 + 169c: 00 00 04 00 nop\.i 0x0 + 16a0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 16a6: 40 28 00 30 0a 00 fpcvt\.fx\.s2 f4=f5 + 16ac: 00 00 04 00 nop\.i 0x0 + 16b0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 16b6: 40 28 00 30 0b 00 fpcvt\.fx\.s3 f4=f5 + 16bc: 00 00 04 00 nop\.i 0x0 + 16c0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 16c6: 40 28 00 34 08 00 fpcvt\.fx\.trunc\.s0 f4=f5 + 16cc: 00 00 04 00 nop\.i 0x0 + 16d0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 16d6: 40 28 00 34 08 00 fpcvt\.fx\.trunc\.s0 f4=f5 + 16dc: 00 00 04 00 nop\.i 0x0 + 16e0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 16e6: 40 28 00 34 09 00 fpcvt\.fx\.trunc\.s1 f4=f5 + 16ec: 00 00 04 00 nop\.i 0x0 + 16f0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 16f6: 40 28 00 34 0a 00 fpcvt\.fx\.trunc\.s2 f4=f5 + 16fc: 00 00 04 00 nop\.i 0x0 + 1700: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1706: 40 28 00 34 0b 00 fpcvt\.fx\.trunc\.s3 f4=f5 + 170c: 00 00 04 00 nop\.i 0x0 + 1710: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1716: 40 28 00 32 08 00 fpcvt\.fxu\.s0 f4=f5 + 171c: 00 00 04 00 nop\.i 0x0 + 1720: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1726: 40 28 00 32 08 00 fpcvt\.fxu\.s0 f4=f5 + 172c: 00 00 04 00 nop\.i 0x0 + 1730: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1736: 40 28 00 32 09 00 fpcvt\.fxu\.s1 f4=f5 + 173c: 00 00 04 00 nop\.i 0x0 + 1740: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1746: 40 28 00 32 0a 00 fpcvt\.fxu\.s2 f4=f5 + 174c: 00 00 04 00 nop\.i 0x0 + 1750: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1756: 40 28 00 32 0b 00 fpcvt\.fxu\.s3 f4=f5 + 175c: 00 00 04 00 nop\.i 0x0 + 1760: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1766: 40 28 00 36 08 00 fpcvt\.fxu\.trunc\.s0 f4=f5 + 176c: 00 00 04 00 nop\.i 0x0 + 1770: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1776: 40 28 00 36 08 00 fpcvt\.fxu\.trunc\.s0 f4=f5 + 177c: 00 00 04 00 nop\.i 0x0 + 1780: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1786: 40 28 00 36 09 00 fpcvt\.fxu\.trunc\.s1 f4=f5 + 178c: 00 00 04 00 nop\.i 0x0 + 1790: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1796: 40 28 00 36 0a 00 fpcvt\.fxu\.trunc\.s2 f4=f5 + 179c: 00 00 04 00 nop\.i 0x0 + 17a0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 17a6: 40 28 00 36 0b 00 fpcvt\.fxu\.trunc\.s3 f4=f5 + 17ac: 00 00 04 00 nop\.i 0x0 + 17b0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 17b6: 40 28 00 38 00 00 fcvt\.xf f4=f5 + 17bc: 00 00 04 00 nop\.i 0x0 + 17c0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 17c6: 40 00 14 02 40 00 fnorm\.s0 f4=f5 + 17cc: 00 00 04 00 nop\.i 0x0 + 17d0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 17d6: 00 00 00 08 00 00 fsetc\.s0 0x0,0x0 + 17dc: 00 00 04 00 nop\.i 0x0 + 17e0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 17e6: 00 f8 fd 08 00 00 fsetc\.s0 0x3f,0x3f + 17ec: 00 00 04 00 nop\.i 0x0 + 17f0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 17f6: 00 00 00 08 00 00 fsetc\.s0 0x0,0x0 + 17fc: 00 00 04 00 nop\.i 0x0 + 1800: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1806: 00 f8 fd 08 00 00 fsetc\.s0 0x3f,0x3f + 180c: 00 00 04 00 nop\.i 0x0 + 1810: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1816: 00 00 00 08 01 00 fsetc\.s1 0x0,0x0 + 181c: 00 00 04 00 nop\.i 0x0 + 1820: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1826: 00 f8 fd 08 01 00 fsetc\.s1 0x3f,0x3f + 182c: 00 00 04 00 nop\.i 0x0 + 1830: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1836: 00 00 00 08 02 00 fsetc\.s2 0x0,0x0 + 183c: 00 00 04 00 nop\.i 0x0 + 1840: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1846: 00 f8 fd 08 02 00 fsetc\.s2 0x3f,0x3f + 184c: 00 00 04 00 nop\.i 0x0 + 1850: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1856: 00 00 00 08 03 00 fsetc\.s3 0x0,0x0 + 185c: 00 00 04 00 nop\.i 0x0 + 1860: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1866: 00 f8 fd 08 03 00 fsetc\.s3 0x3f,0x3f + 186c: 00 00 04 00 nop\.i 0x0 + 1870: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1876: 00 00 00 0a 00 00 fclrf\.s0 + 187c: 00 00 04 00 nop\.i 0x0 + 1880: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1886: 00 00 00 0a 00 00 fclrf\.s0 + 188c: 00 00 04 00 nop\.i 0x0 + 1890: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1896: 00 00 00 0a 01 00 fclrf\.s1 + 189c: 00 00 04 00 nop\.i 0x0 + 18a0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 18a6: 00 00 00 0a 02 00 fclrf\.s2 + 18ac: 00 00 04 00 nop\.i 0x0 + 18b0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 18b6: 00 00 00 0a 03 00 fclrf\.s3 + 18bc: 00 00 04 00 nop\.i 0x0 + 18c0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 18c6: 40 e7 ff 10 04 00 fchkf\.s0 0 <_start> + 18cc: 00 00 04 00 nop\.i 0x0 + 18d0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 18d6: 30 e7 ff 10 04 00 fchkf\.s0 0 <_start> + 18dc: 00 00 04 00 nop\.i 0x0 + 18e0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 18e6: 20 e7 ff 10 05 00 fchkf\.s1 0 <_start> + 18ec: 00 00 04 00 nop\.i 0x0 + 18f0: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 18f6: 10 e7 ff 10 06 00 fchkf\.s2 0 <_start> + 18fc: 00 00 04 00 nop\.i 0x0 + 1900: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1906: 00 e7 ff 10 07 00 fchkf\.s3 0 <_start> + 190c: 00 00 04 00 nop\.i 0x0 + 1910: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + \.\.\. + 191e: 04 00 0c 00 nop\.i 0x0 + 1922: 00 00 01 00 00 00 \[MFI\] nop\.m 0x0 + 1928: 00 02 00 00 00 00 nop\.f 0x0 + 192e: 04 00 00 00 nop\.i 0x0 diff --git a/gas/testsuite/gas/ia64/opc-f.pl b/gas/testsuite/gas/ia64/opc-f.pl new file mode 100644 index 0000000..d1862c2 --- /dev/null +++ b/gas/testsuite/gas/ia64/opc-f.pl @@ -0,0 +1,163 @@ +print ".text\n\t.type _start,@", "function\n_start:\n\n"; + +@sf = ( "", ".s0", ".s1", ".s2", ".s3" ); + +# Arithmetic + +foreach $i ( "fma", "fma.s", "fma.d", "fpma", + "fms", "fms.s", "fms.d", "fpms", + "fnma", "fnma.s", "fnma.d", "fpnma" ) { + foreach $s (@sf) { + print "\t${i}${s} f4 = f5, f6, f7\n"; + } + print "\n"; +} + +foreach $i ( "fmpy", "fmpy.s", "fmpy.d", "fpmpy", + "fadd", "fadd.s", "fadd.d", #"fpadd", ??? ias doesn't eat it + "fsub", "fsub.s", "fsub.d", "fpsub", + "fnmpy", "fnmpy.s", "fnmpy.d", "fpnmpy" ) { + foreach $s (@sf) { + print "\t${i}${s} f4 = f5, f6\n"; + } + print "\n"; +} + +foreach $i ( "fnorm", "fnorm.s", "fnorm.d" ) { + foreach $s (@sf) { + print "\t${i}${s} f4 = f5\n"; + } + print "\n"; +} + +# Fixed Point Multiply Add + +foreach $s ( ".l", ".lu", ".h", ".hu" ) { + print "\txma${s} f4 = f5, f6, f7\n"; +} +print "\n"; + +foreach $s ( ".l", ".lu", ".h", ".hu" ) { + print "\txmpy${s} f4 = f5, f6\n"; +} +print "\n"; + +# Parallel Floating Point Select + +print "\tfselect f4 = f5, f6, f7\n\n"; + +# Floating Point Compare + +@cmp = ( ".eq", ".lt", ".le", ".unord", ".gt", ".ge", ".neq", ".nlt", + ".nle", ".ngt", ".nge", ".ord" ); + +# Floating Point Class + +foreach $u ( "", ".unc" ) { + foreach $c ( '@nat', '@qnan', '@snan', '@pos', '@neg', '@unorm', + '@norm', '@inf', '0x1ff' ) { + foreach $m ( ".m", ".nm" ) { + print "\tfclass${m}${u} p3, p4 = f4, $c\n"; + } + } + print "\n"; +} + +# Approximation + +foreach $i ( "frcpa", "fprcpa" ) { + foreach $s (@sf) { + print "\t${i}${s} f4, p5 = f6, f7\n"; + } + print "\n"; +} + +foreach $i ( "frsqrta", "fprsqrta" ) { + foreach $s (@sf) { + print "\t${i}${s} f4, p5 = f6\n"; + } + print "\n"; +} + +# Min/Max + +foreach $i ( "fmin", "fmax", "famin", "famax", + "fpmin", "fpmax", "fpamin", "fpamax" ) { + foreach $s (@sf) { + print "\t${i}${s} f4 = f5, f6\n"; + } + print "\n"; +} + +# Parallel Compare + +foreach $c (@cmp) { + foreach $s (@sf) { + print "\tfcmp${c}${u}${s} p3, p4 = f4, f5\n"; + } + print "\n"; +} + +# Merge and Logical + +foreach $i ( "fmerge.s", "fmerge.ns", "fmerge.se", "fmix.lr", "fmix.r", + "fmix.l", "fsxt.l", "fpack", "fswap", "fswap.nl", "fswap.nr", + "fand", "fandcm", "for", "fxor", "fpmerge.s", "fpmerge.ns", + "fpmerge.se" ) { + print "\t$i f4 = f5, f6\n"; +} +print "\n"; + +foreach $i ( "fabs", "fneg", "fnegabs", "fpabs", "fpneg", "fpnegabs" ) { + print "\t$i f4 = f5\n"; +} +print "\n"; + +# Convert Floating to Fixed + +foreach $b ( "fcvt", "fpcvt" ) { + foreach $f ( ".fx", ".fxu" ) { + foreach $t ( "", ".trunc" ) { + foreach $s (@sf) { + print "\t${b}${f}${t}${s} f4 = f5\n"; + } + print "\n"; + } + } +} + +# Convert Fixed to Floating + +foreach $e ( ".xf", ".xuf" ) { + print "\tfcvt$e f4 = f5\n"; +} +print "\n"; + +# Set Controls + +foreach $s (@sf) { + print "\tfsetc$s 0, 0\n"; + print "\tfsetc$s 0x3f, 0x3f\n"; +} +print "\n"; + +# Clear flags + +foreach $s (@sf) { + print "\tfclrf$s\n"; +} +print "\n"; + +# Check flags + +foreach $s (@sf) { + print "\tfchkf$s _start\n"; +} +print "\n"; + +# Misc + +print "\tbreak.f 0\n"; +print "\tnop.f 0\n"; +print "\n"; + diff --git a/gas/testsuite/gas/ia64/opc-f.s b/gas/testsuite/gas/ia64/opc-f.s new file mode 100644 index 0000000..8784bb9 --- /dev/null +++ b/gas/testsuite/gas/ia64/opc-f.s @@ -0,0 +1,481 @@ +.text + .type _start,@function +_start: + + fma f4 = f5, f6, f7 + fma.s0 f4 = f5, f6, f7 + fma.s1 f4 = f5, f6, f7 + fma.s2 f4 = f5, f6, f7 + fma.s3 f4 = f5, f6, f7 + + fma.s f4 = f5, f6, f7 + fma.s.s0 f4 = f5, f6, f7 + fma.s.s1 f4 = f5, f6, f7 + fma.s.s2 f4 = f5, f6, f7 + fma.s.s3 f4 = f5, f6, f7 + + fma.d f4 = f5, f6, f7 + fma.d.s0 f4 = f5, f6, f7 + fma.d.s1 f4 = f5, f6, f7 + fma.d.s2 f4 = f5, f6, f7 + fma.d.s3 f4 = f5, f6, f7 + + fpma f4 = f5, f6, f7 + fpma.s0 f4 = f5, f6, f7 + fpma.s1 f4 = f5, f6, f7 + fpma.s2 f4 = f5, f6, f7 + fpma.s3 f4 = f5, f6, f7 + + fms f4 = f5, f6, f7 + fms.s0 f4 = f5, f6, f7 + fms.s1 f4 = f5, f6, f7 + fms.s2 f4 = f5, f6, f7 + fms.s3 f4 = f5, f6, f7 + + fms.s f4 = f5, f6, f7 + fms.s.s0 f4 = f5, f6, f7 + fms.s.s1 f4 = f5, f6, f7 + fms.s.s2 f4 = f5, f6, f7 + fms.s.s3 f4 = f5, f6, f7 + + fms.d f4 = f5, f6, f7 + fms.d.s0 f4 = f5, f6, f7 + fms.d.s1 f4 = f5, f6, f7 + fms.d.s2 f4 = f5, f6, f7 + fms.d.s3 f4 = f5, f6, f7 + + fpms f4 = f5, f6, f7 + fpms.s0 f4 = f5, f6, f7 + fpms.s1 f4 = f5, f6, f7 + fpms.s2 f4 = f5, f6, f7 + fpms.s3 f4 = f5, f6, f7 + + fnma f4 = f5, f6, f7 + fnma.s0 f4 = f5, f6, f7 + fnma.s1 f4 = f5, f6, f7 + fnma.s2 f4 = f5, f6, f7 + fnma.s3 f4 = f5, f6, f7 + + fnma.s f4 = f5, f6, f7 + fnma.s.s0 f4 = f5, f6, f7 + fnma.s.s1 f4 = f5, f6, f7 + fnma.s.s2 f4 = f5, f6, f7 + fnma.s.s3 f4 = f5, f6, f7 + + fnma.d f4 = f5, f6, f7 + fnma.d.s0 f4 = f5, f6, f7 + fnma.d.s1 f4 = f5, f6, f7 + fnma.d.s2 f4 = f5, f6, f7 + fnma.d.s3 f4 = f5, f6, f7 + + fpnma f4 = f5, f6, f7 + fpnma.s0 f4 = f5, f6, f7 + fpnma.s1 f4 = f5, f6, f7 + fpnma.s2 f4 = f5, f6, f7 + fpnma.s3 f4 = f5, f6, f7 + + fmpy f4 = f5, f6 + fmpy.s0 f4 = f5, f6 + fmpy.s1 f4 = f5, f6 + fmpy.s2 f4 = f5, f6 + fmpy.s3 f4 = f5, f6 + + fmpy.s f4 = f5, f6 + fmpy.s.s0 f4 = f5, f6 + fmpy.s.s1 f4 = f5, f6 + fmpy.s.s2 f4 = f5, f6 + fmpy.s.s3 f4 = f5, f6 + + fmpy.d f4 = f5, f6 + fmpy.d.s0 f4 = f5, f6 + fmpy.d.s1 f4 = f5, f6 + fmpy.d.s2 f4 = f5, f6 + fmpy.d.s3 f4 = f5, f6 + + fpmpy f4 = f5, f6 + fpmpy.s0 f4 = f5, f6 + fpmpy.s1 f4 = f5, f6 + fpmpy.s2 f4 = f5, f6 + fpmpy.s3 f4 = f5, f6 + + fadd f4 = f5, f6 + fadd.s0 f4 = f5, f6 + fadd.s1 f4 = f5, f6 + fadd.s2 f4 = f5, f6 + fadd.s3 f4 = f5, f6 + + fadd.s f4 = f5, f6 + fadd.s.s0 f4 = f5, f6 + fadd.s.s1 f4 = f5, f6 + fadd.s.s2 f4 = f5, f6 + fadd.s.s3 f4 = f5, f6 + + fadd.d f4 = f5, f6 + fadd.d.s0 f4 = f5, f6 + fadd.d.s1 f4 = f5, f6 + fadd.d.s2 f4 = f5, f6 + fadd.d.s3 f4 = f5, f6 + + fsub f4 = f5, f6 + fsub.s0 f4 = f5, f6 + fsub.s1 f4 = f5, f6 + fsub.s2 f4 = f5, f6 + fsub.s3 f4 = f5, f6 + + fsub.s f4 = f5, f6 + fsub.s.s0 f4 = f5, f6 + fsub.s.s1 f4 = f5, f6 + fsub.s.s2 f4 = f5, f6 + fsub.s.s3 f4 = f5, f6 + + fsub.d f4 = f5, f6 + fsub.d.s0 f4 = f5, f6 + fsub.d.s1 f4 = f5, f6 + fsub.d.s2 f4 = f5, f6 + fsub.d.s3 f4 = f5, f6 + + fpsub f4 = f5, f6 + fpsub.s0 f4 = f5, f6 + fpsub.s1 f4 = f5, f6 + fpsub.s2 f4 = f5, f6 + fpsub.s3 f4 = f5, f6 + + fnmpy f4 = f5, f6 + fnmpy.s0 f4 = f5, f6 + fnmpy.s1 f4 = f5, f6 + fnmpy.s2 f4 = f5, f6 + fnmpy.s3 f4 = f5, f6 + + fnmpy.s f4 = f5, f6 + fnmpy.s.s0 f4 = f5, f6 + fnmpy.s.s1 f4 = f5, f6 + fnmpy.s.s2 f4 = f5, f6 + fnmpy.s.s3 f4 = f5, f6 + + fnmpy.d f4 = f5, f6 + fnmpy.d.s0 f4 = f5, f6 + fnmpy.d.s1 f4 = f5, f6 + fnmpy.d.s2 f4 = f5, f6 + fnmpy.d.s3 f4 = f5, f6 + + fpnmpy f4 = f5, f6 + fpnmpy.s0 f4 = f5, f6 + fpnmpy.s1 f4 = f5, f6 + fpnmpy.s2 f4 = f5, f6 + fpnmpy.s3 f4 = f5, f6 + + fnorm f4 = f5 + fnorm.s0 f4 = f5 + fnorm.s1 f4 = f5 + fnorm.s2 f4 = f5 + fnorm.s3 f4 = f5 + + fnorm.s f4 = f5 + fnorm.s.s0 f4 = f5 + fnorm.s.s1 f4 = f5 + fnorm.s.s2 f4 = f5 + fnorm.s.s3 f4 = f5 + + fnorm.d f4 = f5 + fnorm.d.s0 f4 = f5 + fnorm.d.s1 f4 = f5 + fnorm.d.s2 f4 = f5 + fnorm.d.s3 f4 = f5 + + xma.l f4 = f5, f6, f7 + xma.lu f4 = f5, f6, f7 + xma.h f4 = f5, f6, f7 + xma.hu f4 = f5, f6, f7 + + xmpy.l f4 = f5, f6 + xmpy.lu f4 = f5, f6 + xmpy.h f4 = f5, f6 + xmpy.hu f4 = f5, f6 + + fselect f4 = f5, f6, f7 + + fclass.m p3, p4 = f4, @nat + fclass.nm p3, p4 = f4, @nat + fclass.m p3, p4 = f4, @qnan + fclass.nm p3, p4 = f4, @qnan + fclass.m p3, p4 = f4, @snan + fclass.nm p3, p4 = f4, @snan + fclass.m p3, p4 = f4, @pos + fclass.nm p3, p4 = f4, @pos + fclass.m p3, p4 = f4, @neg + fclass.nm p3, p4 = f4, @neg + fclass.m p3, p4 = f4, @unorm + fclass.nm p3, p4 = f4, @unorm + fclass.m p3, p4 = f4, @norm + fclass.nm p3, p4 = f4, @norm + fclass.m p3, p4 = f4, @inf + fclass.nm p3, p4 = f4, @inf + fclass.m p3, p4 = f4, 0x1ff + fclass.nm p3, p4 = f4, 0x1ff + + fclass.m.unc p3, p4 = f4, @nat + fclass.nm.unc p3, p4 = f4, @nat + fclass.m.unc p3, p4 = f4, @qnan + fclass.nm.unc p3, p4 = f4, @qnan + fclass.m.unc p3, p4 = f4, @snan + fclass.nm.unc p3, p4 = f4, @snan + fclass.m.unc p3, p4 = f4, @pos + fclass.nm.unc p3, p4 = f4, @pos + fclass.m.unc p3, p4 = f4, @neg + fclass.nm.unc p3, p4 = f4, @neg + fclass.m.unc p3, p4 = f4, @unorm + fclass.nm.unc p3, p4 = f4, @unorm + fclass.m.unc p3, p4 = f4, @norm + fclass.nm.unc p3, p4 = f4, @norm + fclass.m.unc p3, p4 = f4, @inf + fclass.nm.unc p3, p4 = f4, @inf + fclass.m.unc p3, p4 = f4, 0x1ff + fclass.nm.unc p3, p4 = f4, 0x1ff + + frcpa f4, p5 = f6, f7 + frcpa.s0 f4, p5 = f6, f7 + frcpa.s1 f4, p5 = f6, f7 + frcpa.s2 f4, p5 = f6, f7 + frcpa.s3 f4, p5 = f6, f7 + + fprcpa f4, p5 = f6, f7 + fprcpa.s0 f4, p5 = f6, f7 + fprcpa.s1 f4, p5 = f6, f7 + fprcpa.s2 f4, p5 = f6, f7 + fprcpa.s3 f4, p5 = f6, f7 + + frsqrta f4, p5 = f6 + frsqrta.s0 f4, p5 = f6 + frsqrta.s1 f4, p5 = f6 + frsqrta.s2 f4, p5 = f6 + frsqrta.s3 f4, p5 = f6 + + fprsqrta f4, p5 = f6 + fprsqrta.s0 f4, p5 = f6 + fprsqrta.s1 f4, p5 = f6 + fprsqrta.s2 f4, p5 = f6 + fprsqrta.s3 f4, p5 = f6 + + fmin f4 = f5, f6 + fmin.s0 f4 = f5, f6 + fmin.s1 f4 = f5, f6 + fmin.s2 f4 = f5, f6 + fmin.s3 f4 = f5, f6 + + fmax f4 = f5, f6 + fmax.s0 f4 = f5, f6 + fmax.s1 f4 = f5, f6 + fmax.s2 f4 = f5, f6 + fmax.s3 f4 = f5, f6 + + famin f4 = f5, f6 + famin.s0 f4 = f5, f6 + famin.s1 f4 = f5, f6 + famin.s2 f4 = f5, f6 + famin.s3 f4 = f5, f6 + + famax f4 = f5, f6 + famax.s0 f4 = f5, f6 + famax.s1 f4 = f5, f6 + famax.s2 f4 = f5, f6 + famax.s3 f4 = f5, f6 + + fpmin f4 = f5, f6 + fpmin.s0 f4 = f5, f6 + fpmin.s1 f4 = f5, f6 + fpmin.s2 f4 = f5, f6 + fpmin.s3 f4 = f5, f6 + + fpmax f4 = f5, f6 + fpmax.s0 f4 = f5, f6 + fpmax.s1 f4 = f5, f6 + fpmax.s2 f4 = f5, f6 + fpmax.s3 f4 = f5, f6 + + fpamin f4 = f5, f6 + fpamin.s0 f4 = f5, f6 + fpamin.s1 f4 = f5, f6 + fpamin.s2 f4 = f5, f6 + fpamin.s3 f4 = f5, f6 + + fpamax f4 = f5, f6 + fpamax.s0 f4 = f5, f6 + fpamax.s1 f4 = f5, f6 + fpamax.s2 f4 = f5, f6 + fpamax.s3 f4 = f5, f6 + + fcmp.eq p3, p4 = f4, f5 + fcmp.eq.s0 p3, p4 = f4, f5 + fcmp.eq.s1 p3, p4 = f4, f5 + fcmp.eq.s2 p3, p4 = f4, f5 + fcmp.eq.s3 p3, p4 = f4, f5 + + fcmp.lt p3, p4 = f4, f5 + fcmp.lt.s0 p3, p4 = f4, f5 + fcmp.lt.s1 p3, p4 = f4, f5 + fcmp.lt.s2 p3, p4 = f4, f5 + fcmp.lt.s3 p3, p4 = f4, f5 + + fcmp.le p3, p4 = f4, f5 + fcmp.le.s0 p3, p4 = f4, f5 + fcmp.le.s1 p3, p4 = f4, f5 + fcmp.le.s2 p3, p4 = f4, f5 + fcmp.le.s3 p3, p4 = f4, f5 + + fcmp.unord p3, p4 = f4, f5 + fcmp.unord.s0 p3, p4 = f4, f5 + fcmp.unord.s1 p3, p4 = f4, f5 + fcmp.unord.s2 p3, p4 = f4, f5 + fcmp.unord.s3 p3, p4 = f4, f5 + + fcmp.gt p3, p4 = f4, f5 + fcmp.gt.s0 p3, p4 = f4, f5 + fcmp.gt.s1 p3, p4 = f4, f5 + fcmp.gt.s2 p3, p4 = f4, f5 + fcmp.gt.s3 p3, p4 = f4, f5 + + fcmp.ge p3, p4 = f4, f5 + fcmp.ge.s0 p3, p4 = f4, f5 + fcmp.ge.s1 p3, p4 = f4, f5 + fcmp.ge.s2 p3, p4 = f4, f5 + fcmp.ge.s3 p3, p4 = f4, f5 + + fcmp.neq p3, p4 = f4, f5 + fcmp.neq.s0 p3, p4 = f4, f5 + fcmp.neq.s1 p3, p4 = f4, f5 + fcmp.neq.s2 p3, p4 = f4, f5 + fcmp.neq.s3 p3, p4 = f4, f5 + + fcmp.nlt p3, p4 = f4, f5 + fcmp.nlt.s0 p3, p4 = f4, f5 + fcmp.nlt.s1 p3, p4 = f4, f5 + fcmp.nlt.s2 p3, p4 = f4, f5 + fcmp.nlt.s3 p3, p4 = f4, f5 + + fcmp.nle p3, p4 = f4, f5 + fcmp.nle.s0 p3, p4 = f4, f5 + fcmp.nle.s1 p3, p4 = f4, f5 + fcmp.nle.s2 p3, p4 = f4, f5 + fcmp.nle.s3 p3, p4 = f4, f5 + + fcmp.ngt p3, p4 = f4, f5 + fcmp.ngt.s0 p3, p4 = f4, f5 + fcmp.ngt.s1 p3, p4 = f4, f5 + fcmp.ngt.s2 p3, p4 = f4, f5 + fcmp.ngt.s3 p3, p4 = f4, f5 + + fcmp.nge p3, p4 = f4, f5 + fcmp.nge.s0 p3, p4 = f4, f5 + fcmp.nge.s1 p3, p4 = f4, f5 + fcmp.nge.s2 p3, p4 = f4, f5 + fcmp.nge.s3 p3, p4 = f4, f5 + + fcmp.ord p3, p4 = f4, f5 + fcmp.ord.s0 p3, p4 = f4, f5 + fcmp.ord.s1 p3, p4 = f4, f5 + fcmp.ord.s2 p3, p4 = f4, f5 + fcmp.ord.s3 p3, p4 = f4, f5 + + fmerge.s f4 = f5, f6 + fmerge.ns f4 = f5, f6 + fmerge.se f4 = f5, f6 + fmix.lr f4 = f5, f6 + fmix.r f4 = f5, f6 + fmix.l f4 = f5, f6 + fsxt.l f4 = f5, f6 + fpack f4 = f5, f6 + fswap f4 = f5, f6 + fswap.nl f4 = f5, f6 + fswap.nr f4 = f5, f6 + fand f4 = f5, f6 + fandcm f4 = f5, f6 + for f4 = f5, f6 + fxor f4 = f5, f6 + fpmerge.s f4 = f5, f6 + fpmerge.ns f4 = f5, f6 + fpmerge.se f4 = f5, f6 + + fabs f4 = f5 + fneg f4 = f5 + fnegabs f4 = f5 + fpabs f4 = f5 + fpneg f4 = f5 + fpnegabs f4 = f5 + + fcvt.fx f4 = f5 + fcvt.fx.s0 f4 = f5 + fcvt.fx.s1 f4 = f5 + fcvt.fx.s2 f4 = f5 + fcvt.fx.s3 f4 = f5 + + fcvt.fx.trunc f4 = f5 + fcvt.fx.trunc.s0 f4 = f5 + fcvt.fx.trunc.s1 f4 = f5 + fcvt.fx.trunc.s2 f4 = f5 + fcvt.fx.trunc.s3 f4 = f5 + + fcvt.fxu f4 = f5 + fcvt.fxu.s0 f4 = f5 + fcvt.fxu.s1 f4 = f5 + fcvt.fxu.s2 f4 = f5 + fcvt.fxu.s3 f4 = f5 + + fcvt.fxu.trunc f4 = f5 + fcvt.fxu.trunc.s0 f4 = f5 + fcvt.fxu.trunc.s1 f4 = f5 + fcvt.fxu.trunc.s2 f4 = f5 + fcvt.fxu.trunc.s3 f4 = f5 + + fpcvt.fx f4 = f5 + fpcvt.fx.s0 f4 = f5 + fpcvt.fx.s1 f4 = f5 + fpcvt.fx.s2 f4 = f5 + fpcvt.fx.s3 f4 = f5 + + fpcvt.fx.trunc f4 = f5 + fpcvt.fx.trunc.s0 f4 = f5 + fpcvt.fx.trunc.s1 f4 = f5 + fpcvt.fx.trunc.s2 f4 = f5 + fpcvt.fx.trunc.s3 f4 = f5 + + fpcvt.fxu f4 = f5 + fpcvt.fxu.s0 f4 = f5 + fpcvt.fxu.s1 f4 = f5 + fpcvt.fxu.s2 f4 = f5 + fpcvt.fxu.s3 f4 = f5 + + fpcvt.fxu.trunc f4 = f5 + fpcvt.fxu.trunc.s0 f4 = f5 + fpcvt.fxu.trunc.s1 f4 = f5 + fpcvt.fxu.trunc.s2 f4 = f5 + fpcvt.fxu.trunc.s3 f4 = f5 + + fcvt.xf f4 = f5 + fcvt.xuf f4 = f5 + + fsetc 0, 0 + fsetc 0x3f, 0x3f + fsetc.s0 0, 0 + fsetc.s0 0x3f, 0x3f + fsetc.s1 0, 0 + fsetc.s1 0x3f, 0x3f + fsetc.s2 0, 0 + fsetc.s2 0x3f, 0x3f + fsetc.s3 0, 0 + fsetc.s3 0x3f, 0x3f + + fclrf + fclrf.s0 + fclrf.s1 + fclrf.s2 + fclrf.s3 + + fchkf _start + fchkf.s0 _start + fchkf.s1 _start + fchkf.s2 _start + fchkf.s3 _start + + break.f 0 + nop.f 0 + diff --git a/gas/testsuite/gas/ia64/opc-i.d b/gas/testsuite/gas/ia64/opc-i.d new file mode 100644 index 0000000..5b108fe --- /dev/null +++ b/gas/testsuite/gas/ia64/opc-i.d @@ -0,0 +1,245 @@ +# objdump: -d +# name: ia64 opc-i + +.*: +file format .* + +Disassembly of section \.text: + +0000000000000000 <_start>: + 0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 6: 40 28 18 8c 38 80 pmpyshr2 r4=r5,r6,0 + c: 50 30 68 71 pmpyshr2\.u r4=r5,r6,16 + 10: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 16: 40 28 18 b4 3a 80 pmpy2\.r r4=r5,r6 + 1c: 50 30 78 75 pmpy2\.l r4=r5,r6 + 20: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 26: 40 28 18 20 3a 80 mix1\.r r4=r5,r6 + 2c: 50 30 40 75 mix2\.r r4=r5,r6 + 30: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 36: 40 28 18 20 3e 80 mix4\.r r4=r5,r6 + 3c: 50 30 50 74 mix1\.l r4=r5,r6 + 40: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 46: 40 28 18 a8 3a 80 mix2\.l r4=r5,r6 + 4c: 50 30 50 7c mix4\.l r4=r5,r6 + 50: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 56: 40 28 18 80 3a 80 pack2\.uss r4=r5,r6 + 5c: 50 30 10 75 pack2\.sss r4=r5,r6 + 60: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 66: 40 28 18 08 3e 80 pack4\.sss r4=r5,r6 + 6c: 50 30 20 74 unpack1\.h r4=r5,r6 + 70: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 76: 40 28 18 90 3a 80 unpack2\.h r4=r5,r6 + 7c: 50 30 20 7c unpack4\.h r4=r5,r6 + 80: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 86: 40 28 18 18 3a 80 unpack1\.l r4=r5,r6 + 8c: 50 30 30 75 unpack2\.l r4=r5,r6 + 90: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 96: 40 28 18 18 3e 80 unpack4\.l r4=r5,r6 + 9c: 50 30 08 74 pmin1\.u r4=r5,r6 + a0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + a6: 40 28 18 14 3a 80 pmax1\.u r4=r5,r6 + ac: 50 30 18 75 pmin2\.u r4=r5,r6 + b0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + b6: 40 28 18 9c 3a 80 pmax2\.u r4=r5,r6 + bc: 50 30 58 74 psad1 r4=r5,r6 + c0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + c6: 40 28 2c 28 3b 80 mux1 r4=r5,@rev + cc: 50 40 50 76 mux1 r4=r5,@mix + d0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + d6: 40 28 24 28 3b 80 mux1 r4=r5,@shuf + dc: 50 50 50 76 mux1 r4=r5,@alt + e0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + e6: 40 28 00 28 3b 80 mux1 r4=r5,@brcst + ec: 50 00 50 77 mux2 r4=r5,0x0 + f0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + f6: 40 28 fc ab 3b 80 mux2 r4=r5,0xff + fc: 50 50 55 77 mux2 r4=r5,0xaa + 100: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 106: 40 30 14 88 38 80 pshr2 r4=r5,r6 + 10c: 00 28 18 73 pshr2 r4=r5,0 + 110: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 116: 40 80 14 8c 39 80 pshr2 r4=r5,8 + 11c: e0 2b 18 73 pshr2 r4=r5,31 + 120: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 126: 40 30 14 08 3c 80 pshr4 r4=r5,r6 + 12c: 00 28 18 7a pshr4 r4=r5,0 + 130: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 136: 40 80 14 0c 3d 80 pshr4 r4=r5,8 + 13c: e0 2b 18 7a pshr4 r4=r5,31 + 140: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 146: 40 30 14 80 38 80 pshr2\.u r4=r5,r6 + 14c: 00 28 08 73 pshr2\.u r4=r5,0 + 150: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 156: 40 80 14 84 39 80 pshr2\.u r4=r5,8 + 15c: e0 2b 08 73 pshr2\.u r4=r5,31 + 160: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 166: 40 30 14 00 3c 80 pshr4\.u r4=r5,r6 + 16c: 00 28 08 7a pshr4\.u r4=r5,0 + 170: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 176: 40 80 14 04 3d 80 pshr4\.u r4=r5,8 + 17c: e0 2b 08 7a pshr4\.u r4=r5,31 + 180: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 186: 40 30 14 88 3c 80 shr r4=r5,r6 + 18c: 60 28 00 79 shr\.u r4=r5,r6 + 190: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 196: 40 28 18 90 38 80 pshl2 r4=r5,r6 + 19c: 50 f8 28 77 pshl2 r4=r5,0 + 1a0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 1a6: 40 28 5c 94 3b 80 pshl2 r4=r5,8 + 1ac: 50 00 28 77 pshl2 r4=r5,31 + 1b0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 1b6: 40 28 18 10 3c 80 pshl4 r4=r5,r6 + 1bc: 50 f8 28 7e pshl4 r4=r5,0 + 1c0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 1c6: 40 28 5c 14 3f 80 pshl4 r4=r5,8 + 1cc: 50 00 28 7e pshl4 r4=r5,31 + 1d0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 1d6: 40 28 18 90 3c 80 shl r4=r5,r6 + 1dc: 00 28 48 73 popcnt r4=r5 + 1e0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 1e6: 40 28 18 00 2b 80 shrp r4=r5,r6,0 + 1ec: 50 30 30 56 shrp r4=r5,r6,12 + 1f0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 1f6: 40 28 18 7e 2b 80 shrp r4=r5,r6,63 + 1fc: 10 28 3c 52 extr r4=r5,0,16 + 200: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 206: 40 08 14 7c 29 80 extr r4=r5,0,63 + 20c: 50 29 9c 52 extr r4=r5,10,40 + 210: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 216: 40 00 14 1e 29 80 extr\.u r4=r5,0,16 + 21c: 00 28 f8 52 extr\.u r4=r5,0,63 + 220: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 226: 40 a0 14 4e 29 80 extr\.u r4=r5,10,40 + 22c: 50 f8 3d 53 dep\.z r4=r5,0,16 + 230: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 236: 40 28 fc fc 29 80 dep\.z r4=r5,0,63 + 23c: 50 a8 9d 53 dep\.z r4=r5,10,40 + 240: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 246: 40 00 fc 9f 29 80 dep\.z r4=0,0,16 + 24c: f0 ff fb 53 dep\.z r4=127,0,63 + 250: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 256: 40 00 e8 e3 2d 80 dep\.z r4=-128,5,50 + 25c: 50 ad 9f 53 dep\.z r4=85,10,40 + 260: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 266: 40 f0 17 9e 2b 80 dep r4=0,r5,0,16 + 26c: e0 2f f8 5f dep r4=-1,r5,0,63 + 270: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 276: 00 00 00 02 00 80 nop\.f 0x0 + 27c: 50 30 58 4d dep r4=r5,r6,10,7 + 280: 04 00 00 00 01 00 \[MLI\] nop\.m 0x0 + 286: 00 00 00 00 00 80 movl r4=0x0 + 28c: 00 00 00 60 + 290: 04 00 00 00 01 c0 \[MLI\] nop\.m 0x0 + 296: ff ff ff ff 7f 80 movl r4=0xffffffffffffffff + 29c: f0 f7 ff 6f + 2a0: 04 00 00 00 01 80 \[MLI\] nop\.m 0x0 + 2a6: 90 78 56 34 12 80 movl r4=0x1234567890abcdef + 2ac: f0 76 6d 66 + 2b0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 2b6: 00 00 00 00 00 e0 break\.i 0x0 + 2bc: ff ff 01 08 break\.i 0x1fffff + 2c0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 2c6: 00 00 00 02 00 e0 nop\.i 0x0 + 2cc: ff ff 05 08 nop\.i 0x1fffff + 2d0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 2d6: 30 25 fc ff 04 80 chk\.s\.i r4,0 <_start> + 2dc: 00 00 c4 00 mov r4=b0 + 2e0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 2e6: 00 20 04 80 03 00 mov b0=r4 + 2ec: 40 00 00 03 mov pr=r4,0x0 + 2f0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 2f6: a0 21 80 84 01 e0 mov pr=r4,0x1234 + 2fc: 4f 80 7f 0b mov pr=r4,0xfffffffffffffffe + 300: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 306: 00 00 00 00 01 e0 mov pr\.rot=0x0 + 30c: 7f 00 00 02 mov pr\.rot=0x3ff0000 + 310: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 316: 00 c0 ff 7f 05 80 mov pr\.rot=0xfffffffffc000000 + 31c: 00 28 40 00 zxt1 r4=r5 + 320: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 326: 40 00 14 22 00 80 zxt2 r4=r5 + 32c: 00 28 48 00 zxt4 r4=r5 + 330: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 336: 40 00 14 28 00 80 sxt1 r4=r5 + 33c: 00 28 54 00 sxt2 r4=r5 + 340: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 346: 40 00 14 2c 00 80 sxt4 r4=r5 + 34c: 00 28 60 00 czx1\.l r4=r5 + 350: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 356: 40 00 14 32 00 80 czx2\.l r4=r5 + 35c: 00 28 70 00 czx1\.r r4=r5 + 360: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 366: 40 00 14 3a 00 40 czx2\.r r4=r5 + 36c: 00 20 0c 50 tbit\.z p2,p3=r4,0 + 370: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 376: 20 14 10 06 28 40 tbit\.z\.unc p2,p3=r4,1 + 37c: 40 20 0c 58 tbit\.z\.and p2,p3=r4,2 + 380: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 386: 20 30 10 86 28 40 tbit\.z\.or p2,p3=r4,3 + 38c: 80 20 0c 59 tbit\.z\.or\.andcm p2,p3=r4,4 + 390: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 396: 20 54 10 86 28 40 tbit\.nz\.or p2,p3=r4,5 + 39c: c8 20 0c 58 tbit\.nz\.and p2,p3=r4,6 + 3a0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 3a6: 30 74 10 84 2c 60 tbit\.nz\.or\.andcm p3,p2=r4,7 + 3ac: 00 21 08 50 tbit\.z p3,p2=r4,8 + 3b0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 3b6: 30 94 10 04 28 40 tbit\.z\.unc p3,p2=r4,9 + 3bc: 48 21 0c 58 tbit\.nz\.and p2,p3=r4,10 + 3c0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 3c6: 20 b4 10 86 28 40 tbit\.nz\.or p2,p3=r4,11 + 3cc: 88 21 0c 59 tbit\.nz\.or\.andcm p2,p3=r4,12 + 3d0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 3d6: 20 d0 10 86 28 40 tbit\.z\.or p2,p3=r4,13 + 3dc: c0 21 0c 58 tbit\.z\.and p2,p3=r4,14 + 3e0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 3e6: 30 f0 10 84 2c 40 tbit\.z\.or\.andcm p3,p2=r4,15 + 3ec: 10 20 0c 50 tnat\.z p2,p3=r4 + 3f0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 3f6: 20 0c 10 06 28 40 tnat\.z\.unc p2,p3=r4 + 3fc: 10 20 0c 58 tnat\.z\.and p2,p3=r4 + 400: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 406: 20 08 10 86 28 40 tnat\.z\.or p2,p3=r4 + 40c: 10 20 0c 59 tnat\.z\.or\.andcm p2,p3=r4 + 410: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 416: 20 0c 10 86 28 40 tnat\.nz\.or p2,p3=r4 + 41c: 18 20 0c 58 tnat\.nz\.and p2,p3=r4 + 420: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 426: 30 0c 10 84 2c 60 tnat\.nz\.or\.andcm p3,p2=r4 + 42c: 10 20 08 50 tnat\.z p3,p2=r4 + 430: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 436: 30 0c 10 04 28 40 tnat\.z\.unc p3,p2=r4 + 43c: 18 20 0c 58 tnat\.nz\.and p2,p3=r4 + 440: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 446: 20 0c 10 86 28 40 tnat\.nz\.or p2,p3=r4 + 44c: 18 20 0c 59 tnat\.nz\.or\.andcm p2,p3=r4 + 450: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 456: 20 08 10 86 28 40 tnat\.z\.or p2,p3=r4 + 45c: 10 20 0c 58 tnat\.z\.and p2,p3=r4 + 460: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 + 466: 30 08 10 84 2c 60 tnat\.z\.or\.andcm p3,p2=r4 + 46c: 40 88 04 07 mov b3=r4 + 470: 01 00 00 00 01 00 \[MII\] nop\.m 0x0 + 476: 30 20 24 84 03 00 mov\.imp b3=r4,570 <_start\+0x570> + 47c: 00 00 04 00 nop\.i 0x0;; + \.\.\. + 570: 01 00 00 00 01 00 \[MII\] nop\.m 0x0 + 576: 30 20 00 84 03 60 mov\.sptk b3=r4,670 <_start\+0x670> + 57c: 40 40 08 07 mov\.sptk\.imp b3=r4,670 <_start\+0x670>;; + \.\.\. + 670: 01 00 00 00 01 00 \[MII\] nop\.m 0x0 + 676: 30 20 08 84 03 60 mov\.dptk b3=r4,770 <_start\+0x770> + 67c: 40 50 08 07 mov\.dptk\.imp b3=r4,770 <_start\+0x770>;; + \.\.\. + 770: 01 00 00 00 01 00 \[MII\] nop\.m 0x0 + 776: 30 20 14 84 03 60 mov\.ret b3=r4,870 <_start\+0x870> + 77c: 40 68 08 07 mov\.ret\.imp b3=r4,870 <_start\+0x870>;; + \.\.\. + 870: 01 00 00 00 01 00 \[MII\] nop\.m 0x0 + 876: 30 20 10 84 03 60 mov\.ret\.sptk b3=r4,970 <_start\+0x970> + 87c: 40 60 08 07 mov\.ret\.sptk\.imp b3=r4,970 <_start\+0x970>;; + \.\.\. + 970: 01 00 00 00 01 00 \[MII\] nop\.m 0x0 + 976: 30 20 18 84 03 60 mov\.ret\.dptk b3=r4,a70 <_start\+0xa70> + 97c: 40 70 08 07 mov\.ret\.dptk\.imp b3=r4,a70 <_start\+0xa70>;; + \.\.\. diff --git a/gas/testsuite/gas/ia64/opc-i.pl b/gas/testsuite/gas/ia64/opc-i.pl new file mode 100644 index 0000000..ad2f7e8 --- /dev/null +++ b/gas/testsuite/gas/ia64/opc-i.pl @@ -0,0 +1,186 @@ +$AT = '@'; +print <<END +.text + .type _start,${AT}function +_start: + + pmpyshr2 r4 = r5, r6, 0 + pmpyshr2.u r4 = r5, r6, 16 + + pmpy2.r r4 = r5, r6 + pmpy2.l r4 = r5, r6 + + mix1.r r4 = r5, r6 + mix2.r r4 = r5, r6 + mix4.r r4 = r5, r6 + mix1.l r4 = r5, r6 + mix2.l r4 = r5, r6 + mix4.l r4 = r5, r6 + + pack2.uss r4 = r5, r6 + pack2.sss r4 = r5, r6 + pack4.sss r4 = r5, r6 + + unpack1.h r4 = r5, r6 + unpack2.h r4 = r5, r6 + unpack4.h r4 = r5, r6 + unpack1.l r4 = r5, r6 + unpack2.l r4 = r5, r6 + unpack4.l r4 = r5, r6 + + pmin1.u r4 = r5, r6 + pmax1.u r4 = r5, r6 + + pmin2 r4 = r5, r6 + pmax2 r4 = r5, r6 + + psad1 r4 = r5, r6 + + mux1 r4 = r5, ${AT}rev + mux1 r4 = r5, ${AT}mix + mux1 r4 = r5, ${AT}shuf + mux1 r4 = r5, ${AT}alt + mux1 r4 = r5, ${AT}brcst + + mux2 r4 = r5, 0 + mux2 r4 = r5, 0xff + mux2 r4 = r5, 0xaa + + pshr2 r4 = r5, r6 + pshr2 r4 = r5, 0 + pshr2 r4 = r5, 8 + pshr2 r4 = r5, 31 + + pshr4 r4 = r5, r6 + pshr4 r4 = r5, 0 + pshr4 r4 = r5, 8 + pshr4 r4 = r5, 31 + + pshr2.u r4 = r5, r6 + pshr2.u r4 = r5, 0 + pshr2.u r4 = r5, 8 + pshr2.u r4 = r5, 31 + + pshr4.u r4 = r5, r6 + pshr4.u r4 = r5, 0 + pshr4.u r4 = r5, 8 + pshr4.u r4 = r5, 31 + + shr r4 = r5, r6 + shr.u r4 = r5, r6 + + pshl2 r4 = r5, r6 + pshl2 r4 = r5, 0 + pshl2 r4 = r5, 8 + pshl2 r4 = r5, 31 + + pshl4 r4 = r5, r6 + pshl4 r4 = r5, 0 + pshl4 r4 = r5, 8 + pshl4 r4 = r5, 31 + + shl r4 = r5, r6 + + popcnt r4 = r5 + + shrp r4 = r5, r6, 0 + shrp r4 = r5, r6, 12 + shrp r4 = r5, r6, 63 + + extr r4 = r5, 0, 16 + extr r4 = r5, 0, 63 + extr r4 = r5, 10, 40 + + extr.u r4 = r5, 0, 16 + extr.u r4 = r5, 0, 63 + extr.u r4 = r5, 10, 40 + + dep.z r4 = r5, 0, 16 + dep.z r4 = r5, 0, 63 + dep.z r4 = r5, 10, 40 + dep.z r4 = 0, 0, 16 + dep.z r4 = 127, 0, 63 + dep.z r4 = -128, 5, 50 + dep.z r4 = 0x55, 10, 40 + + dep r4 = 0, r5, 0, 16 + dep r4 = -1, r5, 0, 63 + dep r4 = r5, r6, 10, 7 + + movl r4 = 0 + movl r4 = 0xffffffffffffffff + movl r4 = 0x1234567890abcdef + + break.i 0 + break.i 0x1fffff + + nop.i 0 + nop.i 0x1fffff + + chk.s.i r4, _start + + mov r4 = b0 + mov b0 = r4 + + mov pr = r4, 0 + mov pr = r4, 0x1234 + mov pr = r4, 0x1ffff + + mov pr.rot = 0 +// ??? This was originally 0x3ffffff, but that generates an assembler warning +// that the testsuite infrastructure isn't set up to ignore. + mov pr.rot = 0x3ff0000 + mov pr.rot = -0x4000000 + + zxt1 r4 = r5 + zxt2 r4 = r5 + zxt4 r4 = r5 + + sxt1 r4 = r5 + sxt2 r4 = r5 + sxt4 r4 = r5 + + czx1.l r4 = r5 + czx2.l r4 = r5 + czx1.r r4 = r5 + czx2.r r4 = r5 + +END +; + +@ctype = ( "", ".unc", ".and", ".or", ".or.andcm", ".orcm", + ".andcm", ".and.orcm" ); + +$i = 0; +foreach $z ( ".z", ".nz" ) { + foreach $c (@ctype) { + print "\ttbit${z}${c} p2, p3 = r4, $i\n"; + ++$i; + } +} +print "\n"; + +foreach $z ( ".z", ".nz" ) { + foreach $c (@ctype) { + print "\ttnat${z}${c} p2, p3 = r4\n"; + } +} +print "\n"; + + +@mwh = ( "", ".sptk", ".dptk" ); +@ih = ( "", ".imp" ); + +$LAB = 1; + +foreach $b ("", ".ret") { + foreach $w (@mwh) { + foreach $i (@ih) { + print "\tmov${b}${w}${i} b3 = r4, .L${LAB}\n"; + } + print ".space 240\n"; + print ".L${LAB}:\n"; + ++$LAB; + } + print "\n"; +} diff --git a/gas/testsuite/gas/ia64/opc-i.s b/gas/testsuite/gas/ia64/opc-i.s new file mode 100644 index 0000000..8be5a57 --- /dev/null +++ b/gas/testsuite/gas/ia64/opc-i.s @@ -0,0 +1,383 @@ +.text + .type _start,@function +_start: + + pmpyshr2 r4 = r5, r6, 0 + pmpyshr2.u r4 = r5, r6, 16 + + pmpy2.r r4 = r5, r6 + pmpy2.l r4 = r5, r6 + + mix1.r r4 = r5, r6 + mix2.r r4 = r5, r6 + mix4.r r4 = r5, r6 + mix1.l r4 = r5, r6 + mix2.l r4 = r5, r6 + mix4.l r4 = r5, r6 + + pack2.uss r4 = r5, r6 + pack2.sss r4 = r5, r6 + pack4.sss r4 = r5, r6 + + unpack1.h r4 = r5, r6 + unpack2.h r4 = r5, r6 + unpack4.h r4 = r5, r6 + unpack1.l r4 = r5, r6 + unpack2.l r4 = r5, r6 + unpack4.l r4 = r5, r6 + + pmin1.u r4 = r5, r6 + pmax1.u r4 = r5, r6 + + pmin2 r4 = r5, r6 + pmax2 r4 = r5, r6 + + psad1 r4 = r5, r6 + + mux1 r4 = r5, @rev + mux1 r4 = r5, @mix + mux1 r4 = r5, @shuf + mux1 r4 = r5, @alt + mux1 r4 = r5, @brcst + + mux2 r4 = r5, 0 + mux2 r4 = r5, 0xff + mux2 r4 = r5, 0xaa + + pshr2 r4 = r5, r6 + pshr2 r4 = r5, 0 + pshr2 r4 = r5, 8 + pshr2 r4 = r5, 31 + + pshr4 r4 = r5, r6 + pshr4 r4 = r5, 0 + pshr4 r4 = r5, 8 + pshr4 r4 = r5, 31 + + pshr2.u r4 = r5, r6 + pshr2.u r4 = r5, 0 + pshr2.u r4 = r5, 8 + pshr2.u r4 = r5, 31 + + pshr4.u r4 = r5, r6 + pshr4.u r4 = r5, 0 + pshr4.u r4 = r5, 8 + pshr4.u r4 = r5, 31 + + shr r4 = r5, r6 + shr.u r4 = r5, r6 + + pshl2 r4 = r5, r6 + pshl2 r4 = r5, 0 + pshl2 r4 = r5, 8 + pshl2 r4 = r5, 31 + + pshl4 r4 = r5, r6 + pshl4 r4 = r5, 0 + pshl4 r4 = r5, 8 + pshl4 r4 = r5, 31 + + shl r4 = r5, r6 + + popcnt r4 = r5 + + shrp r4 = r5, r6, 0 + shrp r4 = r5, r6, 12 + shrp r4 = r5, r6, 63 + + extr r4 = r5, 0, 16 + extr r4 = r5, 0, 63 + extr r4 = r5, 10, 40 + + extr.u r4 = r5, 0, 16 + extr.u r4 = r5, 0, 63 + extr.u r4 = r5, 10, 40 + + dep.z r4 = r5, 0, 16 + dep.z r4 = r5, 0, 63 + dep.z r4 = r5, 10, 40 + dep.z r4 = 0, 0, 16 + dep.z r4 = 127, 0, 63 + dep.z r4 = -128, 5, 50 + dep.z r4 = 0x55, 10, 40 + + dep r4 = 0, r5, 0, 16 + dep r4 = -1, r5, 0, 63 + dep r4 = r5, r6, 10, 7 + + movl r4 = 0 + movl r4 = 0xffffffffffffffff + movl r4 = 0x1234567890abcdef + + break.i 0 + break.i 0x1fffff + + nop.i 0 + nop.i 0x1fffff + + chk.s.i r4, _start + + mov r4 = b0 + mov b0 = r4 + + mov pr = r4, 0 + mov pr = r4, 0x1234 + mov pr = r4, 0x1ffff + + mov pr.rot = 0 + mov pr.rot = 0x3ff0000 + mov pr.rot = -0x4000000 + + zxt1 r4 = r5 + zxt2 r4 = r5 + zxt4 r4 = r5 + + sxt1 r4 = r5 + sxt2 r4 = r5 + sxt4 r4 = r5 + + czx1.l r4 = r5 + czx2.l r4 = r5 + czx1.r r4 = r5 + czx2.r r4 = r5 + + tbit.z p2, p3 = r4, 0 + tbit.z.unc p2, p3 = r4, 1 + tbit.z.and p2, p3 = r4, 2 + tbit.z.or p2, p3 = r4, 3 + tbit.z.or.andcm p2, p3 = r4, 4 + tbit.z.orcm p2, p3 = r4, 5 + tbit.z.andcm p2, p3 = r4, 6 + tbit.z.and.orcm p2, p3 = r4, 7 + tbit.nz p2, p3 = r4, 8 + tbit.nz.unc p2, p3 = r4, 9 + tbit.nz.and p2, p3 = r4, 10 + tbit.nz.or p2, p3 = r4, 11 + tbit.nz.or.andcm p2, p3 = r4, 12 + tbit.nz.orcm p2, p3 = r4, 13 + tbit.nz.andcm p2, p3 = r4, 14 + tbit.nz.and.orcm p2, p3 = r4, 15 + + tnat.z p2, p3 = r4 + tnat.z.unc p2, p3 = r4 + tnat.z.and p2, p3 = r4 + tnat.z.or p2, p3 = r4 + tnat.z.or.andcm p2, p3 = r4 + tnat.z.orcm p2, p3 = r4 + tnat.z.andcm p2, p3 = r4 + tnat.z.and.orcm p2, p3 = r4 + tnat.nz p2, p3 = r4 + tnat.nz.unc p2, p3 = r4 + tnat.nz.and p2, p3 = r4 + tnat.nz.or p2, p3 = r4 + tnat.nz.or.andcm p2, p3 = r4 + tnat.nz.orcm p2, p3 = r4 + tnat.nz.andcm p2, p3 = r4 + tnat.nz.and.orcm p2, p3 = r4 + + mov.few.dc.dc b3 = r4, .L1 + mov.few.dc.dc.imp b3 = r4, .L1 + mov.few.dc.nt b3 = r4, .L1 + mov.few.dc.nt.imp b3 = r4, .L1 + mov.few.tk.dc b3 = r4, .L1 + mov.few.tk.dc.imp b3 = r4, .L1 + mov.few.tk.tk b3 = r4, .L1 + mov.few.tk.tk.imp b3 = r4, .L1 + mov.few.tk.nt b3 = r4, .L1 + mov.few.tk.nt.imp b3 = r4, .L1 + mov.few.nt.dc b3 = r4, .L1 + mov.few.nt.dc.imp b3 = r4, .L1 + mov.few.nt.tk b3 = r4, .L1 + mov.few.nt.tk.imp b3 = r4, .L1 + mov.few.nt.nt b3 = r4, .L1 + mov.few.nt.nt.imp b3 = r4, .L1 +.L1: + mov.many.dc.dc b3 = r4, .L2 + mov.many.dc.dc.imp b3 = r4, .L2 + mov.many.dc.nt b3 = r4, .L2 + mov.many.dc.nt.imp b3 = r4, .L2 + mov.many.tk.dc b3 = r4, .L2 + mov.many.tk.dc.imp b3 = r4, .L2 + mov.many.tk.tk b3 = r4, .L2 + mov.many.tk.tk.imp b3 = r4, .L2 + mov.many.tk.nt b3 = r4, .L2 + mov.many.tk.nt.imp b3 = r4, .L2 + mov.many.nt.dc b3 = r4, .L2 + mov.many.nt.dc.imp b3 = r4, .L2 + mov.many.nt.tk b3 = r4, .L2 + mov.many.nt.tk.imp b3 = r4, .L2 + mov.many.nt.nt b3 = r4, .L2 + mov.many.nt.nt.imp b3 = r4, .L2 +.L2: + mov.sptk.few.dc.dc b3 = r4, .L3 + mov.sptk.few.dc.dc.imp b3 = r4, .L3 + mov.sptk.few.dc.nt b3 = r4, .L3 + mov.sptk.few.dc.nt.imp b3 = r4, .L3 + mov.sptk.few.tk.dc b3 = r4, .L3 + mov.sptk.few.tk.dc.imp b3 = r4, .L3 + mov.sptk.few.tk.tk b3 = r4, .L3 + mov.sptk.few.tk.tk.imp b3 = r4, .L3 + mov.sptk.few.tk.nt b3 = r4, .L3 + mov.sptk.few.tk.nt.imp b3 = r4, .L3 + mov.sptk.few.nt.dc b3 = r4, .L3 + mov.sptk.few.nt.dc.imp b3 = r4, .L3 + mov.sptk.few.nt.tk b3 = r4, .L3 + mov.sptk.few.nt.tk.imp b3 = r4, .L3 + mov.sptk.few.nt.nt b3 = r4, .L3 + mov.sptk.few.nt.nt.imp b3 = r4, .L3 +.L3: + mov.sptk.many.dc.dc b3 = r4, .L4 + mov.sptk.many.dc.dc.imp b3 = r4, .L4 + mov.sptk.many.dc.nt b3 = r4, .L4 + mov.sptk.many.dc.nt.imp b3 = r4, .L4 + mov.sptk.many.tk.dc b3 = r4, .L4 + mov.sptk.many.tk.dc.imp b3 = r4, .L4 + mov.sptk.many.tk.tk b3 = r4, .L4 + mov.sptk.many.tk.tk.imp b3 = r4, .L4 + mov.sptk.many.tk.nt b3 = r4, .L4 + mov.sptk.many.tk.nt.imp b3 = r4, .L4 + mov.sptk.many.nt.dc b3 = r4, .L4 + mov.sptk.many.nt.dc.imp b3 = r4, .L4 + mov.sptk.many.nt.tk b3 = r4, .L4 + mov.sptk.many.nt.tk.imp b3 = r4, .L4 + mov.sptk.many.nt.nt b3 = r4, .L4 + mov.sptk.many.nt.nt.imp b3 = r4, .L4 +.L4: + mov.dptk.few.dc.dc b3 = r4, .L5 + mov.dptk.few.dc.dc.imp b3 = r4, .L5 + mov.dptk.few.dc.nt b3 = r4, .L5 + mov.dptk.few.dc.nt.imp b3 = r4, .L5 + mov.dptk.few.tk.dc b3 = r4, .L5 + mov.dptk.few.tk.dc.imp b3 = r4, .L5 + mov.dptk.few.tk.tk b3 = r4, .L5 + mov.dptk.few.tk.tk.imp b3 = r4, .L5 + mov.dptk.few.tk.nt b3 = r4, .L5 + mov.dptk.few.tk.nt.imp b3 = r4, .L5 + mov.dptk.few.nt.dc b3 = r4, .L5 + mov.dptk.few.nt.dc.imp b3 = r4, .L5 + mov.dptk.few.nt.tk b3 = r4, .L5 + mov.dptk.few.nt.tk.imp b3 = r4, .L5 + mov.dptk.few.nt.nt b3 = r4, .L5 + mov.dptk.few.nt.nt.imp b3 = r4, .L5 +.L5: + mov.dptk.many.dc.dc b3 = r4, .L6 + mov.dptk.many.dc.dc.imp b3 = r4, .L6 + mov.dptk.many.dc.nt b3 = r4, .L6 + mov.dptk.many.dc.nt.imp b3 = r4, .L6 + mov.dptk.many.tk.dc b3 = r4, .L6 + mov.dptk.many.tk.dc.imp b3 = r4, .L6 + mov.dptk.many.tk.tk b3 = r4, .L6 + mov.dptk.many.tk.tk.imp b3 = r4, .L6 + mov.dptk.many.tk.nt b3 = r4, .L6 + mov.dptk.many.tk.nt.imp b3 = r4, .L6 + mov.dptk.many.nt.dc b3 = r4, .L6 + mov.dptk.many.nt.dc.imp b3 = r4, .L6 + mov.dptk.many.nt.tk b3 = r4, .L6 + mov.dptk.many.nt.tk.imp b3 = r4, .L6 + mov.dptk.many.nt.nt b3 = r4, .L6 + mov.dptk.many.nt.nt.imp b3 = r4, .L6 +.L6: + + mov.ret.few.dc.dc b3 = r4, .L7 + mov.ret.few.dc.dc.imp b3 = r4, .L7 + mov.ret.few.dc.nt b3 = r4, .L7 + mov.ret.few.dc.nt.imp b3 = r4, .L7 + mov.ret.few.tk.dc b3 = r4, .L7 + mov.ret.few.tk.dc.imp b3 = r4, .L7 + mov.ret.few.tk.tk b3 = r4, .L7 + mov.ret.few.tk.tk.imp b3 = r4, .L7 + mov.ret.few.tk.nt b3 = r4, .L7 + mov.ret.few.tk.nt.imp b3 = r4, .L7 + mov.ret.few.nt.dc b3 = r4, .L7 + mov.ret.few.nt.dc.imp b3 = r4, .L7 + mov.ret.few.nt.tk b3 = r4, .L7 + mov.ret.few.nt.tk.imp b3 = r4, .L7 + mov.ret.few.nt.nt b3 = r4, .L7 + mov.ret.few.nt.nt.imp b3 = r4, .L7 +.L7: + mov.ret.many.dc.dc b3 = r4, .L8 + mov.ret.many.dc.dc.imp b3 = r4, .L8 + mov.ret.many.dc.nt b3 = r4, .L8 + mov.ret.many.dc.nt.imp b3 = r4, .L8 + mov.ret.many.tk.dc b3 = r4, .L8 + mov.ret.many.tk.dc.imp b3 = r4, .L8 + mov.ret.many.tk.tk b3 = r4, .L8 + mov.ret.many.tk.tk.imp b3 = r4, .L8 + mov.ret.many.tk.nt b3 = r4, .L8 + mov.ret.many.tk.nt.imp b3 = r4, .L8 + mov.ret.many.nt.dc b3 = r4, .L8 + mov.ret.many.nt.dc.imp b3 = r4, .L8 + mov.ret.many.nt.tk b3 = r4, .L8 + mov.ret.many.nt.tk.imp b3 = r4, .L8 + mov.ret.many.nt.nt b3 = r4, .L8 + mov.ret.many.nt.nt.imp b3 = r4, .L8 +.L8: + mov.ret.sptk.few.dc.dc b3 = r4, .L9 + mov.ret.sptk.few.dc.dc.imp b3 = r4, .L9 + mov.ret.sptk.few.dc.nt b3 = r4, .L9 + mov.ret.sptk.few.dc.nt.imp b3 = r4, .L9 + mov.ret.sptk.few.tk.dc b3 = r4, .L9 + mov.ret.sptk.few.tk.dc.imp b3 = r4, .L9 + mov.ret.sptk.few.tk.tk b3 = r4, .L9 + mov.ret.sptk.few.tk.tk.imp b3 = r4, .L9 + mov.ret.sptk.few.tk.nt b3 = r4, .L9 + mov.ret.sptk.few.tk.nt.imp b3 = r4, .L9 + mov.ret.sptk.few.nt.dc b3 = r4, .L9 + mov.ret.sptk.few.nt.dc.imp b3 = r4, .L9 + mov.ret.sptk.few.nt.tk b3 = r4, .L9 + mov.ret.sptk.few.nt.tk.imp b3 = r4, .L9 + mov.ret.sptk.few.nt.nt b3 = r4, .L9 + mov.ret.sptk.few.nt.nt.imp b3 = r4, .L9 +.L9: + mov.ret.sptk.many.dc.dc b3 = r4, .L10 + mov.ret.sptk.many.dc.dc.imp b3 = r4, .L10 + mov.ret.sptk.many.dc.nt b3 = r4, .L10 + mov.ret.sptk.many.dc.nt.imp b3 = r4, .L10 + mov.ret.sptk.many.tk.dc b3 = r4, .L10 + mov.ret.sptk.many.tk.dc.imp b3 = r4, .L10 + mov.ret.sptk.many.tk.tk b3 = r4, .L10 + mov.ret.sptk.many.tk.tk.imp b3 = r4, .L10 + mov.ret.sptk.many.tk.nt b3 = r4, .L10 + mov.ret.sptk.many.tk.nt.imp b3 = r4, .L10 + mov.ret.sptk.many.nt.dc b3 = r4, .L10 + mov.ret.sptk.many.nt.dc.imp b3 = r4, .L10 + mov.ret.sptk.many.nt.tk b3 = r4, .L10 + mov.ret.sptk.many.nt.tk.imp b3 = r4, .L10 + mov.ret.sptk.many.nt.nt b3 = r4, .L10 + mov.ret.sptk.many.nt.nt.imp b3 = r4, .L10 +.L10: + mov.ret.dptk.few.dc.dc b3 = r4, .L11 + mov.ret.dptk.few.dc.dc.imp b3 = r4, .L11 + mov.ret.dptk.few.dc.nt b3 = r4, .L11 + mov.ret.dptk.few.dc.nt.imp b3 = r4, .L11 + mov.ret.dptk.few.tk.dc b3 = r4, .L11 + mov.ret.dptk.few.tk.dc.imp b3 = r4, .L11 + mov.ret.dptk.few.tk.tk b3 = r4, .L11 + mov.ret.dptk.few.tk.tk.imp b3 = r4, .L11 + mov.ret.dptk.few.tk.nt b3 = r4, .L11 + mov.ret.dptk.few.tk.nt.imp b3 = r4, .L11 + mov.ret.dptk.few.nt.dc b3 = r4, .L11 + mov.ret.dptk.few.nt.dc.imp b3 = r4, .L11 + mov.ret.dptk.few.nt.tk b3 = r4, .L11 + mov.ret.dptk.few.nt.tk.imp b3 = r4, .L11 + mov.ret.dptk.few.nt.nt b3 = r4, .L11 + mov.ret.dptk.few.nt.nt.imp b3 = r4, .L11 +.L11: + mov.ret.dptk.many.dc.dc b3 = r4, .L12 + mov.ret.dptk.many.dc.dc.imp b3 = r4, .L12 + mov.ret.dptk.many.dc.nt b3 = r4, .L12 + mov.ret.dptk.many.dc.nt.imp b3 = r4, .L12 + mov.ret.dptk.many.tk.dc b3 = r4, .L12 + mov.ret.dptk.many.tk.dc.imp b3 = r4, .L12 + mov.ret.dptk.many.tk.tk b3 = r4, .L12 + mov.ret.dptk.many.tk.tk.imp b3 = r4, .L12 + mov.ret.dptk.many.tk.nt b3 = r4, .L12 + mov.ret.dptk.many.tk.nt.imp b3 = r4, .L12 + mov.ret.dptk.many.nt.dc b3 = r4, .L12 + mov.ret.dptk.many.nt.dc.imp b3 = r4, .L12 + mov.ret.dptk.many.nt.tk b3 = r4, .L12 + mov.ret.dptk.many.nt.tk.imp b3 = r4, .L12 + mov.ret.dptk.many.nt.nt b3 = r4, .L12 + mov.ret.dptk.many.nt.nt.imp b3 = r4, .L12 +.L12: + diff --git a/gas/testsuite/gas/ia64/opc-m.d b/gas/testsuite/gas/ia64/opc-m.d new file mode 100644 index 0000000..f38bab1 --- /dev/null +++ b/gas/testsuite/gas/ia64/opc-m.d @@ -0,0 +1,1328 @@ +# objdump: -d +# name: ia64 opc-m + +.*: +file format .* + +Disassembly of section \.text: + +0000000000000000 <_start>: + 0: 08 20 00 0a 00 10 \[MMI\] ld1 r4=\[r5\] + 6: 40 30 14 00 24 00 ld1 r4=\[r5\],r6 + c: 00 00 04 00 nop\.i 0x0 + 10: 08 20 00 0a 00 16 \[MMI\] ld1 r4=\[r5\],-256 + 16: 40 00 14 04 20 00 ld1\.nt1 r4=\[r5\] + 1c: 00 00 04 00 nop\.i 0x0 + 20: 08 20 18 0a 02 12 \[MMI\] ld1\.nt1 r4=\[r5\],r6 + 26: 40 68 14 04 2c 00 ld1\.nt1 r4=\[r5\],-243 + 2c: 00 00 04 00 nop\.i 0x0 + 30: 08 20 00 0a 06 10 \[MMI\] ld1\.nta r4=\[r5\] + 36: 40 30 14 0c 24 00 ld1\.nta r4=\[r5\],r6 + 3c: 00 00 04 00 nop\.i 0x0 + 40: 08 20 68 0a 06 16 \[MMI\] ld1\.nta r4=\[r5\],-230 + 46: 40 00 14 40 20 00 ld1\.s r4=\[r5\] + 4c: 00 00 04 00 nop\.i 0x0 + 50: 08 20 18 0a 20 12 \[MMI\] ld1\.s r4=\[r5\],r6 + 56: 40 38 15 40 2c 00 ld1\.s r4=\[r5\],-217 + 5c: 00 00 04 00 nop\.i 0x0 + 60: 08 20 00 0a 22 10 \[MMI\] ld1\.s\.nt1 r4=\[r5\] + 66: 40 30 14 44 24 00 ld1\.s\.nt1 r4=\[r5\],r6 + 6c: 00 00 04 00 nop\.i 0x0 + 70: 08 20 d0 0a 22 16 \[MMI\] ld1\.s\.nt1 r4=\[r5\],-204 + 76: 40 00 14 4c 20 00 ld1\.s\.nta r4=\[r5\] + 7c: 00 00 04 00 nop\.i 0x0 + 80: 08 20 18 0a 26 12 \[MMI\] ld1\.s\.nta r4=\[r5\],r6 + 86: 40 08 16 4c 2c 00 ld1\.s\.nta r4=\[r5\],-191 + 8c: 00 00 04 00 nop\.i 0x0 + 90: 08 20 00 0a 40 10 \[MMI\] ld1\.a r4=\[r5\] + 96: 40 30 14 80 24 00 ld1\.a r4=\[r5\],r6 + 9c: 00 00 04 00 nop\.i 0x0 + a0: 08 20 38 0b 40 16 \[MMI\] ld1\.a r4=\[r5\],-178 + a6: 40 00 14 84 20 00 ld1\.a\.nt1 r4=\[r5\] + ac: 00 00 04 00 nop\.i 0x0 + b0: 08 20 18 0a 42 12 \[MMI\] ld1\.a\.nt1 r4=\[r5\],r6 + b6: 40 d8 16 84 2c 00 ld1\.a\.nt1 r4=\[r5\],-165 + bc: 00 00 04 00 nop\.i 0x0 + c0: 08 20 00 0a 46 10 \[MMI\] ld1\.a\.nta r4=\[r5\] + c6: 40 30 14 8c 24 00 ld1\.a\.nta r4=\[r5\],r6 + cc: 00 00 04 00 nop\.i 0x0 + d0: 08 20 a0 0b 46 16 \[MMI\] ld1\.a\.nta r4=\[r5\],-152 + d6: 40 00 14 c0 20 00 ld1\.sa r4=\[r5\] + dc: 00 00 04 00 nop\.i 0x0 + e0: 08 20 18 0a 60 12 \[MMI\] ld1\.sa r4=\[r5\],r6 + e6: 40 a8 17 c0 2c 00 ld1\.sa r4=\[r5\],-139 + ec: 00 00 04 00 nop\.i 0x0 + f0: 08 20 00 0a 62 10 \[MMI\] ld1\.sa\.nt1 r4=\[r5\] + f6: 40 30 14 c4 24 00 ld1\.sa\.nt1 r4=\[r5\],r6 + fc: 00 00 04 00 nop\.i 0x0 + 100: 08 20 08 0a 63 16 \[MMI\] ld1\.sa\.nt1 r4=\[r5\],-126 + 106: 40 00 14 cc 20 00 ld1\.sa\.nta r4=\[r5\] + 10c: 00 00 04 00 nop\.i 0x0 + 110: 08 20 18 0a 66 12 \[MMI\] ld1\.sa\.nta r4=\[r5\],r6 + 116: 40 78 14 ce 2c 00 ld1\.sa\.nta r4=\[r5\],-113 + 11c: 00 00 04 00 nop\.i 0x0 + 120: 08 20 00 0a 00 11 \[MMI\] ld1\.c\.clr r4=\[r5\] + 126: 40 30 14 00 26 00 ld1\.c\.clr r4=\[r5\],r6 + 12c: 00 00 04 00 nop\.i 0x0 + 130: 08 20 70 0a 01 17 \[MMI\] ld1\.c\.clr r4=\[r5\],-100 + 136: 40 00 14 04 22 00 ld1\.c\.clr\.nt1 r4=\[r5\] + 13c: 00 00 04 00 nop\.i 0x0 + 140: 08 20 18 0a 02 13 \[MMI\] ld1\.c\.clr\.nt1 r4=\[r5\],r6 + 146: 40 48 15 06 2e 00 ld1\.c\.clr\.nt1 r4=\[r5\],-87 + 14c: 00 00 04 00 nop\.i 0x0 + 150: 08 20 00 0a 06 11 \[MMI\] ld1\.c\.clr\.nta r4=\[r5\] + 156: 40 30 14 0c 26 00 ld1\.c\.clr\.nta r4=\[r5\],r6 + 15c: 00 00 04 00 nop\.i 0x0 + 160: 08 20 d8 0a 07 17 \[MMI\] ld1\.c\.clr\.nta r4=\[r5\],-74 + 166: 40 00 14 40 22 00 ld1\.c\.nc r4=\[r5\] + 16c: 00 00 04 00 nop\.i 0x0 + 170: 08 20 18 0a 20 13 \[MMI\] ld1\.c\.nc r4=\[r5\],r6 + 176: 40 18 16 42 2e 00 ld1\.c\.nc r4=\[r5\],-61 + 17c: 00 00 04 00 nop\.i 0x0 + 180: 08 20 00 0a 22 11 \[MMI\] ld1\.c\.nc\.nt1 r4=\[r5\] + 186: 40 30 14 44 26 00 ld1\.c\.nc\.nt1 r4=\[r5\],r6 + 18c: 00 00 04 00 nop\.i 0x0 + 190: 08 20 40 0b 23 17 \[MMI\] ld1\.c\.nc\.nt1 r4=\[r5\],-48 + 196: 40 00 14 4c 22 00 ld1\.c\.nc\.nta r4=\[r5\] + 19c: 00 00 04 00 nop\.i 0x0 + 1a0: 08 20 18 0a 26 13 \[MMI\] ld1\.c\.nc\.nta r4=\[r5\],r6 + 1a6: 40 e8 16 4e 2e 00 ld1\.c\.nc\.nta r4=\[r5\],-35 + 1ac: 00 00 04 00 nop\.i 0x0 + 1b0: 08 20 00 0a 80 10 \[MMI\] ld1\.bias r4=\[r5\] + 1b6: 40 30 14 00 25 00 ld1\.bias r4=\[r5\],r6 + 1bc: 00 00 04 00 nop\.i 0x0 + 1c0: 08 20 a8 0b 81 16 \[MMI\] ld1\.bias r4=\[r5\],-22 + 1c6: 40 00 14 04 21 00 ld1\.bias\.nt1 r4=\[r5\] + 1cc: 00 00 04 00 nop\.i 0x0 + 1d0: 08 20 18 0a 82 12 \[MMI\] ld1\.bias\.nt1 r4=\[r5\],r6 + 1d6: 40 b8 17 06 2d 00 ld1\.bias\.nt1 r4=\[r5\],-9 + 1dc: 00 00 04 00 nop\.i 0x0 + 1e0: 08 20 00 0a 86 10 \[MMI\] ld1\.bias\.nta r4=\[r5\] + 1e6: 40 30 14 0c 25 00 ld1\.bias\.nta r4=\[r5\],r6 + 1ec: 00 00 04 00 nop\.i 0x0 + 1f0: 08 20 10 0a 86 14 \[MMI\] ld1\.bias\.nta r4=\[r5\],4 + 1f6: 40 00 14 40 21 00 ld1\.acq r4=\[r5\] + 1fc: 00 00 04 00 nop\.i 0x0 + 200: 08 20 18 0a a0 12 \[MMI\] ld1\.acq r4=\[r5\],r6 + 206: 40 88 14 40 29 00 ld1\.acq r4=\[r5\],17 + 20c: 00 00 04 00 nop\.i 0x0 + 210: 08 20 00 0a a2 10 \[MMI\] ld1\.acq\.nt1 r4=\[r5\] + 216: 40 30 14 44 25 00 ld1\.acq\.nt1 r4=\[r5\],r6 + 21c: 00 00 04 00 nop\.i 0x0 + 220: 08 20 78 0a a2 14 \[MMI\] ld1\.acq\.nt1 r4=\[r5\],30 + 226: 40 00 14 4c 21 00 ld1\.acq\.nta r4=\[r5\] + 22c: 00 00 04 00 nop\.i 0x0 + 230: 08 20 18 0a a6 12 \[MMI\] ld1\.acq\.nta r4=\[r5\],r6 + 236: 40 58 15 4c 29 00 ld1\.acq\.nta r4=\[r5\],43 + 23c: 00 00 04 00 nop\.i 0x0 + 240: 08 20 00 0a 40 11 \[MMI\] ld1\.c\.clr\.acq r4=\[r5\] + 246: 40 30 14 80 26 00 ld1\.c\.clr\.acq r4=\[r5\],r6 + 24c: 00 00 04 00 nop\.i 0x0 + 250: 08 20 e0 0a 40 15 \[MMI\] ld1\.c\.clr\.acq r4=\[r5\],56 + 256: 40 00 14 84 22 00 ld1\.c\.clr\.acq\.nt1 r4=\[r5\] + 25c: 00 00 04 00 nop\.i 0x0 + 260: 08 20 18 0a 42 13 \[MMI\] ld1\.c\.clr\.acq\.nt1 r4=\[r5\],r6 + 266: 40 28 16 84 2a 00 ld1\.c\.clr\.acq\.nt1 r4=\[r5\],69 + 26c: 00 00 04 00 nop\.i 0x0 + 270: 08 20 00 0a 46 11 \[MMI\] ld1\.c\.clr\.acq\.nta r4=\[r5\] + 276: 40 30 14 8c 26 00 ld1\.c\.clr\.acq\.nta r4=\[r5\],r6 + 27c: 00 00 04 00 nop\.i 0x0 + 280: 08 20 48 0b 46 15 \[MMI\] ld1\.c\.clr\.acq\.nta r4=\[r5\],82 + 286: 40 00 14 10 20 00 ld2 r4=\[r5\] + 28c: 00 00 04 00 nop\.i 0x0 + 290: 08 20 18 0a 08 12 \[MMI\] ld2 r4=\[r5\],r6 + 296: 40 f8 16 10 28 00 ld2 r4=\[r5\],95 + 29c: 00 00 04 00 nop\.i 0x0 + 2a0: 08 20 00 0a 0a 10 \[MMI\] ld2\.nt1 r4=\[r5\] + 2a6: 40 30 14 14 24 00 ld2\.nt1 r4=\[r5\],r6 + 2ac: 00 00 04 00 nop\.i 0x0 + 2b0: 08 20 b0 0b 0a 14 \[MMI\] ld2\.nt1 r4=\[r5\],108 + 2b6: 40 00 14 1c 20 00 ld2\.nta r4=\[r5\] + 2bc: 00 00 04 00 nop\.i 0x0 + 2c0: 08 20 18 0a 0e 12 \[MMI\] ld2\.nta r4=\[r5\],r6 + 2c6: 40 c8 17 1c 28 00 ld2\.nta r4=\[r5\],121 + 2cc: 00 00 04 00 nop\.i 0x0 + 2d0: 08 20 00 0a 28 10 \[MMI\] ld2\.s r4=\[r5\] + 2d6: 40 30 14 50 24 00 ld2\.s r4=\[r5\],r6 + 2dc: 00 00 04 00 nop\.i 0x0 + 2e0: 08 20 18 0a 29 14 \[MMI\] ld2\.s r4=\[r5\],134 + 2e6: 40 00 14 54 20 00 ld2\.s\.nt1 r4=\[r5\] + 2ec: 00 00 04 00 nop\.i 0x0 + 2f0: 08 20 18 0a 2a 12 \[MMI\] ld2\.s\.nt1 r4=\[r5\],r6 + 2f6: 40 98 14 56 28 00 ld2\.s\.nt1 r4=\[r5\],147 + 2fc: 00 00 04 00 nop\.i 0x0 + 300: 08 20 00 0a 2e 10 \[MMI\] ld2\.s\.nta r4=\[r5\] + 306: 40 30 14 5c 24 00 ld2\.s\.nta r4=\[r5\],r6 + 30c: 00 00 04 00 nop\.i 0x0 + 310: 08 20 80 0a 2f 14 \[MMI\] ld2\.s\.nta r4=\[r5\],160 + 316: 40 00 14 90 20 00 ld2\.a r4=\[r5\] + 31c: 00 00 04 00 nop\.i 0x0 + 320: 08 20 18 0a 48 12 \[MMI\] ld2\.a r4=\[r5\],r6 + 326: 40 68 15 92 28 00 ld2\.a r4=\[r5\],173 + 32c: 00 00 04 00 nop\.i 0x0 + 330: 08 20 00 0a 4a 10 \[MMI\] ld2\.a\.nt1 r4=\[r5\] + 336: 40 30 14 94 24 00 ld2\.a\.nt1 r4=\[r5\],r6 + 33c: 00 00 04 00 nop\.i 0x0 + 340: 08 20 e8 0a 4b 14 \[MMI\] ld2\.a\.nt1 r4=\[r5\],186 + 346: 40 00 14 9c 20 00 ld2\.a\.nta r4=\[r5\] + 34c: 00 00 04 00 nop\.i 0x0 + 350: 08 20 18 0a 4e 12 \[MMI\] ld2\.a\.nta r4=\[r5\],r6 + 356: 40 38 16 9e 28 00 ld2\.a\.nta r4=\[r5\],199 + 35c: 00 00 04 00 nop\.i 0x0 + 360: 08 20 00 0a 68 10 \[MMI\] ld2\.sa r4=\[r5\] + 366: 40 30 14 d0 24 00 ld2\.sa r4=\[r5\],r6 + 36c: 00 00 04 00 nop\.i 0x0 + 370: 08 20 50 0b 69 14 \[MMI\] ld2\.sa r4=\[r5\],212 + 376: 40 00 14 d4 20 00 ld2\.sa\.nt1 r4=\[r5\] + 37c: 00 00 04 00 nop\.i 0x0 + 380: 08 20 18 0a 6a 12 \[MMI\] ld2\.sa\.nt1 r4=\[r5\],r6 + 386: 40 08 17 d6 28 00 ld2\.sa\.nt1 r4=\[r5\],225 + 38c: 00 00 04 00 nop\.i 0x0 + 390: 08 20 00 0a 6e 10 \[MMI\] ld2\.sa\.nta r4=\[r5\] + 396: 40 30 14 dc 24 00 ld2\.sa\.nta r4=\[r5\],r6 + 39c: 00 00 04 00 nop\.i 0x0 + 3a0: 08 20 b8 0b 6f 14 \[MMI\] ld2\.sa\.nta r4=\[r5\],238 + 3a6: 40 00 14 10 22 00 ld2\.c\.clr r4=\[r5\] + 3ac: 00 00 04 00 nop\.i 0x0 + 3b0: 08 20 18 0a 08 13 \[MMI\] ld2\.c\.clr r4=\[r5\],r6 + 3b6: 40 d8 17 12 2a 00 ld2\.c\.clr r4=\[r5\],251 + 3bc: 00 00 04 00 nop\.i 0x0 + 3c0: 08 20 00 0a 0a 11 \[MMI\] ld2\.c\.clr\.nt1 r4=\[r5\] + 3c6: 40 30 14 14 26 00 ld2\.c\.clr\.nt1 r4=\[r5\],r6 + 3cc: 00 00 04 00 nop\.i 0x0 + 3d0: 08 20 20 0a 0a 17 \[MMI\] ld2\.c\.clr\.nt1 r4=\[r5\],-248 + 3d6: 40 00 14 1c 22 00 ld2\.c\.clr\.nta r4=\[r5\] + 3dc: 00 00 04 00 nop\.i 0x0 + 3e0: 08 20 18 0a 0e 13 \[MMI\] ld2\.c\.clr\.nta r4=\[r5\],r6 + 3e6: 40 a8 14 1c 2e 00 ld2\.c\.clr\.nta r4=\[r5\],-235 + 3ec: 00 00 04 00 nop\.i 0x0 + 3f0: 08 20 00 0a 28 11 \[MMI\] ld2\.c\.nc r4=\[r5\] + 3f6: 40 30 14 50 26 00 ld2\.c\.nc r4=\[r5\],r6 + 3fc: 00 00 04 00 nop\.i 0x0 + 400: 08 20 88 0a 28 17 \[MMI\] ld2\.c\.nc r4=\[r5\],-222 + 406: 40 00 14 54 22 00 ld2\.c\.nc\.nt1 r4=\[r5\] + 40c: 00 00 04 00 nop\.i 0x0 + 410: 08 20 18 0a 2a 13 \[MMI\] ld2\.c\.nc\.nt1 r4=\[r5\],r6 + 416: 40 78 15 54 2e 00 ld2\.c\.nc\.nt1 r4=\[r5\],-209 + 41c: 00 00 04 00 nop\.i 0x0 + 420: 08 20 00 0a 2e 11 \[MMI\] ld2\.c\.nc\.nta r4=\[r5\] + 426: 40 30 14 5c 26 00 ld2\.c\.nc\.nta r4=\[r5\],r6 + 42c: 00 00 04 00 nop\.i 0x0 + 430: 08 20 f0 0a 2e 17 \[MMI\] ld2\.c\.nc\.nta r4=\[r5\],-196 + 436: 40 00 14 10 21 00 ld2\.bias r4=\[r5\] + 43c: 00 00 04 00 nop\.i 0x0 + 440: 08 20 18 0a 88 12 \[MMI\] ld2\.bias r4=\[r5\],r6 + 446: 40 48 16 10 2d 00 ld2\.bias r4=\[r5\],-183 + 44c: 00 00 04 00 nop\.i 0x0 + 450: 08 20 00 0a 8a 10 \[MMI\] ld2\.bias\.nt1 r4=\[r5\] + 456: 40 30 14 14 25 00 ld2\.bias\.nt1 r4=\[r5\],r6 + 45c: 00 00 04 00 nop\.i 0x0 + 460: 08 20 58 0b 8a 16 \[MMI\] ld2\.bias\.nt1 r4=\[r5\],-170 + 466: 40 00 14 1c 21 00 ld2\.bias\.nta r4=\[r5\] + 46c: 00 00 04 00 nop\.i 0x0 + 470: 08 20 18 0a 8e 12 \[MMI\] ld2\.bias\.nta r4=\[r5\],r6 + 476: 40 18 17 1c 2d 00 ld2\.bias\.nta r4=\[r5\],-157 + 47c: 00 00 04 00 nop\.i 0x0 + 480: 08 20 00 0a a8 10 \[MMI\] ld2\.acq r4=\[r5\] + 486: 40 30 14 50 25 00 ld2\.acq r4=\[r5\],r6 + 48c: 00 00 04 00 nop\.i 0x0 + 490: 08 20 c0 0b a8 16 \[MMI\] ld2\.acq r4=\[r5\],-144 + 496: 40 00 14 54 21 00 ld2\.acq\.nt1 r4=\[r5\] + 49c: 00 00 04 00 nop\.i 0x0 + 4a0: 08 20 18 0a aa 12 \[MMI\] ld2\.acq\.nt1 r4=\[r5\],r6 + 4a6: 40 e8 17 54 2d 00 ld2\.acq\.nt1 r4=\[r5\],-131 + 4ac: 00 00 04 00 nop\.i 0x0 + 4b0: 08 20 00 0a ae 10 \[MMI\] ld2\.acq\.nta r4=\[r5\] + 4b6: 40 30 14 5c 25 00 ld2\.acq\.nta r4=\[r5\],r6 + 4bc: 00 00 04 00 nop\.i 0x0 + 4c0: 08 20 28 0a af 16 \[MMI\] ld2\.acq\.nta r4=\[r5\],-118 + 4c6: 40 00 14 90 22 00 ld2\.c\.clr\.acq r4=\[r5\] + 4cc: 00 00 04 00 nop\.i 0x0 + 4d0: 08 20 18 0a 48 13 \[MMI\] ld2\.c\.clr\.acq r4=\[r5\],r6 + 4d6: 40 b8 14 92 2e 00 ld2\.c\.clr\.acq r4=\[r5\],-105 + 4dc: 00 00 04 00 nop\.i 0x0 + 4e0: 08 20 00 0a 4a 11 \[MMI\] ld2\.c\.clr\.acq\.nt1 r4=\[r5\] + 4e6: 40 30 14 94 26 00 ld2\.c\.clr\.acq\.nt1 r4=\[r5\],r6 + 4ec: 00 00 04 00 nop\.i 0x0 + 4f0: 08 20 90 0a 4b 17 \[MMI\] ld2\.c\.clr\.acq\.nt1 r4=\[r5\],-92 + 4f6: 40 00 14 9c 22 00 ld2\.c\.clr\.acq\.nta r4=\[r5\] + 4fc: 00 00 04 00 nop\.i 0x0 + 500: 08 20 18 0a 4e 13 \[MMI\] ld2\.c\.clr\.acq\.nta r4=\[r5\],r6 + 506: 40 88 15 9e 2e 00 ld2\.c\.clr\.acq\.nta r4=\[r5\],-79 + 50c: 00 00 04 00 nop\.i 0x0 + 510: 08 20 00 0a 10 10 \[MMI\] ld4 r4=\[r5\] + 516: 40 30 14 20 24 00 ld4 r4=\[r5\],r6 + 51c: 00 00 04 00 nop\.i 0x0 + 520: 08 20 f8 0a 11 16 \[MMI\] ld4 r4=\[r5\],-66 + 526: 40 00 14 24 20 00 ld4\.nt1 r4=\[r5\] + 52c: 00 00 04 00 nop\.i 0x0 + 530: 08 20 18 0a 12 12 \[MMI\] ld4\.nt1 r4=\[r5\],r6 + 536: 40 58 16 26 2c 00 ld4\.nt1 r4=\[r5\],-53 + 53c: 00 00 04 00 nop\.i 0x0 + 540: 08 20 00 0a 16 10 \[MMI\] ld4\.nta r4=\[r5\] + 546: 40 30 14 2c 24 00 ld4\.nta r4=\[r5\],r6 + 54c: 00 00 04 00 nop\.i 0x0 + 550: 08 20 60 0b 17 16 \[MMI\] ld4\.nta r4=\[r5\],-40 + 556: 40 00 14 60 20 00 ld4\.s r4=\[r5\] + 55c: 00 00 04 00 nop\.i 0x0 + 560: 08 20 18 0a 30 12 \[MMI\] ld4\.s r4=\[r5\],r6 + 566: 40 28 17 62 2c 00 ld4\.s r4=\[r5\],-27 + 56c: 00 00 04 00 nop\.i 0x0 + 570: 08 20 00 0a 32 10 \[MMI\] ld4\.s\.nt1 r4=\[r5\] + 576: 40 30 14 64 24 00 ld4\.s\.nt1 r4=\[r5\],r6 + 57c: 00 00 04 00 nop\.i 0x0 + 580: 08 20 c8 0b 33 16 \[MMI\] ld4\.s\.nt1 r4=\[r5\],-14 + 586: 40 00 14 6c 20 00 ld4\.s\.nta r4=\[r5\] + 58c: 00 00 04 00 nop\.i 0x0 + 590: 08 20 18 0a 36 12 \[MMI\] ld4\.s\.nta r4=\[r5\],r6 + 596: 40 f8 17 6e 2c 00 ld4\.s\.nta r4=\[r5\],-1 + 59c: 00 00 04 00 nop\.i 0x0 + 5a0: 08 20 00 0a 50 10 \[MMI\] ld4\.a r4=\[r5\] + 5a6: 40 30 14 a0 24 00 ld4\.a r4=\[r5\],r6 + 5ac: 00 00 04 00 nop\.i 0x0 + 5b0: 08 20 30 0a 50 14 \[MMI\] ld4\.a r4=\[r5\],12 + 5b6: 40 00 14 a4 20 00 ld4\.a\.nt1 r4=\[r5\] + 5bc: 00 00 04 00 nop\.i 0x0 + 5c0: 08 20 18 0a 52 12 \[MMI\] ld4\.a\.nt1 r4=\[r5\],r6 + 5c6: 40 c8 14 a4 28 00 ld4\.a\.nt1 r4=\[r5\],25 + 5cc: 00 00 04 00 nop\.i 0x0 + 5d0: 08 20 00 0a 56 10 \[MMI\] ld4\.a\.nta r4=\[r5\] + 5d6: 40 30 14 ac 24 00 ld4\.a\.nta r4=\[r5\],r6 + 5dc: 00 00 04 00 nop\.i 0x0 + 5e0: 08 20 98 0a 56 14 \[MMI\] ld4\.a\.nta r4=\[r5\],38 + 5e6: 40 00 14 e0 20 00 ld4\.sa r4=\[r5\] + 5ec: 00 00 04 00 nop\.i 0x0 + 5f0: 08 20 18 0a 70 12 \[MMI\] ld4\.sa r4=\[r5\],r6 + 5f6: 40 98 15 e0 28 00 ld4\.sa r4=\[r5\],51 + 5fc: 00 00 04 00 nop\.i 0x0 + 600: 08 20 00 0a 72 10 \[MMI\] ld4\.sa\.nt1 r4=\[r5\] + 606: 40 30 14 e4 24 00 ld4\.sa\.nt1 r4=\[r5\],r6 + 60c: 00 00 04 00 nop\.i 0x0 + 610: 08 20 00 0b 72 14 \[MMI\] ld4\.sa\.nt1 r4=\[r5\],64 + 616: 40 00 14 ec 20 00 ld4\.sa\.nta r4=\[r5\] + 61c: 00 00 04 00 nop\.i 0x0 + 620: 08 20 18 0a 76 12 \[MMI\] ld4\.sa\.nta r4=\[r5\],r6 + 626: 40 68 16 ec 28 00 ld4\.sa\.nta r4=\[r5\],77 + 62c: 00 00 04 00 nop\.i 0x0 + 630: 08 20 00 0a 10 11 \[MMI\] ld4\.c\.clr r4=\[r5\] + 636: 40 30 14 20 26 00 ld4\.c\.clr r4=\[r5\],r6 + 63c: 00 00 04 00 nop\.i 0x0 + 640: 08 20 68 0b 10 15 \[MMI\] ld4\.c\.clr r4=\[r5\],90 + 646: 40 00 14 24 22 00 ld4\.c\.clr\.nt1 r4=\[r5\] + 64c: 00 00 04 00 nop\.i 0x0 + 650: 08 20 18 0a 12 13 \[MMI\] ld4\.c\.clr\.nt1 r4=\[r5\],r6 + 656: 40 38 17 24 2a 00 ld4\.c\.clr\.nt1 r4=\[r5\],103 + 65c: 00 00 04 00 nop\.i 0x0 + 660: 08 20 00 0a 16 11 \[MMI\] ld4\.c\.clr\.nta r4=\[r5\] + 666: 40 30 14 2c 26 00 ld4\.c\.clr\.nta r4=\[r5\],r6 + 66c: 00 00 04 00 nop\.i 0x0 + 670: 08 20 d0 0b 16 15 \[MMI\] ld4\.c\.clr\.nta r4=\[r5\],116 + 676: 40 00 14 60 22 00 ld4\.c\.nc r4=\[r5\] + 67c: 00 00 04 00 nop\.i 0x0 + 680: 08 20 18 0a 30 13 \[MMI\] ld4\.c\.nc r4=\[r5\],r6 + 686: 40 08 14 62 2a 00 ld4\.c\.nc r4=\[r5\],129 + 68c: 00 00 04 00 nop\.i 0x0 + 690: 08 20 00 0a 32 11 \[MMI\] ld4\.c\.nc\.nt1 r4=\[r5\] + 696: 40 30 14 64 26 00 ld4\.c\.nc\.nt1 r4=\[r5\],r6 + 69c: 00 00 04 00 nop\.i 0x0 + 6a0: 08 20 38 0a 33 15 \[MMI\] ld4\.c\.nc\.nt1 r4=\[r5\],142 + 6a6: 40 00 14 6c 22 00 ld4\.c\.nc\.nta r4=\[r5\] + 6ac: 00 00 04 00 nop\.i 0x0 + 6b0: 08 20 18 0a 36 13 \[MMI\] ld4\.c\.nc\.nta r4=\[r5\],r6 + 6b6: 40 d8 14 6e 2a 00 ld4\.c\.nc\.nta r4=\[r5\],155 + 6bc: 00 00 04 00 nop\.i 0x0 + 6c0: 08 20 00 0a 90 10 \[MMI\] ld4\.bias r4=\[r5\] + 6c6: 40 30 14 20 25 00 ld4\.bias r4=\[r5\],r6 + 6cc: 00 00 04 00 nop\.i 0x0 + 6d0: 08 20 a0 0a 91 14 \[MMI\] ld4\.bias r4=\[r5\],168 + 6d6: 40 00 14 24 21 00 ld4\.bias\.nt1 r4=\[r5\] + 6dc: 00 00 04 00 nop\.i 0x0 + 6e0: 08 20 18 0a 92 12 \[MMI\] ld4\.bias\.nt1 r4=\[r5\],r6 + 6e6: 40 a8 15 26 29 00 ld4\.bias\.nt1 r4=\[r5\],181 + 6ec: 00 00 04 00 nop\.i 0x0 + 6f0: 08 20 00 0a 96 10 \[MMI\] ld4\.bias\.nta r4=\[r5\] + 6f6: 40 30 14 2c 25 00 ld4\.bias\.nta r4=\[r5\],r6 + 6fc: 00 00 04 00 nop\.i 0x0 + 700: 08 20 08 0b 97 14 \[MMI\] ld4\.bias\.nta r4=\[r5\],194 + 706: 40 00 14 60 21 00 ld4\.acq r4=\[r5\] + 70c: 00 00 04 00 nop\.i 0x0 + 710: 08 20 18 0a b0 12 \[MMI\] ld4\.acq r4=\[r5\],r6 + 716: 40 78 16 62 29 00 ld4\.acq r4=\[r5\],207 + 71c: 00 00 04 00 nop\.i 0x0 + 720: 08 20 00 0a b2 10 \[MMI\] ld4\.acq\.nt1 r4=\[r5\] + 726: 40 30 14 64 25 00 ld4\.acq\.nt1 r4=\[r5\],r6 + 72c: 00 00 04 00 nop\.i 0x0 + 730: 08 20 70 0b b3 14 \[MMI\] ld4\.acq\.nt1 r4=\[r5\],220 + 736: 40 00 14 6c 21 00 ld4\.acq\.nta r4=\[r5\] + 73c: 00 00 04 00 nop\.i 0x0 + 740: 08 20 18 0a b6 12 \[MMI\] ld4\.acq\.nta r4=\[r5\],r6 + 746: 40 48 17 6e 29 00 ld4\.acq\.nta r4=\[r5\],233 + 74c: 00 00 04 00 nop\.i 0x0 + 750: 08 20 00 0a 50 11 \[MMI\] ld4\.c\.clr\.acq r4=\[r5\] + 756: 40 30 14 a0 26 00 ld4\.c\.clr\.acq r4=\[r5\],r6 + 75c: 00 00 04 00 nop\.i 0x0 + 760: 08 20 d8 0b 51 15 \[MMI\] ld4\.c\.clr\.acq r4=\[r5\],246 + 766: 40 00 14 a4 22 00 ld4\.c\.clr\.acq\.nt1 r4=\[r5\] + 76c: 00 00 04 00 nop\.i 0x0 + 770: 08 20 18 0a 52 13 \[MMI\] ld4\.c\.clr\.acq\.nt1 r4=\[r5\],r6 + 776: 40 18 14 a4 2e 00 ld4\.c\.clr\.acq\.nt1 r4=\[r5\],-253 + 77c: 00 00 04 00 nop\.i 0x0 + 780: 08 20 00 0a 56 11 \[MMI\] ld4\.c\.clr\.acq\.nta r4=\[r5\] + 786: 40 30 14 ac 26 00 ld4\.c\.clr\.acq\.nta r4=\[r5\],r6 + 78c: 00 00 04 00 nop\.i 0x0 + 790: 08 20 40 0a 56 17 \[MMI\] ld4\.c\.clr\.acq\.nta r4=\[r5\],-240 + 796: 40 00 14 30 20 00 ld8 r4=\[r5\] + 79c: 00 00 04 00 nop\.i 0x0 + 7a0: 08 20 18 0a 18 12 \[MMI\] ld8 r4=\[r5\],r6 + 7a6: 40 e8 14 30 2c 00 ld8 r4=\[r5\],-227 + 7ac: 00 00 04 00 nop\.i 0x0 + 7b0: 08 20 00 0a 1a 10 \[MMI\] ld8\.nt1 r4=\[r5\] + 7b6: 40 30 14 34 24 00 ld8\.nt1 r4=\[r5\],r6 + 7bc: 00 00 04 00 nop\.i 0x0 + 7c0: 08 20 a8 0a 1a 16 \[MMI\] ld8\.nt1 r4=\[r5\],-214 + 7c6: 40 00 14 3c 20 00 ld8\.nta r4=\[r5\] + 7cc: 00 00 04 00 nop\.i 0x0 + 7d0: 08 20 18 0a 1e 12 \[MMI\] ld8\.nta r4=\[r5\],r6 + 7d6: 40 b8 15 3c 2c 00 ld8\.nta r4=\[r5\],-201 + 7dc: 00 00 04 00 nop\.i 0x0 + 7e0: 08 20 00 0a 38 10 \[MMI\] ld8\.s r4=\[r5\] + 7e6: 40 30 14 70 24 00 ld8\.s r4=\[r5\],r6 + 7ec: 00 00 04 00 nop\.i 0x0 + 7f0: 08 20 10 0b 38 16 \[MMI\] ld8\.s r4=\[r5\],-188 + 7f6: 40 00 14 74 20 00 ld8\.s\.nt1 r4=\[r5\] + 7fc: 00 00 04 00 nop\.i 0x0 + 800: 08 20 18 0a 3a 12 \[MMI\] ld8\.s\.nt1 r4=\[r5\],r6 + 806: 40 88 16 74 2c 00 ld8\.s\.nt1 r4=\[r5\],-175 + 80c: 00 00 04 00 nop\.i 0x0 + 810: 08 20 00 0a 3e 10 \[MMI\] ld8\.s\.nta r4=\[r5\] + 816: 40 30 14 7c 24 00 ld8\.s\.nta r4=\[r5\],r6 + 81c: 00 00 04 00 nop\.i 0x0 + 820: 08 20 78 0b 3e 16 \[MMI\] ld8\.s\.nta r4=\[r5\],-162 + 826: 40 00 14 b0 20 00 ld8\.a r4=\[r5\] + 82c: 00 00 04 00 nop\.i 0x0 + 830: 08 20 18 0a 58 12 \[MMI\] ld8\.a r4=\[r5\],r6 + 836: 40 58 17 b0 2c 00 ld8\.a r4=\[r5\],-149 + 83c: 00 00 04 00 nop\.i 0x0 + 840: 08 20 00 0a 5a 10 \[MMI\] ld8\.a\.nt1 r4=\[r5\] + 846: 40 30 14 b4 24 00 ld8\.a\.nt1 r4=\[r5\],r6 + 84c: 00 00 04 00 nop\.i 0x0 + 850: 08 20 e0 0b 5a 16 \[MMI\] ld8\.a\.nt1 r4=\[r5\],-136 + 856: 40 00 14 bc 20 00 ld8\.a\.nta r4=\[r5\] + 85c: 00 00 04 00 nop\.i 0x0 + 860: 08 20 18 0a 5e 12 \[MMI\] ld8\.a\.nta r4=\[r5\],r6 + 866: 40 28 14 be 2c 00 ld8\.a\.nta r4=\[r5\],-123 + 86c: 00 00 04 00 nop\.i 0x0 + 870: 08 20 00 0a 78 10 \[MMI\] ld8\.sa r4=\[r5\] + 876: 40 30 14 f0 24 00 ld8\.sa r4=\[r5\],r6 + 87c: 00 00 04 00 nop\.i 0x0 + 880: 08 20 48 0a 79 16 \[MMI\] ld8\.sa r4=\[r5\],-110 + 886: 40 00 14 f4 20 00 ld8\.sa\.nt1 r4=\[r5\] + 88c: 00 00 04 00 nop\.i 0x0 + 890: 08 20 18 0a 7a 12 \[MMI\] ld8\.sa\.nt1 r4=\[r5\],r6 + 896: 40 f8 14 f6 2c 00 ld8\.sa\.nt1 r4=\[r5\],-97 + 89c: 00 00 04 00 nop\.i 0x0 + 8a0: 08 20 00 0a 7e 10 \[MMI\] ld8\.sa\.nta r4=\[r5\] + 8a6: 40 30 14 fc 24 00 ld8\.sa\.nta r4=\[r5\],r6 + 8ac: 00 00 04 00 nop\.i 0x0 + 8b0: 08 20 b0 0a 7f 16 \[MMI\] ld8\.sa\.nta r4=\[r5\],-84 + 8b6: 40 00 14 30 22 00 ld8\.c\.clr r4=\[r5\] + 8bc: 00 00 04 00 nop\.i 0x0 + 8c0: 08 20 18 0a 18 13 \[MMI\] ld8\.c\.clr r4=\[r5\],r6 + 8c6: 40 c8 15 32 2e 00 ld8\.c\.clr r4=\[r5\],-71 + 8cc: 00 00 04 00 nop\.i 0x0 + 8d0: 08 20 00 0a 1a 11 \[MMI\] ld8\.c\.clr\.nt1 r4=\[r5\] + 8d6: 40 30 14 34 26 00 ld8\.c\.clr\.nt1 r4=\[r5\],r6 + 8dc: 00 00 04 00 nop\.i 0x0 + 8e0: 08 20 18 0b 1b 17 \[MMI\] ld8\.c\.clr\.nt1 r4=\[r5\],-58 + 8e6: 40 00 14 3c 22 00 ld8\.c\.clr\.nta r4=\[r5\] + 8ec: 00 00 04 00 nop\.i 0x0 + 8f0: 08 20 18 0a 1e 13 \[MMI\] ld8\.c\.clr\.nta r4=\[r5\],r6 + 8f6: 40 98 16 3e 2e 00 ld8\.c\.clr\.nta r4=\[r5\],-45 + 8fc: 00 00 04 00 nop\.i 0x0 + 900: 08 20 00 0a 38 11 \[MMI\] ld8\.c\.nc r4=\[r5\] + 906: 40 30 14 70 26 00 ld8\.c\.nc r4=\[r5\],r6 + 90c: 00 00 04 00 nop\.i 0x0 + 910: 08 20 80 0b 39 17 \[MMI\] ld8\.c\.nc r4=\[r5\],-32 + 916: 40 00 14 74 22 00 ld8\.c\.nc\.nt1 r4=\[r5\] + 91c: 00 00 04 00 nop\.i 0x0 + 920: 08 20 18 0a 3a 13 \[MMI\] ld8\.c\.nc\.nt1 r4=\[r5\],r6 + 926: 40 68 17 76 2e 00 ld8\.c\.nc\.nt1 r4=\[r5\],-19 + 92c: 00 00 04 00 nop\.i 0x0 + 930: 08 20 00 0a 3e 11 \[MMI\] ld8\.c\.nc\.nta r4=\[r5\] + 936: 40 30 14 7c 26 00 ld8\.c\.nc\.nta r4=\[r5\],r6 + 93c: 00 00 04 00 nop\.i 0x0 + 940: 08 20 e8 0b 3f 17 \[MMI\] ld8\.c\.nc\.nta r4=\[r5\],-6 + 946: 40 00 14 30 21 00 ld8\.bias r4=\[r5\] + 94c: 00 00 04 00 nop\.i 0x0 + 950: 08 20 18 0a 98 12 \[MMI\] ld8\.bias r4=\[r5\],r6 + 956: 40 38 14 30 29 00 ld8\.bias r4=\[r5\],7 + 95c: 00 00 04 00 nop\.i 0x0 + 960: 08 20 00 0a 9a 10 \[MMI\] ld8\.bias\.nt1 r4=\[r5\] + 966: 40 30 14 34 25 00 ld8\.bias\.nt1 r4=\[r5\],r6 + 96c: 00 00 04 00 nop\.i 0x0 + 970: 08 20 50 0a 9a 14 \[MMI\] ld8\.bias\.nt1 r4=\[r5\],20 + 976: 40 00 14 3c 21 00 ld8\.bias\.nta r4=\[r5\] + 97c: 00 00 04 00 nop\.i 0x0 + 980: 08 20 18 0a 9e 12 \[MMI\] ld8\.bias\.nta r4=\[r5\],r6 + 986: 40 08 15 3c 29 00 ld8\.bias\.nta r4=\[r5\],33 + 98c: 00 00 04 00 nop\.i 0x0 + 990: 08 20 00 0a b8 10 \[MMI\] ld8\.acq r4=\[r5\] + 996: 40 30 14 70 25 00 ld8\.acq r4=\[r5\],r6 + 99c: 00 00 04 00 nop\.i 0x0 + 9a0: 08 20 b8 0a b8 14 \[MMI\] ld8\.acq r4=\[r5\],46 + 9a6: 40 00 14 74 21 00 ld8\.acq\.nt1 r4=\[r5\] + 9ac: 00 00 04 00 nop\.i 0x0 + 9b0: 08 20 18 0a ba 12 \[MMI\] ld8\.acq\.nt1 r4=\[r5\],r6 + 9b6: 40 d8 15 74 29 00 ld8\.acq\.nt1 r4=\[r5\],59 + 9bc: 00 00 04 00 nop\.i 0x0 + 9c0: 08 20 00 0a be 10 \[MMI\] ld8\.acq\.nta r4=\[r5\] + 9c6: 40 30 14 7c 25 00 ld8\.acq\.nta r4=\[r5\],r6 + 9cc: 00 00 04 00 nop\.i 0x0 + 9d0: 08 20 20 0b be 14 \[MMI\] ld8\.acq\.nta r4=\[r5\],72 + 9d6: 40 00 14 b0 22 00 ld8\.c\.clr\.acq r4=\[r5\] + 9dc: 00 00 04 00 nop\.i 0x0 + 9e0: 08 20 18 0a 58 13 \[MMI\] ld8\.c\.clr\.acq r4=\[r5\],r6 + 9e6: 40 a8 16 b0 2a 00 ld8\.c\.clr\.acq r4=\[r5\],85 + 9ec: 00 00 04 00 nop\.i 0x0 + 9f0: 08 20 00 0a 5a 11 \[MMI\] ld8\.c\.clr\.acq\.nt1 r4=\[r5\] + 9f6: 40 30 14 b4 26 00 ld8\.c\.clr\.acq\.nt1 r4=\[r5\],r6 + 9fc: 00 00 04 00 nop\.i 0x0 + a00: 08 20 88 0b 5a 15 \[MMI\] ld8\.c\.clr\.acq\.nt1 r4=\[r5\],98 + a06: 40 00 14 bc 22 00 ld8\.c\.clr\.acq\.nta r4=\[r5\] + a0c: 00 00 04 00 nop\.i 0x0 + a10: 08 20 18 0a 5e 13 \[MMI\] ld8\.c\.clr\.acq\.nta r4=\[r5\],r6 + a16: 40 78 17 bc 2a 00 ld8\.c\.clr\.acq\.nta r4=\[r5\],111 + a1c: 00 00 04 00 nop\.i 0x0 + a20: 08 20 00 0a d8 10 \[MMI\] ld8\.fill r4=\[r5\] + a26: 40 30 14 b0 25 00 ld8\.fill r4=\[r5\],r6 + a2c: 00 00 04 00 nop\.i 0x0 + a30: 08 20 f0 0b d8 14 \[MMI\] ld8\.fill r4=\[r5\],124 + a36: 40 00 14 b4 21 00 ld8\.fill\.nt1 r4=\[r5\] + a3c: 00 00 04 00 nop\.i 0x0 + a40: 08 20 18 0a da 12 \[MMI\] ld8\.fill\.nt1 r4=\[r5\],r6 + a46: 40 48 14 b6 29 00 ld8\.fill\.nt1 r4=\[r5\],137 + a4c: 00 00 04 00 nop\.i 0x0 + a50: 08 20 00 0a de 10 \[MMI\] ld8\.fill\.nta r4=\[r5\] + a56: 40 30 14 bc 25 00 ld8\.fill\.nta r4=\[r5\],r6 + a5c: 00 00 04 00 nop\.i 0x0 + a60: 08 20 58 0a df 14 \[MMI\] ld8\.fill\.nta r4=\[r5\],150 + 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f4=\[r5\] + c4c: 00 00 04 00 nop\.i 0x0 + c50: 08 20 18 0a 56 1a \[MMI\] ldfs\.a\.nta f4=\[r5\],r6 + c56: 40 a8 17 ae 3c 00 ldfs\.a\.nta f4=\[r5\],-11 + c5c: 00 00 04 00 nop\.i 0x0 + c60: 08 20 00 0a 70 18 \[MMI\] ldfs\.sa f4=\[r5\] + c66: 40 30 14 e0 34 00 ldfs\.sa f4=\[r5\],r6 + c6c: 00 00 04 00 nop\.i 0x0 + c70: 08 20 08 0a 70 1c \[MMI\] ldfs\.sa f4=\[r5\],2 + c76: 40 00 14 e4 30 00 ldfs\.sa\.nt1 f4=\[r5\] + c7c: 00 00 04 00 nop\.i 0x0 + c80: 08 20 18 0a 72 1a \[MMI\] ldfs\.sa\.nt1 f4=\[r5\],r6 + c86: 40 78 14 e4 38 00 ldfs\.sa\.nt1 f4=\[r5\],15 + c8c: 00 00 04 00 nop\.i 0x0 + c90: 08 20 00 0a 76 18 \[MMI\] ldfs\.sa\.nta f4=\[r5\] + c96: 40 30 14 ec 34 00 ldfs\.sa\.nta f4=\[r5\],r6 + c9c: 00 00 04 00 nop\.i 0x0 + ca0: 08 20 70 0a 76 1c \[MMI\] ldfs\.sa\.nta f4=\[r5\],28 + ca6: 40 00 14 20 32 00 ldfs\.c\.clr f4=\[r5\] + cac: 00 00 04 00 nop\.i 0x0 + cb0: 08 20 18 0a 10 1b \[MMI\] ldfs\.c\.clr f4=\[r5\],r6 + cb6: 40 48 15 20 3a 00 ldfs\.c\.clr f4=\[r5\],41 + cbc: 00 00 04 00 nop\.i 0x0 + cc0: 08 20 00 0a 12 19 \[MMI\] ldfs\.c\.clr\.nt1 f4=\[r5\] + cc6: 40 30 14 24 36 00 ldfs\.c\.clr\.nt1 f4=\[r5\],r6 + ccc: 00 00 04 00 nop\.i 0x0 + cd0: 08 20 d8 0a 12 1d \[MMI\] ldfs\.c\.clr\.nt1 f4=\[r5\],54 + cd6: 40 00 14 2c 32 00 ldfs\.c\.clr\.nta f4=\[r5\] + cdc: 00 00 04 00 nop\.i 0x0 + ce0: 08 20 18 0a 16 1b \[MMI\] ldfs\.c\.clr\.nta f4=\[r5\],r6 + ce6: 40 18 16 2c 3a 00 ldfs\.c\.clr\.nta f4=\[r5\],67 + cec: 00 00 04 00 nop\.i 0x0 + cf0: 08 20 00 0a 30 19 \[MMI\] ldfs\.c\.nc f4=\[r5\] + cf6: 40 30 14 60 36 00 ldfs\.c\.nc f4=\[r5\],r6 + cfc: 00 00 04 00 nop\.i 0x0 + d00: 08 20 40 0b 30 1d \[MMI\] ldfs\.c\.nc f4=\[r5\],80 + d06: 40 00 14 64 32 00 ldfs\.c\.nc\.nt1 f4=\[r5\] + d0c: 00 00 04 00 nop\.i 0x0 + d10: 08 20 18 0a 32 1b \[MMI\] ldfs\.c\.nc\.nt1 f4=\[r5\],r6 + d16: 40 e8 16 64 3a 00 ldfs\.c\.nc\.nt1 f4=\[r5\],93 + d1c: 00 00 04 00 nop\.i 0x0 + d20: 08 20 00 0a 36 19 \[MMI\] ldfs\.c\.nc\.nta f4=\[r5\] + d26: 40 30 14 6c 36 00 ldfs\.c\.nc\.nta f4=\[r5\],r6 + d2c: 00 00 04 00 nop\.i 0x0 + d30: 08 20 a8 0b 36 1d \[MMI\] ldfs\.c\.nc\.nta f4=\[r5\],106 + d36: 40 00 14 30 30 00 ldfd f4=\[r5\] + d3c: 00 00 04 00 nop\.i 0x0 + d40: 08 20 18 0a 18 1a \[MMI\] ldfd f4=\[r5\],r6 + d46: 40 b8 17 30 38 00 ldfd f4=\[r5\],119 + d4c: 00 00 04 00 nop\.i 0x0 + d50: 08 20 00 0a 1a 18 \[MMI\] ldfd\.nt1 f4=\[r5\] + d56: 40 30 14 34 34 00 ldfd\.nt1 f4=\[r5\],r6 + d5c: 00 00 04 00 nop\.i 0x0 + d60: 08 20 10 0a 1b 1c \[MMI\] ldfd\.nt1 f4=\[r5\],132 + d66: 40 00 14 3c 30 00 ldfd\.nta f4=\[r5\] + d6c: 00 00 04 00 nop\.i 0x0 + d70: 08 20 18 0a 1e 1a \[MMI\] ldfd\.nta f4=\[r5\],r6 + d76: 40 88 14 3e 38 00 ldfd\.nta f4=\[r5\],145 + d7c: 00 00 04 00 nop\.i 0x0 + d80: 08 20 00 0a 38 18 \[MMI\] ldfd\.s f4=\[r5\] + d86: 40 30 14 70 34 00 ldfd\.s f4=\[r5\],r6 + d8c: 00 00 04 00 nop\.i 0x0 + d90: 08 20 78 0a 39 1c \[MMI\] ldfd\.s f4=\[r5\],158 + d96: 40 00 14 74 30 00 ldfd\.s\.nt1 f4=\[r5\] + d9c: 00 00 04 00 nop\.i 0x0 + da0: 08 20 18 0a 3a 1a \[MMI\] ldfd\.s\.nt1 f4=\[r5\],r6 + da6: 40 58 15 76 38 00 ldfd\.s\.nt1 f4=\[r5\],171 + dac: 00 00 04 00 nop\.i 0x0 + db0: 08 20 00 0a 3e 18 \[MMI\] ldfd\.s\.nta f4=\[r5\] + db6: 40 30 14 7c 34 00 ldfd\.s\.nta f4=\[r5\],r6 + dbc: 00 00 04 00 nop\.i 0x0 + dc0: 08 20 e0 0a 3f 1c \[MMI\] ldfd\.s\.nta f4=\[r5\],184 + dc6: 40 00 14 b0 30 00 ldfd\.a f4=\[r5\] + dcc: 00 00 04 00 nop\.i 0x0 + dd0: 08 20 18 0a 58 1a \[MMI\] ldfd\.a f4=\[r5\],r6 + dd6: 40 28 16 b2 38 00 ldfd\.a f4=\[r5\],197 + ddc: 00 00 04 00 nop\.i 0x0 + de0: 08 20 00 0a 5a 18 \[MMI\] ldfd\.a\.nt1 f4=\[r5\] + de6: 40 30 14 b4 34 00 ldfd\.a\.nt1 f4=\[r5\],r6 + dec: 00 00 04 00 nop\.i 0x0 + df0: 08 20 48 0b 5b 1c \[MMI\] ldfd\.a\.nt1 f4=\[r5\],210 + df6: 40 00 14 bc 30 00 ldfd\.a\.nta f4=\[r5\] + dfc: 00 00 04 00 nop\.i 0x0 + e00: 08 20 18 0a 5e 1a \[MMI\] ldfd\.a\.nta f4=\[r5\],r6 + e06: 40 f8 16 be 38 00 ldfd\.a\.nta f4=\[r5\],223 + e0c: 00 00 04 00 nop\.i 0x0 + e10: 08 20 00 0a 78 18 \[MMI\] ldfd\.sa f4=\[r5\] + e16: 40 30 14 f0 34 00 ldfd\.sa f4=\[r5\],r6 + e1c: 00 00 04 00 nop\.i 0x0 + e20: 08 20 b0 0b 79 1c \[MMI\] ldfd\.sa f4=\[r5\],236 + e26: 40 00 14 f4 30 00 ldfd\.sa\.nt1 f4=\[r5\] + e2c: 00 00 04 00 nop\.i 0x0 + e30: 08 20 18 0a 7a 1a \[MMI\] ldfd\.sa\.nt1 f4=\[r5\],r6 + e36: 40 c8 17 f6 38 00 ldfd\.sa\.nt1 f4=\[r5\],249 + e3c: 00 00 04 00 nop\.i 0x0 + e40: 08 20 00 0a 7e 18 \[MMI\] ldfd\.sa\.nta f4=\[r5\] + e46: 40 30 14 fc 34 00 ldfd\.sa\.nta f4=\[r5\],r6 + e4c: 00 00 04 00 nop\.i 0x0 + e50: 08 20 18 0a 7e 1e \[MMI\] ldfd\.sa\.nta f4=\[r5\],-250 + e56: 40 00 14 30 32 00 ldfd\.c\.clr f4=\[r5\] + e5c: 00 00 04 00 nop\.i 0x0 + e60: 08 20 18 0a 18 1b \[MMI\] ldfd\.c\.clr f4=\[r5\],r6 + e66: 40 98 14 30 3e 00 ldfd\.c\.clr f4=\[r5\],-237 + e6c: 00 00 04 00 nop\.i 0x0 + e70: 08 20 00 0a 1a 19 \[MMI\] ldfd\.c\.clr\.nt1 f4=\[r5\] + e76: 40 30 14 34 36 00 ldfd\.c\.clr\.nt1 f4=\[r5\],r6 + e7c: 00 00 04 00 nop\.i 0x0 + e80: 08 20 80 0a 1a 1f \[MMI\] ldfd\.c\.clr\.nt1 f4=\[r5\],-224 + e86: 40 00 14 3c 32 00 ldfd\.c\.clr\.nta f4=\[r5\] + e8c: 00 00 04 00 nop\.i 0x0 + e90: 08 20 18 0a 1e 1b \[MMI\] ldfd\.c\.clr\.nta f4=\[r5\],r6 + e96: 40 68 15 3c 3e 00 ldfd\.c\.clr\.nta f4=\[r5\],-211 + e9c: 00 00 04 00 nop\.i 0x0 + ea0: 08 20 00 0a 38 19 \[MMI\] ldfd\.c\.nc f4=\[r5\] + ea6: 40 30 14 70 36 00 ldfd\.c\.nc f4=\[r5\],r6 + eac: 00 00 04 00 nop\.i 0x0 + eb0: 08 20 e8 0a 38 1f \[MMI\] ldfd\.c\.nc f4=\[r5\],-198 + eb6: 40 00 14 74 32 00 ldfd\.c\.nc\.nt1 f4=\[r5\] + ebc: 00 00 04 00 nop\.i 0x0 + ec0: 08 20 18 0a 3a 1b \[MMI\] ldfd\.c\.nc\.nt1 f4=\[r5\],r6 + ec6: 40 38 16 74 3e 00 ldfd\.c\.nc\.nt1 f4=\[r5\],-185 + ecc: 00 00 04 00 nop\.i 0x0 + ed0: 08 20 00 0a 3e 19 \[MMI\] ldfd\.c\.nc\.nta f4=\[r5\] + ed6: 40 30 14 7c 36 00 ldfd\.c\.nc\.nta f4=\[r5\],r6 + edc: 00 00 04 00 nop\.i 0x0 + ee0: 08 20 50 0b 3e 1f \[MMI\] ldfd\.c\.nc\.nta f4=\[r5\],-172 + ee6: 40 00 14 10 30 00 ldf8 f4=\[r5\] + eec: 00 00 04 00 nop\.i 0x0 + ef0: 08 20 18 0a 08 1a \[MMI\] ldf8 f4=\[r5\],r6 + ef6: 40 08 17 10 3c 00 ldf8 f4=\[r5\],-159 + efc: 00 00 04 00 nop\.i 0x0 + f00: 08 20 00 0a 0a 18 \[MMI\] ldf8\.nt1 f4=\[r5\] + f06: 40 30 14 14 34 00 ldf8\.nt1 f4=\[r5\],r6 + f0c: 00 00 04 00 nop\.i 0x0 + f10: 08 20 b8 0b 0a 1e \[MMI\] ldf8\.nt1 f4=\[r5\],-146 + f16: 40 00 14 1c 30 00 ldf8\.nta f4=\[r5\] + f1c: 00 00 04 00 nop\.i 0x0 + f20: 08 20 18 0a 0e 1a \[MMI\] ldf8\.nta f4=\[r5\],r6 + f26: 40 d8 17 1c 3c 00 ldf8\.nta f4=\[r5\],-133 + f2c: 00 00 04 00 nop\.i 0x0 + f30: 08 20 00 0a 28 18 \[MMI\] ldf8\.s f4=\[r5\] + f36: 40 30 14 50 34 00 ldf8\.s f4=\[r5\],r6 + f3c: 00 00 04 00 nop\.i 0x0 + f40: 08 20 20 0a 29 1e \[MMI\] ldf8\.s f4=\[r5\],-120 + f46: 40 00 14 54 30 00 ldf8\.s\.nt1 f4=\[r5\] + f4c: 00 00 04 00 nop\.i 0x0 + f50: 08 20 18 0a 2a 1a \[MMI\] ldf8\.s\.nt1 f4=\[r5\],r6 + f56: 40 a8 14 56 3c 00 ldf8\.s\.nt1 f4=\[r5\],-107 + f5c: 00 00 04 00 nop\.i 0x0 + f60: 08 20 00 0a 2e 18 \[MMI\] ldf8\.s\.nta f4=\[r5\] + f66: 40 30 14 5c 34 00 ldf8\.s\.nta f4=\[r5\],r6 + f6c: 00 00 04 00 nop\.i 0x0 + f70: 08 20 88 0a 2f 1e \[MMI\] ldf8\.s\.nta f4=\[r5\],-94 + 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fec: 00 00 04 00 nop\.i 0x0 + ff0: 08 20 00 0a 6e 18 \[MMI\] ldf8\.sa\.nta f4=\[r5\] + ff6: 40 30 14 dc 34 00 ldf8\.sa\.nta f4=\[r5\],r6 + ffc: 00 00 04 00 nop\.i 0x0 + 1000: 08 20 c0 0b 6f 1e \[MMI\] ldf8\.sa\.nta f4=\[r5\],-16 + 1006: 40 00 14 10 32 00 ldf8\.c\.clr f4=\[r5\] + 100c: 00 00 04 00 nop\.i 0x0 + 1010: 08 20 18 0a 08 1b \[MMI\] ldf8\.c\.clr f4=\[r5\],r6 + 1016: 40 e8 17 12 3e 00 ldf8\.c\.clr f4=\[r5\],-3 + 101c: 00 00 04 00 nop\.i 0x0 + 1020: 08 20 00 0a 0a 19 \[MMI\] ldf8\.c\.clr\.nt1 f4=\[r5\] + 1026: 40 30 14 14 36 00 ldf8\.c\.clr\.nt1 f4=\[r5\],r6 + 102c: 00 00 04 00 nop\.i 0x0 + 1030: 08 20 28 0a 0a 1d \[MMI\] ldf8\.c\.clr\.nt1 f4=\[r5\],10 + 1036: 40 00 14 1c 32 00 ldf8\.c\.clr\.nta f4=\[r5\] + 103c: 00 00 04 00 nop\.i 0x0 + 1040: 08 20 18 0a 0e 1b \[MMI\] ldf8\.c\.clr\.nta f4=\[r5\],r6 + 1046: 40 b8 14 1c 3a 00 ldf8\.c\.clr\.nta f4=\[r5\],23 + 104c: 00 00 04 00 nop\.i 0x0 + 1050: 08 20 00 0a 28 19 \[MMI\] ldf8\.c\.nc f4=\[r5\] + 1056: 40 30 14 50 36 00 ldf8\.c\.nc f4=\[r5\],r6 + 105c: 00 00 04 00 nop\.i 0x0 + 1060: 08 20 90 0a 28 1d \[MMI\] ldf8\.c\.nc f4=\[r5\],36 + 1066: 40 00 14 54 32 00 ldf8\.c\.nc\.nt1 f4=\[r5\] + 106c: 00 00 04 00 nop\.i 0x0 + 1070: 08 20 18 0a 2a 1b \[MMI\] ldf8\.c\.nc\.nt1 f4=\[r5\],r6 + 1076: 40 88 15 54 3a 00 ldf8\.c\.nc\.nt1 f4=\[r5\],49 + 107c: 00 00 04 00 nop\.i 0x0 + 1080: 08 20 00 0a 2e 19 \[MMI\] ldf8\.c\.nc\.nta f4=\[r5\] + 1086: 40 30 14 5c 36 00 ldf8\.c\.nc\.nta f4=\[r5\],r6 + 108c: 00 00 04 00 nop\.i 0x0 + 1090: 08 20 f8 0a 2e 1d \[MMI\] ldf8\.c\.nc\.nta f4=\[r5\],62 + 1096: 40 00 14 00 30 00 ldfe f4=\[r5\] + 109c: 00 00 04 00 nop\.i 0x0 + 10a0: 08 20 18 0a 00 1a \[MMI\] ldfe f4=\[r5\],r6 + 10a6: 40 58 16 00 38 00 ldfe f4=\[r5\],75 + 10ac: 00 00 04 00 nop\.i 0x0 + 10b0: 08 20 00 0a 02 18 \[MMI\] ldfe\.nt1 f4=\[r5\] + 10b6: 40 30 14 04 34 00 ldfe\.nt1 f4=\[r5\],r6 + 10bc: 00 00 04 00 nop\.i 0x0 + 10c0: 08 20 60 0b 02 1c \[MMI\] ldfe\.nt1 f4=\[r5\],88 + 10c6: 40 00 14 0c 30 00 ldfe\.nta f4=\[r5\] + 10cc: 00 00 04 00 nop\.i 0x0 + 10d0: 08 20 18 0a 06 1a \[MMI\] ldfe\.nta f4=\[r5\],r6 + 10d6: 40 28 17 0c 38 00 ldfe\.nta f4=\[r5\],101 + 10dc: 00 00 04 00 nop\.i 0x0 + 10e0: 08 20 00 0a 20 18 \[MMI\] ldfe\.s f4=\[r5\] + 10e6: 40 30 14 40 34 00 ldfe\.s f4=\[r5\],r6 + 10ec: 00 00 04 00 nop\.i 0x0 + 10f0: 08 20 c8 0b 20 1c \[MMI\] ldfe\.s f4=\[r5\],114 + 10f6: 40 00 14 44 30 00 ldfe\.s\.nt1 f4=\[r5\] + 10fc: 00 00 04 00 nop\.i 0x0 + 1100: 08 20 18 0a 22 1a \[MMI\] ldfe\.s\.nt1 f4=\[r5\],r6 + 1106: 40 f8 17 44 38 00 ldfe\.s\.nt1 f4=\[r5\],127 + 110c: 00 00 04 00 nop\.i 0x0 + 1110: 08 20 00 0a 26 18 \[MMI\] ldfe\.s\.nta f4=\[r5\] + 1116: 40 30 14 4c 34 00 ldfe\.s\.nta f4=\[r5\],r6 + 111c: 00 00 04 00 nop\.i 0x0 + 1120: 08 20 30 0a 27 1c \[MMI\] ldfe\.s\.nta f4=\[r5\],140 + 1126: 40 00 14 80 30 00 ldfe\.a f4=\[r5\] + 112c: 00 00 04 00 nop\.i 0x0 + 1130: 08 20 18 0a 40 1a \[MMI\] ldfe\.a f4=\[r5\],r6 + 1136: 40 c8 14 82 38 00 ldfe\.a f4=\[r5\],153 + 113c: 00 00 04 00 nop\.i 0x0 + 1140: 08 20 00 0a 42 18 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00 nop\.i 0x0 + 1290: 08 00 14 08 90 19 \[MMI\] stfs \[r4\]=f5 + 1296: c0 2d 10 20 3f 00 stfs \[r4\]=f5,-164 + 129c: 00 00 04 00 nop\.i 0x0 + 12a0: 08 00 14 08 96 19 \[MMI\] stfs\.nta \[r4\]=f5 + 12a6: 90 2e 10 2c 3f 00 stfs\.nta \[r4\]=f5,-151 + 12ac: 00 00 04 00 nop\.i 0x0 + 12b0: 08 00 14 08 98 19 \[MMI\] stfd \[r4\]=f5 + 12b6: 60 2f 10 30 3f 00 stfd \[r4\]=f5,-138 + 12bc: 00 00 04 00 nop\.i 0x0 + 12c0: 08 00 14 08 9e 19 \[MMI\] stfd\.nta \[r4\]=f5 + 12c6: 30 28 10 3e 3f 00 stfd\.nta \[r4\]=f5,-125 + 12cc: 00 00 04 00 nop\.i 0x0 + 12d0: 08 00 14 08 88 19 \[MMI\] stf8 \[r4\]=f5 + 12d6: 00 29 10 12 3f 00 stf8 \[r4\]=f5,-112 + 12dc: 00 00 04 00 nop\.i 0x0 + 12e0: 08 00 14 08 8e 19 \[MMI\] stf8\.nta \[r4\]=f5 + 12e6: d0 29 10 1e 3f 00 stf8\.nta \[r4\]=f5,-99 + 12ec: 00 00 04 00 nop\.i 0x0 + 12f0: 08 00 14 08 80 19 \[MMI\] stfe \[r4\]=f5 + 12f6: a0 2a 10 02 3f 00 stfe \[r4\]=f5,-86 + 12fc: 00 00 04 00 nop\.i 0x0 + 1300: 08 00 14 08 86 19 \[MMI\] stfe\.nta \[r4\]=f5 + 1306: 70 2b 10 0e 3f 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ldfpd\.a\.nt1 f4,f5=\[r5\] + 14c6: 40 28 14 b6 34 00 ldfpd\.a\.nt1 f4,f5=\[r5\],16 + 14cc: 00 00 04 00 nop\.i 0x0 + 14d0: 08 20 14 0a 5f 18 \[MMI\] ldfpd\.a\.nta f4,f5=\[r5\] + 14d6: 40 28 14 be 34 00 ldfpd\.a\.nta f4,f5=\[r5\],16 + 14dc: 00 00 04 00 nop\.i 0x0 + 14e0: 08 20 14 0a 79 18 \[MMI\] ldfpd\.sa f4,f5=\[r5\] + 14e6: 40 28 14 f2 34 00 ldfpd\.sa f4,f5=\[r5\],16 + 14ec: 00 00 04 00 nop\.i 0x0 + 14f0: 08 20 14 0a 7b 18 \[MMI\] ldfpd\.sa\.nt1 f4,f5=\[r5\] + 14f6: 40 28 14 f6 34 00 ldfpd\.sa\.nt1 f4,f5=\[r5\],16 + 14fc: 00 00 04 00 nop\.i 0x0 + 1500: 08 20 14 0a 7f 18 \[MMI\] ldfpd\.sa\.nta f4,f5=\[r5\] + 1506: 40 28 14 fe 34 00 ldfpd\.sa\.nta f4,f5=\[r5\],16 + 150c: 00 00 04 00 nop\.i 0x0 + 1510: 08 20 14 0a 19 19 \[MMI\] ldfpd\.c\.clr f4,f5=\[r5\] + 1516: 40 28 14 32 36 00 ldfpd\.c\.clr f4,f5=\[r5\],16 + 151c: 00 00 04 00 nop\.i 0x0 + 1520: 08 20 14 0a 1b 19 \[MMI\] ldfpd\.c\.clr\.nt1 f4,f5=\[r5\] + 1526: 40 28 14 36 36 00 ldfpd\.c\.clr\.nt1 f4,f5=\[r5\],16 + 152c: 00 00 04 00 nop\.i 0x0 + 1530: 08 20 14 0a 1f 19 \[MMI\] ldfpd\.c\.clr\.nta f4,f5=\[r5\] + 1536: 40 28 14 3e 36 00 ldfpd\.c\.clr\.nta f4,f5=\[r5\],16 + 153c: 00 00 04 00 nop\.i 0x0 + 1540: 08 20 14 0a 39 19 \[MMI\] ldfpd\.c\.nc f4,f5=\[r5\] + 1546: 40 28 14 72 36 00 ldfpd\.c\.nc f4,f5=\[r5\],16 + 154c: 00 00 04 00 nop\.i 0x0 + 1550: 08 20 14 0a 3b 19 \[MMI\] ldfpd\.c\.nc\.nt1 f4,f5=\[r5\] + 1556: 40 28 14 76 36 00 ldfpd\.c\.nc\.nt1 f4,f5=\[r5\],16 + 155c: 00 00 04 00 nop\.i 0x0 + 1560: 08 20 14 0a 3f 19 \[MMI\] ldfpd\.c\.nc\.nta f4,f5=\[r5\] + 1566: 40 28 14 7e 36 00 ldfpd\.c\.nc\.nta f4,f5=\[r5\],16 + 156c: 00 00 04 00 nop\.i 0x0 + 1570: 08 20 14 0a 09 18 \[MMI\] ldfp8 f4,f5=\[r5\] + 1576: 40 28 14 12 34 00 ldfp8 f4,f5=\[r5\],16 + 157c: 00 00 04 00 nop\.i 0x0 + 1580: 08 20 14 0a 0b 18 \[MMI\] ldfp8\.nt1 f4,f5=\[r5\] + 1586: 40 28 14 16 34 00 ldfp8\.nt1 f4,f5=\[r5\],16 + 158c: 00 00 04 00 nop\.i 0x0 + 1590: 08 20 14 0a 0f 18 \[MMI\] ldfp8\.nta f4,f5=\[r5\] + 1596: 40 28 14 1e 34 00 ldfp8\.nta f4,f5=\[r5\],16 + 159c: 00 00 04 00 nop\.i 0x0 + 15a0: 08 20 14 0a 29 18 \[MMI\] ldfp8\.s f4,f5=\[r5\] + 15a6: 40 28 14 52 34 00 ldfp8\.s f4,f5=\[r5\],16 + 15ac: 00 00 04 00 nop\.i 0x0 + 15b0: 08 20 14 0a 2b 18 \[MMI\] ldfp8\.s\.nt1 f4,f5=\[r5\] + 15b6: 40 28 14 56 34 00 ldfp8\.s\.nt1 f4,f5=\[r5\],16 + 15bc: 00 00 04 00 nop\.i 0x0 + 15c0: 08 20 14 0a 2f 18 \[MMI\] ldfp8\.s\.nta f4,f5=\[r5\] + 15c6: 40 28 14 5e 34 00 ldfp8\.s\.nta f4,f5=\[r5\],16 + 15cc: 00 00 04 00 nop\.i 0x0 + 15d0: 08 20 14 0a 49 18 \[MMI\] ldfp8\.a f4,f5=\[r5\] + 15d6: 40 28 14 92 34 00 ldfp8\.a f4,f5=\[r5\],16 + 15dc: 00 00 04 00 nop\.i 0x0 + 15e0: 08 20 14 0a 4b 18 \[MMI\] ldfp8\.a\.nt1 f4,f5=\[r5\] + 15e6: 40 28 14 96 34 00 ldfp8\.a\.nt1 f4,f5=\[r5\],16 + 15ec: 00 00 04 00 nop\.i 0x0 + 15f0: 08 20 14 0a 4f 18 \[MMI\] ldfp8\.a\.nta f4,f5=\[r5\] + 15f6: 40 28 14 9e 34 00 ldfp8\.a\.nta f4,f5=\[r5\],16 + 15fc: 00 00 04 00 nop\.i 0x0 + 1600: 08 20 14 0a 69 18 \[MMI\] ldfp8\.sa f4,f5=\[r5\] + 1606: 40 28 14 d2 34 00 ldfp8\.sa f4,f5=\[r5\],16 + 160c: 00 00 04 00 nop\.i 0x0 + 1610: 08 20 14 0a 6b 18 \[MMI\] ldfp8\.sa\.nt1 f4,f5=\[r5\] + 1616: 40 28 14 d6 34 00 ldfp8\.sa\.nt1 f4,f5=\[r5\],16 + 161c: 00 00 04 00 nop\.i 0x0 + 1620: 08 20 14 0a 6f 18 \[MMI\] ldfp8\.sa\.nta f4,f5=\[r5\] + 1626: 40 28 14 de 34 00 ldfp8\.sa\.nta f4,f5=\[r5\],16 + 162c: 00 00 04 00 nop\.i 0x0 + 1630: 08 20 14 0a 09 19 \[MMI\] ldfp8\.c\.clr f4,f5=\[r5\] + 1636: 40 28 14 12 36 00 ldfp8\.c\.clr f4,f5=\[r5\],16 + 163c: 00 00 04 00 nop\.i 0x0 + 1640: 08 20 14 0a 0b 19 \[MMI\] ldfp8\.c\.clr\.nt1 f4,f5=\[r5\] + 1646: 40 28 14 16 36 00 ldfp8\.c\.clr\.nt1 f4,f5=\[r5\],16 + 164c: 00 00 04 00 nop\.i 0x0 + 1650: 08 20 14 0a 0f 19 \[MMI\] ldfp8\.c\.clr\.nta f4,f5=\[r5\] + 1656: 40 28 14 1e 36 00 ldfp8\.c\.clr\.nta f4,f5=\[r5\],16 + 165c: 00 00 04 00 nop\.i 0x0 + 1660: 08 20 14 0a 29 19 \[MMI\] ldfp8\.c\.nc f4,f5=\[r5\] + 1666: 40 28 14 52 36 00 ldfp8\.c\.nc f4,f5=\[r5\],16 + 166c: 00 00 04 00 nop\.i 0x0 + 1670: 08 20 14 0a 2b 19 \[MMI\] ldfp8\.c\.nc\.nt1 f4,f5=\[r5\] + 1676: 40 28 14 56 36 00 ldfp8\.c\.nc\.nt1 f4,f5=\[r5\],16 + 167c: 00 00 04 00 nop\.i 0x0 + 1680: 08 20 14 0a 2f 19 \[MMI\] ldfp8\.c\.nc\.nta f4,f5=\[r5\] + 1686: 40 28 14 5e 36 00 ldfp8\.c\.nc\.nta f4,f5=\[r5\],16 + 168c: 00 00 04 00 nop\.i 0x0 + 1690: 08 00 00 08 60 19 \[MMI\] lfetch \[r4\] + 1696: 00 28 10 c0 36 00 lfetch \[r4\],r5 + 169c: 00 00 04 00 nop\.i 0x0 + 16a0: 08 00 78 09 61 1f \[MMI\] lfetch \[r4\],-34 + 16a6: 00 00 10 c4 32 00 lfetch\.nt1 \[r4\] + 16ac: 00 00 04 00 nop\.i 0x0 + 16b0: 08 00 14 08 62 1b \[MMI\] lfetch\.nt1 \[r4\],r5 + 16b6: 00 58 13 c6 3e 00 lfetch\.nt1 \[r4\],-21 + 16bc: 00 00 04 00 nop\.i 0x0 + 16c0: 08 00 00 08 64 19 \[MMI\] lfetch\.nt2 \[r4\] + 16c6: 00 28 10 c8 36 00 lfetch\.nt2 \[r4\],r5 + 16cc: 00 00 04 00 nop\.i 0x0 + 16d0: 08 00 e0 09 65 1f \[MMI\] lfetch\.nt2 \[r4\],-8 + 16d6: 00 00 10 cc 32 00 lfetch\.nta \[r4\] + 16dc: 00 00 04 00 nop\.i 0x0 + 16e0: 08 00 14 08 66 1b \[MMI\] lfetch\.nta \[r4\],r5 + 16e6: 00 28 10 cc 3a 00 lfetch\.nta \[r4\],5 + 16ec: 00 00 04 00 nop\.i 0x0 + 16f0: 08 00 00 08 70 19 \[MMI\] lfetch\.fault \[r4\] + 16f6: 00 28 10 e0 36 00 lfetch\.fault \[r4\],r5 + 16fc: 00 00 04 00 nop\.i 0x0 + 1700: 08 00 48 08 70 1d \[MMI\] lfetch\.fault \[r4\],18 + 1706: 00 00 10 e4 32 00 lfetch\.fault\.nt1 \[r4\] + 170c: 00 00 04 00 nop\.i 0x0 + 1710: 08 00 14 08 72 1b \[MMI\] lfetch\.fault\.nt1 \[r4\],r5 + 1716: 00 f8 10 e4 3a 00 lfetch\.fault\.nt1 \[r4\],31 + 171c: 00 00 04 00 nop\.i 0x0 + 1720: 08 00 00 08 74 19 \[MMI\] lfetch\.fault\.nt2 \[r4\] + 1726: 00 28 10 e8 36 00 lfetch\.fault\.nt2 \[r4\],r5 + 172c: 00 00 04 00 nop\.i 0x0 + 1730: 08 00 b0 08 74 1d \[MMI\] lfetch\.fault\.nt2 \[r4\],44 + 1736: 00 00 10 ec 32 00 lfetch\.fault\.nta \[r4\] + 173c: 00 00 04 00 nop\.i 0x0 + 1740: 08 00 14 08 76 1b \[MMI\] lfetch\.fault\.nta \[r4\],r5 + 1746: 00 c8 11 ec 3a 00 lfetch\.fault\.nta \[r4\],57 + 174c: 00 00 04 00 nop\.i 0x0 + 1750: 08 00 00 08 68 19 \[MMI\] lfetch\.excl \[r4\] + 1756: 00 28 10 d0 36 00 lfetch\.excl \[r4\],r5 + 175c: 00 00 04 00 nop\.i 0x0 + 1760: 08 00 18 09 68 1d \[MMI\] lfetch\.excl \[r4\],70 + 1766: 00 00 10 d4 32 00 lfetch\.excl\.nt1 \[r4\] + 176c: 00 00 04 00 nop\.i 0x0 + 1770: 08 00 14 08 6a 1b \[MMI\] lfetch\.excl\.nt1 \[r4\],r5 + 1776: 00 98 12 d4 3a 00 lfetch\.excl\.nt1 \[r4\],83 + 177c: 00 00 04 00 nop\.i 0x0 + 1780: 08 00 00 08 6c 19 \[MMI\] lfetch\.excl\.nt2 \[r4\] + 1786: 00 28 10 d8 36 00 lfetch\.excl\.nt2 \[r4\],r5 + 178c: 00 00 04 00 nop\.i 0x0 + 1790: 08 00 80 09 6c 1d \[MMI\] lfetch\.excl\.nt2 \[r4\],96 + 1796: 00 00 10 dc 32 00 lfetch\.excl\.nta \[r4\] + 179c: 00 00 04 00 nop\.i 0x0 + 17a0: 08 00 14 08 6e 1b \[MMI\] lfetch\.excl\.nta \[r4\],r5 + 17a6: 00 68 13 dc 3a 00 lfetch\.excl\.nta \[r4\],109 + 17ac: 00 00 04 00 nop\.i 0x0 + 17b0: 08 00 00 08 78 19 \[MMI\] lfetch\.fault\.excl \[r4\] + 17b6: 00 28 10 f0 36 00 lfetch\.fault\.excl \[r4\],r5 + 17bc: 00 00 04 00 nop\.i 0x0 + 17c0: 08 00 e8 09 78 1d \[MMI\] lfetch\.fault\.excl \[r4\],122 + 17c6: 00 00 10 f4 32 00 lfetch\.fault\.excl\.nt1 \[r4\] + 17cc: 00 00 04 00 nop\.i 0x0 + 17d0: 08 00 14 08 7a 1b \[MMI\] lfetch\.fault\.excl\.nt1 \[r4\],r5 + 17d6: 00 38 10 f6 3a 00 lfetch\.fault\.excl\.nt1 \[r4\],135 + 17dc: 00 00 04 00 nop\.i 0x0 + 17e0: 08 00 00 08 7c 19 \[MMI\] lfetch\.fault\.excl\.nt2 \[r4\] + 17e6: 00 28 10 f8 36 00 lfetch\.fault\.excl\.nt2 \[r4\],r5 + 17ec: 00 00 04 00 nop\.i 0x0 + 17f0: 08 00 50 08 7d 1d \[MMI\] lfetch\.fault\.excl\.nt2 \[r4\],148 + 17f6: 00 00 10 fc 32 00 lfetch\.fault\.excl\.nta \[r4\] + 17fc: 00 00 04 00 nop\.i 0x0 + 1800: 08 00 14 08 7e 1b \[MMI\] lfetch\.fault\.excl\.nta \[r4\],r5 + 1806: 00 08 11 fe 3a 00 lfetch\.fault\.excl\.nta \[r4\],161 + 180c: 00 00 04 00 nop\.i 0x0 + 1810: 08 20 18 0a 01 10 \[MMI\] cmpxchg1\.acq r4=\[r5\],r6,ar\.ccv + 1816: 40 30 14 06 20 00 cmpxchg1\.acq\.nt1 r4=\[r5\],r6,ar\.ccv + 181c: 00 00 04 00 nop\.i 0x0 + 1820: 08 20 18 0a 07 10 \[MMI\] cmpxchg1\.acq\.nta r4=\[r5\],r6,ar\.ccv + 1826: 40 30 14 42 20 00 cmpxchg1\.rel r4=\[r5\],r6,ar\.ccv + 182c: 00 00 04 00 nop\.i 0x0 + 1830: 08 20 18 0a 23 10 \[MMI\] cmpxchg1\.rel\.nt1 r4=\[r5\],r6,ar\.ccv + 1836: 40 30 14 4e 20 00 cmpxchg1\.rel\.nta r4=\[r5\],r6,ar\.ccv + 183c: 00 00 04 00 nop\.i 0x0 + 1840: 08 20 18 0a 09 10 \[MMI\] cmpxchg2\.acq r4=\[r5\],r6,ar\.ccv + 1846: 40 30 14 16 20 00 cmpxchg2\.acq\.nt1 r4=\[r5\],r6,ar\.ccv + 184c: 00 00 04 00 nop\.i 0x0 + 1850: 08 20 18 0a 0f 10 \[MMI\] cmpxchg2\.acq\.nta r4=\[r5\],r6,ar\.ccv + 1856: 40 30 14 52 20 00 cmpxchg2\.rel r4=\[r5\],r6,ar\.ccv + 185c: 00 00 04 00 nop\.i 0x0 + 1860: 08 20 18 0a 2b 10 \[MMI\] cmpxchg2\.rel\.nt1 r4=\[r5\],r6,ar\.ccv + 1866: 40 30 14 5e 20 00 cmpxchg2\.rel\.nta r4=\[r5\],r6,ar\.ccv + 186c: 00 00 04 00 nop\.i 0x0 + 1870: 08 20 18 0a 11 10 \[MMI\] cmpxchg4\.acq r4=\[r5\],r6,ar\.ccv + 1876: 40 30 14 26 20 00 cmpxchg4\.acq\.nt1 r4=\[r5\],r6,ar\.ccv + 187c: 00 00 04 00 nop\.i 0x0 + 1880: 08 20 18 0a 17 10 \[MMI\] cmpxchg4\.acq\.nta r4=\[r5\],r6,ar\.ccv + 1886: 40 30 14 62 20 00 cmpxchg4\.rel r4=\[r5\],r6,ar\.ccv + 188c: 00 00 04 00 nop\.i 0x0 + 1890: 08 20 18 0a 33 10 \[MMI\] cmpxchg4\.rel\.nt1 r4=\[r5\],r6,ar\.ccv + 1896: 40 30 14 6e 20 00 cmpxchg4\.rel\.nta r4=\[r5\],r6,ar\.ccv + 189c: 00 00 04 00 nop\.i 0x0 + 18a0: 08 20 18 0a 19 10 \[MMI\] cmpxchg8\.acq r4=\[r5\],r6,ar\.ccv + 18a6: 40 30 14 36 20 00 cmpxchg8\.acq\.nt1 r4=\[r5\],r6,ar\.ccv + 18ac: 00 00 04 00 nop\.i 0x0 + 18b0: 08 20 18 0a 1f 10 \[MMI\] cmpxchg8\.acq\.nta r4=\[r5\],r6,ar\.ccv + 18b6: 40 30 14 72 20 00 cmpxchg8\.rel r4=\[r5\],r6,ar\.ccv + 18bc: 00 00 04 00 nop\.i 0x0 + 18c0: 08 20 18 0a 3b 10 \[MMI\] cmpxchg8\.rel\.nt1 r4=\[r5\],r6,ar\.ccv + 18c6: 40 30 14 7e 20 00 cmpxchg8\.rel\.nta r4=\[r5\],r6,ar\.ccv + 18cc: 00 00 04 00 nop\.i 0x0 + 18d0: 08 20 18 0a 41 10 \[MMI\] xchg1 r4=\[r5\],r6 + 18d6: 40 30 14 86 20 00 xchg1\.nt1 r4=\[r5\],r6 + 18dc: 00 00 04 00 nop\.i 0x0 + 18e0: 08 20 18 0a 47 10 \[MMI\] xchg1\.nta r4=\[r5\],r6 + 18e6: 40 30 14 92 20 00 xchg2 r4=\[r5\],r6 + 18ec: 00 00 04 00 nop\.i 0x0 + 18f0: 08 20 18 0a 4b 10 \[MMI\] xchg2\.nt1 r4=\[r5\],r6 + 18f6: 40 30 14 9e 20 00 xchg2\.nta r4=\[r5\],r6 + 18fc: 00 00 04 00 nop\.i 0x0 + 1900: 08 20 18 0a 51 10 \[MMI\] xchg4 r4=\[r5\],r6 + 1906: 40 30 14 a6 20 00 xchg4\.nt1 r4=\[r5\],r6 + 190c: 00 00 04 00 nop\.i 0x0 + 1910: 08 20 18 0a 57 10 \[MMI\] xchg4\.nta r4=\[r5\],r6 + 1916: 40 30 14 b2 20 00 xchg8 r4=\[r5\],r6 + 191c: 00 00 04 00 nop\.i 0x0 + 1920: 08 20 18 0a 5b 10 \[MMI\] xchg8\.nt1 r4=\[r5\],r6 + 1926: 40 30 14 be 20 00 xchg8\.nta r4=\[r5\],r6 + 192c: 00 00 04 00 nop\.i 0x0 + 1930: 08 20 10 0a 91 10 \[MMI\] fetchadd4\.acq r4=\[r5\],-16 + 1936: 40 28 14 26 21 00 fetchadd4\.acq\.nt1 r4=\[r5\],-8 + 193c: 00 00 04 00 nop\.i 0x0 + 1940: 08 20 18 0a 97 10 \[MMI\] fetchadd4\.acq\.nta r4=\[r5\],-4 + 1946: 40 38 14 32 21 00 fetchadd8\.acq r4=\[r5\],-1 + 194c: 00 00 04 00 nop\.i 0x0 + 1950: 08 20 0c 0a 9b 10 \[MMI\] fetchadd8\.acq\.nt1 r4=\[r5\],1 + 1956: 40 10 14 3e 21 00 fetchadd8\.acq\.nta r4=\[r5\],4 + 195c: 00 00 04 00 nop\.i 0x0 + 1960: 08 20 04 0a b1 10 \[MMI\] fetchadd4\.rel r4=\[r5\],8 + 1966: 40 00 14 66 21 00 fetchadd4\.rel\.nt1 r4=\[r5\],16 + 196c: 00 00 04 00 nop\.i 0x0 + 1970: 08 20 10 0a b7 10 \[MMI\] fetchadd4\.rel\.nta r4=\[r5\],-16 + 1976: 40 28 14 72 21 00 fetchadd8\.rel r4=\[r5\],-8 + 197c: 00 00 04 00 nop\.i 0x0 + 1980: 08 20 18 0a bb 10 \[MMI\] fetchadd8\.rel\.nt1 r4=\[r5\],-4 + 1986: 40 38 14 7e 21 00 fetchadd8\.rel\.nta r4=\[r5\],-1 + 198c: 00 00 04 00 nop\.i 0x0 + 1990: 08 20 14 00 e1 18 \[MMI\] setf\.sig f4=r5 + 1996: 40 28 00 d2 31 00 setf\.exp f4=r5 + 199c: 00 00 04 00 nop\.i 0x0 + 19a0: 08 20 14 00 f1 18 \[MMI\] setf\.s f4=r5 + 19a6: 40 28 00 f2 31 00 setf\.d f4=r5 + 19ac: 00 00 04 00 nop\.i 0x0 + 19b0: 08 20 14 00 e1 10 \[MMI\] getf\.sig r4=f5 + 19b6: 40 28 00 d2 21 00 getf\.exp r4=f5 + 19bc: 00 00 04 00 nop\.i 0x0 + 19c0: 08 20 14 00 f1 10 \[MMI\] getf\.s r4=f5 + 19c6: 40 28 00 f2 21 00 getf\.d r4=f5 + 19cc: 00 00 04 00 nop\.i 0x0 + 19d0: 08 18 13 f8 7f 06 \[MMI\] chk\.s\.m r4,0 <_start> + 19d6: 30 26 f0 ff 0d 00 chk\.s f4,0 <_start> + 19dc: 00 00 04 00 nop\.i 0x0 + 19e0: 08 20 88 f9 3f 03 \[MMI\] chk\.a\.nc r4,0 <_start> + 19e6: 40 10 f3 ff 06 00 chk\.a\.clr r4,0 <_start> + 19ec: 00 00 04 00 nop\.i 0x0 + 19f0: 08 20 84 f9 bf 03 \[MMI\] chk\.a\.nc f4,0 <_start> + 19f6: 40 08 f3 ff 07 00 chk\.a\.clr f4,0 <_start> + 19fc: 00 00 04 00 nop\.i 0x0 + 1a00: 08 00 00 00 10 00 \[MMI\] invala + 1a06: 00 00 00 40 00 00 fwb + 1a0c: 00 00 04 00 nop\.i 0x0 + 1a10: 08 00 00 00 22 00 \[MMI\] mf + 1a16: 00 00 00 46 00 00 mf\.a + 1a1c: 00 00 04 00 nop\.i 0x0 + 1a20: 08 00 00 00 30 00 \[MMI\] srlz\.d + 1a26: 00 00 00 62 00 00 srlz\.i + 1a2c: 00 00 04 00 nop\.i 0x0 + 1a30: 09 00 00 00 33 00 \[MMI\] sync\.i + 1a36: 00 00 00 02 00 00 nop\.m 0x0 + 1a3c: 00 00 04 00 nop\.i 0x0;; + 1a40: 01 20 70 18 82 05 \[MII\] alloc r4=ar\.pfs,28,12,16 + 1a46: 00 00 00 02 00 00 nop\.i 0x0 + 1a4c: 00 00 04 00 nop\.i 0x0;; + 1a50: 01 00 00 00 0c 00 \[MII\] flushrs + 1a56: 00 00 00 02 00 00 nop\.i 0x0 + 1a5c: 00 00 04 00 nop\.i 0x0;; + 1a60: 00 00 00 00 0a 00 \[MII\] loadrs + 1a66: 00 00 00 02 00 00 nop\.i 0x0 + 1a6c: 00 00 04 00 nop\.i 0x0 + 1a70: 08 20 00 00 12 00 \[MMI\] invala\.e r4 + 1a76: 40 00 00 26 00 00 invala\.e f4 + 1a7c: 00 00 04 00 nop\.i 0x0 + 1a80: 08 00 00 08 30 04 \[MMI\] fc r4 + 1a86: 00 00 10 68 08 00 ptc\.e r4 + 1a8c: 00 00 04 00 nop\.i 0x0 + 1a90: 08 00 00 00 00 00 \[MMI\] break\.m 0x0 + 1a96: f0 ff 1f 00 00 00 break\.m 0x1ffff + 1a9c: 00 00 04 00 nop\.i 0x0 + 1aa0: 08 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 1aa6: f0 ff 1f 00 00 00 break\.m 0x1ffff + 1aac: 00 00 04 00 nop\.i 0x0 + 1ab0: 08 20 18 0a 38 04 \[MMI\] probe\.r r4=r5,r6 + 1ab6: 40 30 14 72 08 00 probe\.w r4=r5,r6 + 1abc: 00 00 04 00 nop\.i 0x0 + 1ac0: 08 20 00 0a 18 04 \[MMI\] probe\.r r4=r5,0 + 1ac6: 40 08 14 32 08 00 probe\.w r4=r5,1 + 1acc: 00 00 04 00 nop\.i 0x0 + 1ad0: 08 00 08 06 32 04 \[MMI\] probe\.r\.fault r3,2 + 1ad6: 00 18 0c 66 08 00 probe\.w\.fault r3,3 + 1adc: 00 00 04 00 nop\.i 0x0 + 1ae0: 08 00 00 06 31 04 \[MMI\] probe\.rw\.fault r3,0 + 1ae6: 00 00 00 02 00 00 nop\.m 0x0 + 1aec: 00 00 04 00 nop\.i 0x0 + 1af0: 0b 00 20 00 2e 04 \[MMI\] itc\.d r8;; + 1af6: 00 00 00 02 00 00 nop\.m 0x0 + 1afc: 00 00 04 00 nop\.i 0x0;; + 1b00: 0a 00 24 00 2f 04 \[MMI\] itc\.i r9;; + 1b06: 40 23 01 08 00 00 sum 0x1234 + 1b0c: 00 00 04 00 nop\.i 0x0 + 1b10: 08 50 55 d5 25 00 \[MMI\] rum 0x5aaaaa + 1b16: f0 ff ff 6d 04 00 ssm 0xffffff + 1b1c: 00 00 04 00 nop\.i 0x0 + 1b20: 08 00 00 00 27 00 \[MMI\] rsm 0x400000 + 1b26: 00 28 10 12 08 00 ptc\.l r4,r5 + 1b2c: 00 00 04 00 nop\.i 0x0 + 1b30: 0a 00 14 08 0a 04 \[MMI\] ptc\.g r4,r5;; + 1b36: 00 00 00 02 00 00 nop\.m 0x0 + 1b3c: 00 00 04 00 nop\.i 0x0 + 1b40: 0a 00 14 08 0b 04 \[MMI\] ptc\.ga r4,r5;; + 1b46: 00 00 00 02 00 00 nop\.m 0x0 + 1b4c: 00 00 04 00 nop\.i 0x0 + 1b50: 08 00 14 08 0c 04 \[MMI\] ptr\.d r4,r5 + 1b56: 00 28 10 1a 08 00 ptr\.i r4,r5 + 1b5c: 00 00 04 00 nop\.i 0x0 + 1b60: 08 20 00 0a 1a 04 \[MMI\] thash r4=r5 + 1b66: 40 00 14 36 08 00 ttag r4=r5 + 1b6c: 00 00 04 00 nop\.i 0x0 + 1b70: 09 20 00 0a 1e 04 \[MMI\] tpa r4=r5 + 1b76: 40 00 14 3e 08 00 tak r4=r5 + 1b7c: 00 00 04 00 nop\.i 0x0;; diff --git a/gas/testsuite/gas/ia64/opc-m.pl b/gas/testsuite/gas/ia64/opc-m.pl new file mode 100644 index 0000000..93c7bc9 --- /dev/null +++ b/gas/testsuite/gas/ia64/opc-m.pl @@ -0,0 +1,218 @@ +print ".text\n\t.type _start,@", "function\n_start:\n\n"; + +@ldhint = ( "", ".nt1", ".nta" ); +@ldspec = ( "", ".s", ".a", ".sa", ".c.clr", ".c.nc" ); +@sthint = ( "", ".nta" ); + +$i = 0; + +# Integer Load + +foreach $s ( "1", "2", "4", "8" ) { + foreach $e (@ldspec, ".bias", ".acq", ".c.clr.acq") { + foreach $l (@ldhint) { + print "\tld${s}${e}${l} r4 = [r5]\n"; + print "\tld${s}${e}${l} r4 = [r5], r6\n"; + print "\tld${s}${e}${l} r4 = [r5], ", $i - 256, "\n"; + $i = ($i + 13) % 512; + } + print "\n"; + } +} + +# Integer Fill + +for $l (@ldhint) { + print "\tld8.fill${l} r4 = [r5]\n"; + print "\tld8.fill${l} r4 = [r5], r6\n"; + print "\tld8.fill${l} r4 = [r5], ", $i - 256, "\n"; + $i = ($i + 13) % 512; +} +print "\n"; + +# Integer Store + +foreach $s ("1", "2", "4", "8", "1.rel", "2.rel", "4.rel", "8.rel", "8.spill") { + for $l (@sthint) { + print "\tst${s}${l} [r4] = r5\n"; + print "\tst${s}${l} [r4] = r5, ", $i - 256, "\n"; + $i = ($i + 13) % 512; + } + print "\n"; +} + +# Floating Point Load + +foreach $s ( "fs", "fd", "f8", "fe" ) { + foreach $e (@ldspec) { + foreach $l (@ldhint) { + print "\tld${s}${e}${l} f4 = [r5]\n"; + print "\tld${s}${e}${l} f4 = [r5], r6\n"; + print "\tld${s}${e}${l} f4 = [r5], ", $i - 256, "\n"; + $i = ($i + 13) % 512; + } + print "\n"; + } +} + +# Floating Point Fill + +for $l (@ldhint) { + print "\tldf.fill${l} f4 = [r5]\n"; + print "\tldf.fill${l} f4 = [r5], r6\n"; + print "\tldf.fill${l} f4 = [r5], ", $i - 256, "\n"; + $i = ($i + 13) % 512; +} +print "\n"; + +# Floating Point Store + +foreach $s ( "fs", "fd", "f8", "fe", "f.spill" ) { + for $l (@sthint) { + print "\tst${s}${l} [r4] = f5\n"; + print "\tst${s}${l} [r4] = f5, ", $i - 256, "\n"; + $i = ($i + 13) % 512; + } + print "\n"; +} + +# Floating Point Load Pair + +foreach $s ( "fps", "fpd", "fp8" ) { + foreach $e (@ldspec) { + foreach $l (@ldhint) { + print "\tld${s}${e}${l} f4, f5 = [r5]\n"; + print "\tld${s}${e}${l} f4, f5 = [r5], ", ($s eq "fps" ? 8 : 16), "\n"; + } + print "\n"; + } +} + +# Line Prefetch + +@lfhint = ( "", ".nt1", ".nt2", ".nta" ); + +foreach $e ( "", ".excl" ) { + foreach $f ( "", ".fault" ) { + foreach $h (@lfhint) { + print "\tlfetch${f}${e}${h} [r4]\n"; + print "\tlfetch${f}${e}${h} [r4], r5\n"; + print "\tlfetch${f}${e}${h} [r4], ", $i - 256, "\n"; + $i = ($i + 13) % 512; + } + print "\n"; + } +} + +# Compare and Exchange + +foreach $s ( "1", "2", "4", "8" ) { + foreach $e ( ".acq", ".rel" ) { + foreach $h (@ldhint) { + print "\tcmpxchg${s}${e}${h} r4 = [r5], r6, ar.ccv\n"; + } + print "\n"; + } +} + +# Exchange + +foreach $s ( "1", "2", "4", "8" ) { + foreach $h (@ldhint) { + print "\txchg${s}${h} r4 = [r5], r6\n"; + } + print "\n"; +} + +# Fetch and Add + +$i = 0; +@inc3 = ( -16, -8, -4, -1, 1, 4, 8, 16 ); +foreach $s ( "4.acq", "8.acq", "4.rel", "8.rel" ) { + foreach $h (@ldhint) { + print "\tfetchadd${s}${h} r4 = [r5], ", $inc3[$i], "\n"; + $i = ($i + 1) % 8; + } + print "\n"; +} + +# Get/Set FR + +foreach $e ( ".sig", ".exp", ".s", ".d" ) { + print "\tsetf${e} f4 = r5\n"; +} +print "\n"; + +foreach $e ( ".sig", ".exp", ".s", ".d" ) { + print "\tgetf${e} r4 = f5\n"; +} +print "\n"; + +# Speculation and Advanced Load Checkso + +print <<END + chk.s.m r4, _start + chk.s f4, _start + chk.a.nc r4, _start + chk.a.clr r4, _start + chk.a.nc f4, _start + chk.a.clr f4, _start + + invala + fwb + mf + mf.a + srlz.d + srlz.i + sync.i + nop.m 0 + nop.i 0 + + { .mii; alloc r4 = ar.pfs, 2, 10, 16, 16 } + + { .mii; flushrs } + { .mii; loadrs } + + invala.e r4 + invala.e f4 + + fc r4 + ptc.e r4 + + break.m 0 + break.m 0x1ffff + + nop.m 0 + break.m 0x1ffff + + probe.r r4 = r5, r6 + probe.w r4 = r5, r6 + + probe.r r4 = r5, 0 + probe.w r4 = r5, 1 + + probe.r.fault r3, 2 + probe.w.fault r3, 3 + probe.rw.fault r3, 0 + + itc.d r8 + itc.i r9 + + sum 0x1234 + rum 0x5aaaaa + ssm 0xffffff + rsm 0x400000 + + ptc.l r4, r5 + ptc.g r4, r5 + ptc.ga r4, r5 + ptr.d r4, r5 + ptr.i r4, r5 + + thash r4 = r5 + ttag r4 = r5 + tpa r4 = r5 + tak r4 = r5 + +END +; diff --git a/gas/testsuite/gas/ia64/opc-m.s b/gas/testsuite/gas/ia64/opc-m.s new file mode 100644 index 0000000..fa6e66a --- /dev/null +++ b/gas/testsuite/gas/ia64/opc-m.s @@ -0,0 +1,1009 @@ +.text + .type _start,@function +_start: + + ld1 r4 = [r5] + ld1 r4 = [r5], r6 + ld1 r4 = [r5], -256 + ld1.nt1 r4 = [r5] + ld1.nt1 r4 = [r5], r6 + ld1.nt1 r4 = [r5], -243 + ld1.nta r4 = [r5] + ld1.nta r4 = [r5], r6 + ld1.nta r4 = [r5], -230 + + ld1.s r4 = [r5] + ld1.s r4 = [r5], r6 + ld1.s r4 = [r5], -217 + ld1.s.nt1 r4 = [r5] + ld1.s.nt1 r4 = [r5], r6 + ld1.s.nt1 r4 = [r5], -204 + ld1.s.nta r4 = [r5] + ld1.s.nta r4 = [r5], r6 + ld1.s.nta r4 = [r5], -191 + + ld1.a r4 = [r5] + ld1.a r4 = [r5], r6 + ld1.a r4 = [r5], -178 + ld1.a.nt1 r4 = [r5] + ld1.a.nt1 r4 = [r5], r6 + ld1.a.nt1 r4 = [r5], -165 + ld1.a.nta r4 = [r5] + ld1.a.nta r4 = [r5], r6 + ld1.a.nta r4 = [r5], -152 + + ld1.sa r4 = [r5] + ld1.sa r4 = [r5], r6 + ld1.sa r4 = [r5], -139 + ld1.sa.nt1 r4 = [r5] + ld1.sa.nt1 r4 = [r5], r6 + ld1.sa.nt1 r4 = [r5], -126 + ld1.sa.nta r4 = [r5] + ld1.sa.nta r4 = [r5], r6 + ld1.sa.nta r4 = [r5], -113 + + ld1.c.clr r4 = [r5] + ld1.c.clr r4 = [r5], r6 + ld1.c.clr r4 = [r5], -100 + ld1.c.clr.nt1 r4 = [r5] + ld1.c.clr.nt1 r4 = [r5], r6 + ld1.c.clr.nt1 r4 = [r5], -87 + ld1.c.clr.nta r4 = [r5] + ld1.c.clr.nta r4 = [r5], r6 + ld1.c.clr.nta r4 = [r5], -74 + + ld1.c.nc r4 = [r5] + ld1.c.nc r4 = [r5], r6 + ld1.c.nc r4 = [r5], -61 + ld1.c.nc.nt1 r4 = [r5] + ld1.c.nc.nt1 r4 = [r5], r6 + ld1.c.nc.nt1 r4 = [r5], -48 + ld1.c.nc.nta r4 = [r5] + ld1.c.nc.nta r4 = [r5], r6 + ld1.c.nc.nta r4 = [r5], -35 + + ld1.bias r4 = [r5] + ld1.bias r4 = [r5], r6 + ld1.bias r4 = [r5], -22 + ld1.bias.nt1 r4 = [r5] + ld1.bias.nt1 r4 = [r5], r6 + ld1.bias.nt1 r4 = [r5], -9 + ld1.bias.nta r4 = [r5] + ld1.bias.nta r4 = [r5], r6 + ld1.bias.nta r4 = [r5], 4 + + ld1.acq r4 = [r5] + ld1.acq r4 = [r5], r6 + ld1.acq r4 = [r5], 17 + ld1.acq.nt1 r4 = [r5] + ld1.acq.nt1 r4 = [r5], r6 + ld1.acq.nt1 r4 = [r5], 30 + ld1.acq.nta r4 = [r5] + ld1.acq.nta r4 = [r5], r6 + ld1.acq.nta r4 = [r5], 43 + + ld1.c.clr.acq r4 = [r5] + ld1.c.clr.acq r4 = [r5], r6 + ld1.c.clr.acq r4 = [r5], 56 + ld1.c.clr.acq.nt1 r4 = [r5] + ld1.c.clr.acq.nt1 r4 = [r5], r6 + ld1.c.clr.acq.nt1 r4 = [r5], 69 + ld1.c.clr.acq.nta r4 = [r5] + ld1.c.clr.acq.nta r4 = [r5], r6 + ld1.c.clr.acq.nta r4 = [r5], 82 + + ld2 r4 = [r5] + ld2 r4 = [r5], r6 + ld2 r4 = [r5], 95 + ld2.nt1 r4 = [r5] + ld2.nt1 r4 = [r5], r6 + ld2.nt1 r4 = [r5], 108 + ld2.nta r4 = [r5] + ld2.nta r4 = [r5], r6 + ld2.nta r4 = [r5], 121 + + ld2.s r4 = [r5] + ld2.s r4 = [r5], r6 + ld2.s r4 = [r5], 134 + ld2.s.nt1 r4 = [r5] + ld2.s.nt1 r4 = [r5], r6 + ld2.s.nt1 r4 = [r5], 147 + ld2.s.nta r4 = [r5] + ld2.s.nta r4 = [r5], r6 + ld2.s.nta r4 = [r5], 160 + + ld2.a r4 = [r5] + ld2.a r4 = [r5], r6 + ld2.a r4 = [r5], 173 + ld2.a.nt1 r4 = [r5] + ld2.a.nt1 r4 = [r5], r6 + ld2.a.nt1 r4 = [r5], 186 + ld2.a.nta r4 = [r5] + ld2.a.nta r4 = [r5], r6 + ld2.a.nta r4 = [r5], 199 + + ld2.sa r4 = [r5] + ld2.sa r4 = [r5], r6 + ld2.sa r4 = [r5], 212 + ld2.sa.nt1 r4 = [r5] + ld2.sa.nt1 r4 = [r5], r6 + ld2.sa.nt1 r4 = [r5], 225 + ld2.sa.nta r4 = [r5] + ld2.sa.nta r4 = [r5], r6 + ld2.sa.nta r4 = [r5], 238 + + ld2.c.clr r4 = [r5] + ld2.c.clr r4 = [r5], r6 + ld2.c.clr r4 = [r5], 251 + ld2.c.clr.nt1 r4 = [r5] + ld2.c.clr.nt1 r4 = [r5], r6 + ld2.c.clr.nt1 r4 = [r5], -248 + ld2.c.clr.nta r4 = [r5] + ld2.c.clr.nta r4 = [r5], r6 + ld2.c.clr.nta r4 = [r5], -235 + + ld2.c.nc r4 = [r5] + ld2.c.nc r4 = [r5], r6 + ld2.c.nc r4 = [r5], -222 + ld2.c.nc.nt1 r4 = [r5] + ld2.c.nc.nt1 r4 = [r5], r6 + ld2.c.nc.nt1 r4 = [r5], -209 + ld2.c.nc.nta r4 = [r5] + ld2.c.nc.nta r4 = [r5], r6 + ld2.c.nc.nta r4 = [r5], -196 + + ld2.bias r4 = [r5] + ld2.bias r4 = [r5], r6 + ld2.bias r4 = [r5], -183 + ld2.bias.nt1 r4 = [r5] + ld2.bias.nt1 r4 = [r5], r6 + ld2.bias.nt1 r4 = [r5], -170 + ld2.bias.nta r4 = [r5] + ld2.bias.nta r4 = [r5], r6 + ld2.bias.nta r4 = [r5], -157 + + ld2.acq r4 = [r5] + ld2.acq r4 = [r5], r6 + ld2.acq r4 = [r5], -144 + ld2.acq.nt1 r4 = [r5] + ld2.acq.nt1 r4 = [r5], r6 + ld2.acq.nt1 r4 = [r5], -131 + ld2.acq.nta r4 = [r5] + ld2.acq.nta r4 = [r5], r6 + ld2.acq.nta r4 = [r5], -118 + + ld2.c.clr.acq r4 = [r5] + ld2.c.clr.acq r4 = [r5], r6 + ld2.c.clr.acq r4 = [r5], -105 + ld2.c.clr.acq.nt1 r4 = [r5] + ld2.c.clr.acq.nt1 r4 = [r5], r6 + ld2.c.clr.acq.nt1 r4 = [r5], -92 + ld2.c.clr.acq.nta r4 = [r5] + ld2.c.clr.acq.nta r4 = [r5], r6 + ld2.c.clr.acq.nta r4 = [r5], -79 + + ld4 r4 = [r5] + ld4 r4 = [r5], r6 + ld4 r4 = [r5], -66 + ld4.nt1 r4 = [r5] + ld4.nt1 r4 = [r5], r6 + ld4.nt1 r4 = [r5], -53 + ld4.nta r4 = [r5] + ld4.nta r4 = [r5], r6 + ld4.nta r4 = [r5], -40 + + ld4.s r4 = [r5] + ld4.s r4 = [r5], r6 + ld4.s r4 = [r5], -27 + ld4.s.nt1 r4 = [r5] + ld4.s.nt1 r4 = [r5], r6 + ld4.s.nt1 r4 = [r5], -14 + ld4.s.nta r4 = [r5] + ld4.s.nta r4 = [r5], r6 + ld4.s.nta r4 = [r5], -1 + + ld4.a r4 = [r5] + ld4.a r4 = [r5], r6 + ld4.a r4 = [r5], 12 + ld4.a.nt1 r4 = [r5] + ld4.a.nt1 r4 = [r5], r6 + ld4.a.nt1 r4 = [r5], 25 + ld4.a.nta r4 = [r5] + ld4.a.nta r4 = [r5], r6 + ld4.a.nta r4 = [r5], 38 + + ld4.sa r4 = [r5] + ld4.sa r4 = [r5], r6 + ld4.sa r4 = [r5], 51 + ld4.sa.nt1 r4 = [r5] + ld4.sa.nt1 r4 = [r5], r6 + ld4.sa.nt1 r4 = [r5], 64 + ld4.sa.nta r4 = [r5] + ld4.sa.nta r4 = [r5], r6 + ld4.sa.nta r4 = [r5], 77 + + ld4.c.clr r4 = [r5] + ld4.c.clr r4 = [r5], r6 + ld4.c.clr r4 = [r5], 90 + ld4.c.clr.nt1 r4 = [r5] + ld4.c.clr.nt1 r4 = [r5], r6 + ld4.c.clr.nt1 r4 = [r5], 103 + ld4.c.clr.nta r4 = [r5] + ld4.c.clr.nta r4 = [r5], r6 + ld4.c.clr.nta r4 = [r5], 116 + + ld4.c.nc r4 = [r5] + ld4.c.nc r4 = [r5], r6 + ld4.c.nc r4 = [r5], 129 + ld4.c.nc.nt1 r4 = [r5] + ld4.c.nc.nt1 r4 = [r5], r6 + ld4.c.nc.nt1 r4 = [r5], 142 + ld4.c.nc.nta r4 = [r5] + ld4.c.nc.nta r4 = [r5], r6 + ld4.c.nc.nta r4 = [r5], 155 + + ld4.bias r4 = [r5] + ld4.bias r4 = [r5], r6 + ld4.bias r4 = [r5], 168 + ld4.bias.nt1 r4 = [r5] + ld4.bias.nt1 r4 = [r5], r6 + ld4.bias.nt1 r4 = [r5], 181 + ld4.bias.nta r4 = [r5] + ld4.bias.nta r4 = [r5], r6 + ld4.bias.nta r4 = [r5], 194 + + ld4.acq r4 = [r5] + ld4.acq r4 = [r5], r6 + ld4.acq r4 = [r5], 207 + ld4.acq.nt1 r4 = [r5] + ld4.acq.nt1 r4 = [r5], r6 + ld4.acq.nt1 r4 = [r5], 220 + ld4.acq.nta r4 = [r5] + ld4.acq.nta r4 = [r5], r6 + ld4.acq.nta r4 = [r5], 233 + + ld4.c.clr.acq r4 = [r5] + ld4.c.clr.acq r4 = [r5], r6 + ld4.c.clr.acq r4 = [r5], 246 + ld4.c.clr.acq.nt1 r4 = [r5] + ld4.c.clr.acq.nt1 r4 = [r5], r6 + ld4.c.clr.acq.nt1 r4 = [r5], -253 + ld4.c.clr.acq.nta r4 = [r5] + ld4.c.clr.acq.nta r4 = [r5], r6 + ld4.c.clr.acq.nta r4 = [r5], -240 + + ld8 r4 = [r5] + ld8 r4 = [r5], r6 + ld8 r4 = [r5], -227 + ld8.nt1 r4 = [r5] + ld8.nt1 r4 = [r5], r6 + ld8.nt1 r4 = [r5], -214 + ld8.nta r4 = [r5] + ld8.nta r4 = [r5], r6 + ld8.nta r4 = [r5], -201 + + ld8.s r4 = [r5] + ld8.s r4 = [r5], r6 + ld8.s r4 = [r5], -188 + ld8.s.nt1 r4 = [r5] + ld8.s.nt1 r4 = [r5], r6 + ld8.s.nt1 r4 = [r5], -175 + ld8.s.nta r4 = [r5] + ld8.s.nta r4 = [r5], r6 + ld8.s.nta r4 = [r5], -162 + + ld8.a r4 = [r5] + ld8.a r4 = [r5], r6 + ld8.a r4 = [r5], -149 + ld8.a.nt1 r4 = [r5] + ld8.a.nt1 r4 = [r5], r6 + ld8.a.nt1 r4 = [r5], -136 + ld8.a.nta r4 = [r5] + ld8.a.nta r4 = [r5], r6 + ld8.a.nta r4 = [r5], -123 + + ld8.sa r4 = [r5] + ld8.sa r4 = [r5], r6 + ld8.sa r4 = [r5], -110 + ld8.sa.nt1 r4 = [r5] + ld8.sa.nt1 r4 = [r5], r6 + ld8.sa.nt1 r4 = [r5], -97 + ld8.sa.nta r4 = [r5] + ld8.sa.nta r4 = [r5], r6 + ld8.sa.nta r4 = [r5], -84 + + ld8.c.clr r4 = [r5] + ld8.c.clr r4 = [r5], r6 + ld8.c.clr r4 = [r5], -71 + ld8.c.clr.nt1 r4 = [r5] + ld8.c.clr.nt1 r4 = [r5], r6 + ld8.c.clr.nt1 r4 = [r5], -58 + ld8.c.clr.nta r4 = [r5] + ld8.c.clr.nta r4 = [r5], r6 + ld8.c.clr.nta r4 = [r5], -45 + + ld8.c.nc r4 = [r5] + ld8.c.nc r4 = [r5], r6 + ld8.c.nc r4 = [r5], -32 + ld8.c.nc.nt1 r4 = [r5] + ld8.c.nc.nt1 r4 = [r5], r6 + ld8.c.nc.nt1 r4 = [r5], -19 + ld8.c.nc.nta r4 = [r5] + ld8.c.nc.nta r4 = [r5], r6 + ld8.c.nc.nta r4 = [r5], -6 + + ld8.bias r4 = [r5] + ld8.bias r4 = [r5], r6 + ld8.bias r4 = [r5], 7 + ld8.bias.nt1 r4 = [r5] + ld8.bias.nt1 r4 = [r5], r6 + ld8.bias.nt1 r4 = [r5], 20 + ld8.bias.nta r4 = [r5] + ld8.bias.nta r4 = [r5], r6 + ld8.bias.nta r4 = [r5], 33 + + ld8.acq r4 = [r5] + ld8.acq r4 = [r5], r6 + ld8.acq r4 = [r5], 46 + ld8.acq.nt1 r4 = [r5] + ld8.acq.nt1 r4 = [r5], r6 + ld8.acq.nt1 r4 = [r5], 59 + ld8.acq.nta r4 = [r5] + ld8.acq.nta r4 = [r5], r6 + ld8.acq.nta r4 = [r5], 72 + + ld8.c.clr.acq r4 = [r5] + ld8.c.clr.acq r4 = [r5], r6 + ld8.c.clr.acq r4 = [r5], 85 + ld8.c.clr.acq.nt1 r4 = [r5] + ld8.c.clr.acq.nt1 r4 = [r5], r6 + ld8.c.clr.acq.nt1 r4 = [r5], 98 + ld8.c.clr.acq.nta r4 = [r5] + ld8.c.clr.acq.nta r4 = [r5], r6 + ld8.c.clr.acq.nta r4 = [r5], 111 + + ld8.fill r4 = [r5] + ld8.fill r4 = [r5], r6 + ld8.fill r4 = [r5], 124 + ld8.fill.nt1 r4 = [r5] + ld8.fill.nt1 r4 = [r5], r6 + ld8.fill.nt1 r4 = [r5], 137 + ld8.fill.nta r4 = [r5] + ld8.fill.nta r4 = [r5], r6 + ld8.fill.nta r4 = [r5], 150 + + st1 [r4] = r5 + st1 [r4] = r5, 163 + st1.nta [r4] = r5 + st1.nta [r4] = r5, 176 + + st2 [r4] = r5 + st2 [r4] = r5, 189 + st2.nta [r4] = r5 + st2.nta [r4] = r5, 202 + + st4 [r4] = r5 + st4 [r4] = r5, 215 + st4.nta [r4] = r5 + st4.nta [r4] = r5, 228 + + st8 [r4] = r5 + st8 [r4] = r5, 241 + st8.nta [r4] = r5 + st8.nta [r4] = r5, 254 + + st1.rel [r4] = r5 + st1.rel [r4] = r5, -245 + st1.rel.nta [r4] = r5 + st1.rel.nta [r4] = r5, -232 + + st2.rel [r4] = r5 + st2.rel [r4] = r5, -219 + st2.rel.nta [r4] = r5 + st2.rel.nta [r4] = r5, -206 + + st4.rel [r4] = r5 + st4.rel [r4] = r5, -193 + st4.rel.nta [r4] = r5 + st4.rel.nta [r4] = r5, -180 + + st8.rel [r4] = r5 + st8.rel [r4] = r5, -167 + st8.rel.nta [r4] = r5 + st8.rel.nta [r4] = r5, -154 + + st8.spill [r4] = r5 + st8.spill [r4] = r5, -141 + st8.spill.nta [r4] = r5 + st8.spill.nta [r4] = r5, -128 + + ldfs f4 = [r5] + ldfs f4 = [r5], r6 + ldfs f4 = [r5], -115 + ldfs.nt1 f4 = [r5] + ldfs.nt1 f4 = [r5], r6 + ldfs.nt1 f4 = [r5], -102 + ldfs.nta f4 = [r5] + ldfs.nta f4 = [r5], r6 + ldfs.nta f4 = [r5], -89 + + ldfs.s f4 = [r5] + ldfs.s f4 = [r5], r6 + ldfs.s f4 = [r5], -76 + ldfs.s.nt1 f4 = [r5] + ldfs.s.nt1 f4 = [r5], r6 + ldfs.s.nt1 f4 = [r5], -63 + ldfs.s.nta f4 = [r5] + ldfs.s.nta f4 = [r5], r6 + ldfs.s.nta f4 = [r5], -50 + + ldfs.a f4 = [r5] + ldfs.a f4 = [r5], r6 + ldfs.a f4 = [r5], -37 + ldfs.a.nt1 f4 = [r5] + ldfs.a.nt1 f4 = [r5], r6 + ldfs.a.nt1 f4 = [r5], -24 + ldfs.a.nta f4 = [r5] + ldfs.a.nta f4 = [r5], r6 + ldfs.a.nta f4 = [r5], -11 + + ldfs.sa f4 = [r5] + ldfs.sa f4 = [r5], r6 + ldfs.sa f4 = [r5], 2 + ldfs.sa.nt1 f4 = [r5] + ldfs.sa.nt1 f4 = [r5], r6 + ldfs.sa.nt1 f4 = [r5], 15 + ldfs.sa.nta f4 = [r5] + ldfs.sa.nta f4 = [r5], r6 + ldfs.sa.nta f4 = [r5], 28 + + ldfs.c.clr f4 = [r5] + ldfs.c.clr f4 = [r5], r6 + ldfs.c.clr f4 = [r5], 41 + ldfs.c.clr.nt1 f4 = [r5] + ldfs.c.clr.nt1 f4 = [r5], r6 + ldfs.c.clr.nt1 f4 = [r5], 54 + ldfs.c.clr.nta f4 = [r5] + ldfs.c.clr.nta f4 = [r5], r6 + ldfs.c.clr.nta f4 = [r5], 67 + + ldfs.c.nc f4 = [r5] + ldfs.c.nc f4 = [r5], r6 + ldfs.c.nc f4 = [r5], 80 + ldfs.c.nc.nt1 f4 = [r5] + ldfs.c.nc.nt1 f4 = [r5], r6 + ldfs.c.nc.nt1 f4 = [r5], 93 + ldfs.c.nc.nta f4 = [r5] + ldfs.c.nc.nta f4 = [r5], r6 + ldfs.c.nc.nta f4 = [r5], 106 + + ldfd f4 = [r5] + ldfd f4 = [r5], r6 + ldfd f4 = [r5], 119 + ldfd.nt1 f4 = [r5] + ldfd.nt1 f4 = [r5], r6 + ldfd.nt1 f4 = [r5], 132 + ldfd.nta f4 = [r5] + ldfd.nta f4 = [r5], r6 + ldfd.nta f4 = [r5], 145 + + ldfd.s f4 = [r5] + ldfd.s f4 = [r5], r6 + ldfd.s f4 = [r5], 158 + ldfd.s.nt1 f4 = [r5] + ldfd.s.nt1 f4 = [r5], r6 + ldfd.s.nt1 f4 = [r5], 171 + ldfd.s.nta f4 = [r5] + ldfd.s.nta f4 = [r5], r6 + ldfd.s.nta f4 = [r5], 184 + + ldfd.a f4 = [r5] + ldfd.a f4 = [r5], r6 + ldfd.a f4 = [r5], 197 + ldfd.a.nt1 f4 = [r5] + ldfd.a.nt1 f4 = [r5], r6 + ldfd.a.nt1 f4 = [r5], 210 + ldfd.a.nta f4 = [r5] + ldfd.a.nta f4 = [r5], r6 + ldfd.a.nta f4 = [r5], 223 + + ldfd.sa f4 = [r5] + ldfd.sa f4 = [r5], r6 + ldfd.sa f4 = [r5], 236 + ldfd.sa.nt1 f4 = [r5] + ldfd.sa.nt1 f4 = [r5], r6 + ldfd.sa.nt1 f4 = [r5], 249 + ldfd.sa.nta f4 = [r5] + ldfd.sa.nta f4 = [r5], r6 + ldfd.sa.nta f4 = [r5], -250 + + ldfd.c.clr f4 = [r5] + ldfd.c.clr f4 = [r5], r6 + ldfd.c.clr f4 = [r5], -237 + ldfd.c.clr.nt1 f4 = [r5] + ldfd.c.clr.nt1 f4 = [r5], r6 + ldfd.c.clr.nt1 f4 = [r5], -224 + ldfd.c.clr.nta f4 = [r5] + ldfd.c.clr.nta f4 = [r5], r6 + ldfd.c.clr.nta f4 = [r5], -211 + + ldfd.c.nc f4 = [r5] + ldfd.c.nc f4 = [r5], r6 + ldfd.c.nc f4 = [r5], -198 + ldfd.c.nc.nt1 f4 = [r5] + ldfd.c.nc.nt1 f4 = [r5], r6 + ldfd.c.nc.nt1 f4 = [r5], -185 + ldfd.c.nc.nta f4 = [r5] + ldfd.c.nc.nta f4 = [r5], r6 + ldfd.c.nc.nta f4 = [r5], -172 + + ldf8 f4 = [r5] + ldf8 f4 = [r5], r6 + ldf8 f4 = [r5], -159 + ldf8.nt1 f4 = [r5] + ldf8.nt1 f4 = [r5], r6 + ldf8.nt1 f4 = [r5], -146 + ldf8.nta f4 = [r5] + ldf8.nta f4 = [r5], r6 + ldf8.nta f4 = [r5], -133 + + ldf8.s f4 = [r5] + ldf8.s f4 = [r5], r6 + ldf8.s f4 = [r5], -120 + ldf8.s.nt1 f4 = [r5] + ldf8.s.nt1 f4 = [r5], r6 + ldf8.s.nt1 f4 = [r5], -107 + ldf8.s.nta f4 = [r5] + ldf8.s.nta f4 = [r5], r6 + ldf8.s.nta f4 = [r5], -94 + + ldf8.a f4 = [r5] + ldf8.a f4 = [r5], r6 + ldf8.a f4 = [r5], -81 + ldf8.a.nt1 f4 = [r5] + ldf8.a.nt1 f4 = [r5], r6 + ldf8.a.nt1 f4 = [r5], -68 + ldf8.a.nta f4 = [r5] + ldf8.a.nta f4 = [r5], r6 + ldf8.a.nta f4 = [r5], -55 + + ldf8.sa f4 = [r5] + ldf8.sa f4 = [r5], r6 + ldf8.sa f4 = [r5], -42 + ldf8.sa.nt1 f4 = [r5] + ldf8.sa.nt1 f4 = [r5], r6 + ldf8.sa.nt1 f4 = [r5], -29 + ldf8.sa.nta f4 = [r5] + ldf8.sa.nta f4 = [r5], r6 + ldf8.sa.nta f4 = [r5], -16 + + ldf8.c.clr f4 = [r5] + ldf8.c.clr f4 = [r5], r6 + ldf8.c.clr f4 = [r5], -3 + ldf8.c.clr.nt1 f4 = [r5] + ldf8.c.clr.nt1 f4 = [r5], r6 + ldf8.c.clr.nt1 f4 = [r5], 10 + ldf8.c.clr.nta f4 = [r5] + ldf8.c.clr.nta f4 = [r5], r6 + ldf8.c.clr.nta f4 = [r5], 23 + + ldf8.c.nc f4 = [r5] + ldf8.c.nc f4 = [r5], r6 + ldf8.c.nc f4 = [r5], 36 + ldf8.c.nc.nt1 f4 = [r5] + ldf8.c.nc.nt1 f4 = [r5], r6 + ldf8.c.nc.nt1 f4 = [r5], 49 + ldf8.c.nc.nta f4 = [r5] + ldf8.c.nc.nta f4 = [r5], r6 + ldf8.c.nc.nta f4 = [r5], 62 + + ldfe f4 = [r5] + ldfe f4 = [r5], r6 + ldfe f4 = [r5], 75 + ldfe.nt1 f4 = [r5] + ldfe.nt1 f4 = [r5], r6 + ldfe.nt1 f4 = [r5], 88 + ldfe.nta f4 = [r5] + ldfe.nta f4 = [r5], r6 + ldfe.nta f4 = [r5], 101 + + ldfe.s f4 = [r5] + ldfe.s f4 = [r5], r6 + ldfe.s f4 = [r5], 114 + ldfe.s.nt1 f4 = [r5] + ldfe.s.nt1 f4 = [r5], r6 + ldfe.s.nt1 f4 = [r5], 127 + ldfe.s.nta f4 = [r5] + ldfe.s.nta f4 = [r5], r6 + ldfe.s.nta f4 = [r5], 140 + + ldfe.a f4 = [r5] + ldfe.a f4 = [r5], r6 + ldfe.a f4 = [r5], 153 + ldfe.a.nt1 f4 = [r5] + ldfe.a.nt1 f4 = [r5], r6 + ldfe.a.nt1 f4 = [r5], 166 + ldfe.a.nta f4 = [r5] + ldfe.a.nta f4 = [r5], r6 + ldfe.a.nta f4 = [r5], 179 + + ldfe.sa f4 = [r5] + ldfe.sa f4 = [r5], r6 + ldfe.sa f4 = [r5], 192 + ldfe.sa.nt1 f4 = [r5] + ldfe.sa.nt1 f4 = [r5], r6 + ldfe.sa.nt1 f4 = [r5], 205 + ldfe.sa.nta f4 = [r5] + ldfe.sa.nta f4 = [r5], r6 + ldfe.sa.nta f4 = [r5], 218 + + ldfe.c.clr f4 = [r5] + ldfe.c.clr f4 = [r5], r6 + ldfe.c.clr f4 = [r5], 231 + ldfe.c.clr.nt1 f4 = [r5] + ldfe.c.clr.nt1 f4 = [r5], r6 + ldfe.c.clr.nt1 f4 = [r5], 244 + ldfe.c.clr.nta f4 = [r5] + ldfe.c.clr.nta f4 = [r5], r6 + ldfe.c.clr.nta f4 = [r5], -255 + + ldfe.c.nc f4 = [r5] + ldfe.c.nc f4 = [r5], r6 + ldfe.c.nc f4 = [r5], -242 + ldfe.c.nc.nt1 f4 = [r5] + ldfe.c.nc.nt1 f4 = [r5], r6 + ldfe.c.nc.nt1 f4 = [r5], -229 + ldfe.c.nc.nta f4 = [r5] + ldfe.c.nc.nta f4 = [r5], r6 + ldfe.c.nc.nta f4 = [r5], -216 + + ldf.fill f4 = [r5] + ldf.fill f4 = [r5], r6 + ldf.fill f4 = [r5], -203 + ldf.fill.nt1 f4 = [r5] + ldf.fill.nt1 f4 = [r5], r6 + ldf.fill.nt1 f4 = [r5], -190 + ldf.fill.nta f4 = [r5] + ldf.fill.nta f4 = [r5], r6 + ldf.fill.nta f4 = [r5], -177 + + stfs [r4] = f5 + stfs [r4] = f5, -164 + stfs.nta [r4] = f5 + stfs.nta [r4] = f5, -151 + + stfd [r4] = f5 + stfd [r4] = f5, -138 + stfd.nta [r4] = f5 + stfd.nta [r4] = f5, -125 + + stf8 [r4] = f5 + stf8 [r4] = f5, -112 + stf8.nta [r4] = f5 + stf8.nta [r4] = f5, -99 + + stfe [r4] = f5 + stfe [r4] = f5, -86 + stfe.nta [r4] = f5 + stfe.nta [r4] = f5, -73 + + stf.spill [r4] = f5 + stf.spill [r4] = f5, -60 + stf.spill.nta [r4] = f5 + stf.spill.nta [r4] = f5, -47 + + ldfps f4, f5 = [r5] + ldfps f4, f5 = [r5], 8 + ldfps.nt1 f4, f5 = [r5] + ldfps.nt1 f4, f5 = [r5], 8 + ldfps.nta f4, f5 = [r5] + ldfps.nta f4, f5 = [r5], 8 + + ldfps.s f4, f5 = [r5] + ldfps.s f4, f5 = [r5], 8 + ldfps.s.nt1 f4, f5 = [r5] + ldfps.s.nt1 f4, f5 = [r5], 8 + ldfps.s.nta f4, f5 = [r5] + ldfps.s.nta f4, f5 = [r5], 8 + + ldfps.a f4, f5 = [r5] + ldfps.a f4, f5 = [r5], 8 + ldfps.a.nt1 f4, f5 = [r5] + ldfps.a.nt1 f4, f5 = [r5], 8 + ldfps.a.nta f4, f5 = [r5] + ldfps.a.nta f4, f5 = [r5], 8 + + ldfps.sa f4, f5 = [r5] + ldfps.sa f4, f5 = [r5], 8 + ldfps.sa.nt1 f4, f5 = [r5] + ldfps.sa.nt1 f4, f5 = [r5], 8 + ldfps.sa.nta f4, f5 = [r5] + ldfps.sa.nta f4, f5 = [r5], 8 + + ldfps.c.clr f4, f5 = [r5] + ldfps.c.clr f4, f5 = [r5], 8 + ldfps.c.clr.nt1 f4, f5 = [r5] + ldfps.c.clr.nt1 f4, f5 = [r5], 8 + ldfps.c.clr.nta f4, f5 = [r5] + ldfps.c.clr.nta f4, f5 = [r5], 8 + + ldfps.c.nc f4, f5 = [r5] + ldfps.c.nc f4, f5 = [r5], 8 + ldfps.c.nc.nt1 f4, f5 = [r5] + ldfps.c.nc.nt1 f4, f5 = [r5], 8 + ldfps.c.nc.nta f4, f5 = [r5] + ldfps.c.nc.nta f4, f5 = [r5], 8 + + ldfpd f4, f5 = [r5] + ldfpd f4, f5 = [r5], 16 + ldfpd.nt1 f4, f5 = [r5] + ldfpd.nt1 f4, f5 = [r5], 16 + ldfpd.nta f4, f5 = [r5] + ldfpd.nta f4, f5 = [r5], 16 + + ldfpd.s f4, f5 = [r5] + ldfpd.s f4, f5 = [r5], 16 + ldfpd.s.nt1 f4, f5 = [r5] + ldfpd.s.nt1 f4, f5 = [r5], 16 + ldfpd.s.nta f4, f5 = [r5] + ldfpd.s.nta f4, f5 = [r5], 16 + + ldfpd.a f4, f5 = [r5] + ldfpd.a f4, f5 = [r5], 16 + ldfpd.a.nt1 f4, f5 = [r5] + ldfpd.a.nt1 f4, f5 = [r5], 16 + ldfpd.a.nta f4, f5 = [r5] + ldfpd.a.nta f4, f5 = [r5], 16 + + ldfpd.sa f4, f5 = [r5] + ldfpd.sa f4, f5 = [r5], 16 + ldfpd.sa.nt1 f4, f5 = [r5] + ldfpd.sa.nt1 f4, f5 = [r5], 16 + ldfpd.sa.nta f4, f5 = [r5] + ldfpd.sa.nta f4, f5 = [r5], 16 + + ldfpd.c.clr f4, f5 = [r5] + ldfpd.c.clr f4, f5 = [r5], 16 + ldfpd.c.clr.nt1 f4, f5 = [r5] + ldfpd.c.clr.nt1 f4, f5 = [r5], 16 + ldfpd.c.clr.nta f4, f5 = [r5] + ldfpd.c.clr.nta f4, f5 = [r5], 16 + + ldfpd.c.nc f4, f5 = [r5] + ldfpd.c.nc f4, f5 = [r5], 16 + ldfpd.c.nc.nt1 f4, f5 = [r5] + ldfpd.c.nc.nt1 f4, f5 = [r5], 16 + ldfpd.c.nc.nta f4, f5 = [r5] + ldfpd.c.nc.nta f4, f5 = [r5], 16 + + ldfp8 f4, f5 = [r5] + ldfp8 f4, f5 = [r5], 16 + ldfp8.nt1 f4, f5 = [r5] + ldfp8.nt1 f4, f5 = [r5], 16 + ldfp8.nta f4, f5 = [r5] + ldfp8.nta f4, f5 = [r5], 16 + + ldfp8.s f4, f5 = [r5] + ldfp8.s f4, f5 = [r5], 16 + ldfp8.s.nt1 f4, f5 = [r5] + ldfp8.s.nt1 f4, f5 = [r5], 16 + ldfp8.s.nta f4, f5 = [r5] + ldfp8.s.nta f4, f5 = [r5], 16 + + ldfp8.a f4, f5 = [r5] + ldfp8.a f4, f5 = [r5], 16 + ldfp8.a.nt1 f4, f5 = [r5] + ldfp8.a.nt1 f4, f5 = [r5], 16 + ldfp8.a.nta f4, f5 = [r5] + ldfp8.a.nta f4, f5 = [r5], 16 + + ldfp8.sa f4, f5 = [r5] + ldfp8.sa f4, f5 = [r5], 16 + ldfp8.sa.nt1 f4, f5 = [r5] + ldfp8.sa.nt1 f4, f5 = [r5], 16 + ldfp8.sa.nta f4, f5 = [r5] + ldfp8.sa.nta f4, f5 = [r5], 16 + + ldfp8.c.clr f4, f5 = [r5] + ldfp8.c.clr f4, f5 = [r5], 16 + ldfp8.c.clr.nt1 f4, f5 = [r5] + ldfp8.c.clr.nt1 f4, f5 = [r5], 16 + ldfp8.c.clr.nta f4, f5 = [r5] + ldfp8.c.clr.nta f4, f5 = [r5], 16 + + ldfp8.c.nc f4, f5 = [r5] + ldfp8.c.nc f4, f5 = [r5], 16 + ldfp8.c.nc.nt1 f4, f5 = [r5] + ldfp8.c.nc.nt1 f4, f5 = [r5], 16 + ldfp8.c.nc.nta f4, f5 = [r5] + ldfp8.c.nc.nta f4, f5 = [r5], 16 + + lfetch [r4] + lfetch [r4], r5 + lfetch [r4], -34 + lfetch.nt1 [r4] + lfetch.nt1 [r4], r5 + lfetch.nt1 [r4], -21 + lfetch.nt2 [r4] + lfetch.nt2 [r4], r5 + lfetch.nt2 [r4], -8 + lfetch.nta [r4] + lfetch.nta [r4], r5 + lfetch.nta [r4], 5 + + lfetch.fault [r4] + lfetch.fault [r4], r5 + lfetch.fault [r4], 18 + lfetch.fault.nt1 [r4] + lfetch.fault.nt1 [r4], r5 + lfetch.fault.nt1 [r4], 31 + lfetch.fault.nt2 [r4] + lfetch.fault.nt2 [r4], r5 + lfetch.fault.nt2 [r4], 44 + lfetch.fault.nta [r4] + lfetch.fault.nta [r4], r5 + lfetch.fault.nta [r4], 57 + + lfetch.excl [r4] + lfetch.excl [r4], r5 + lfetch.excl [r4], 70 + lfetch.excl.nt1 [r4] + lfetch.excl.nt1 [r4], r5 + lfetch.excl.nt1 [r4], 83 + lfetch.excl.nt2 [r4] + lfetch.excl.nt2 [r4], r5 + lfetch.excl.nt2 [r4], 96 + lfetch.excl.nta [r4] + lfetch.excl.nta [r4], r5 + lfetch.excl.nta [r4], 109 + + lfetch.fault.excl [r4] + lfetch.fault.excl [r4], r5 + lfetch.fault.excl [r4], 122 + lfetch.fault.excl.nt1 [r4] + lfetch.fault.excl.nt1 [r4], r5 + lfetch.fault.excl.nt1 [r4], 135 + lfetch.fault.excl.nt2 [r4] + lfetch.fault.excl.nt2 [r4], r5 + lfetch.fault.excl.nt2 [r4], 148 + lfetch.fault.excl.nta [r4] + lfetch.fault.excl.nta [r4], r5 + lfetch.fault.excl.nta [r4], 161 + + cmpxchg1.acq r4 = [r5], r6, ar.ccv + cmpxchg1.acq.nt1 r4 = [r5], r6, ar.ccv + cmpxchg1.acq.nta r4 = [r5], r6, ar.ccv + + cmpxchg1.rel r4 = [r5], r6, ar.ccv + cmpxchg1.rel.nt1 r4 = [r5], r6, ar.ccv + cmpxchg1.rel.nta r4 = [r5], r6, ar.ccv + + cmpxchg2.acq r4 = [r5], r6, ar.ccv + cmpxchg2.acq.nt1 r4 = [r5], r6, ar.ccv + cmpxchg2.acq.nta r4 = [r5], r6, ar.ccv + + cmpxchg2.rel r4 = [r5], r6, ar.ccv + cmpxchg2.rel.nt1 r4 = [r5], r6, ar.ccv + cmpxchg2.rel.nta r4 = [r5], r6, ar.ccv + + cmpxchg4.acq r4 = [r5], r6, ar.ccv + cmpxchg4.acq.nt1 r4 = [r5], r6, ar.ccv + cmpxchg4.acq.nta r4 = [r5], r6, ar.ccv + + cmpxchg4.rel r4 = [r5], r6, ar.ccv + cmpxchg4.rel.nt1 r4 = [r5], r6, ar.ccv + cmpxchg4.rel.nta r4 = [r5], r6, ar.ccv + + cmpxchg8.acq r4 = [r5], r6, ar.ccv + cmpxchg8.acq.nt1 r4 = [r5], r6, ar.ccv + cmpxchg8.acq.nta r4 = [r5], r6, ar.ccv + + cmpxchg8.rel r4 = [r5], r6, ar.ccv + cmpxchg8.rel.nt1 r4 = [r5], r6, ar.ccv + cmpxchg8.rel.nta r4 = [r5], r6, ar.ccv + + xchg1 r4 = [r5], r6 + xchg1.nt1 r4 = [r5], r6 + xchg1.nta r4 = [r5], r6 + + xchg2 r4 = [r5], r6 + xchg2.nt1 r4 = [r5], r6 + xchg2.nta r4 = [r5], r6 + + xchg4 r4 = [r5], r6 + xchg4.nt1 r4 = [r5], r6 + xchg4.nta r4 = [r5], r6 + + xchg8 r4 = [r5], r6 + xchg8.nt1 r4 = [r5], r6 + xchg8.nta r4 = [r5], r6 + + fetchadd4.acq r4 = [r5], -16 + fetchadd4.acq.nt1 r4 = [r5], -8 + fetchadd4.acq.nta r4 = [r5], -4 + + fetchadd8.acq r4 = [r5], -1 + fetchadd8.acq.nt1 r4 = [r5], 1 + fetchadd8.acq.nta r4 = [r5], 4 + + fetchadd4.rel r4 = [r5], 8 + fetchadd4.rel.nt1 r4 = [r5], 16 + fetchadd4.rel.nta r4 = [r5], -16 + + fetchadd8.rel r4 = [r5], -8 + fetchadd8.rel.nt1 r4 = [r5], -4 + fetchadd8.rel.nta r4 = [r5], -1 + + setf.sig f4 = r5 + setf.exp f4 = r5 + setf.s f4 = r5 + setf.d f4 = r5 + + getf.sig r4 = f5 + getf.exp r4 = f5 + getf.s r4 = f5 + getf.d r4 = f5 + + chk.s.m r4, _start + chk.s f4, _start + chk.a.nc r4, _start + chk.a.clr r4, _start + chk.a.nc f4, _start + chk.a.clr f4, _start + + invala + fwb + mf + mf.a + srlz.d + srlz.i + sync.i + nop.m 0 + nop.i 0;; + + { .mii; alloc r4 = ar.pfs, 2, 10, 16, 16;; } + + { .mii; flushrs;; } + { .mii; loadrs } + + invala.e r4 + invala.e f4 + + fc r4 + ptc.e r4 + + break.m 0 + break.m 0x1ffff + + nop.m 0 + break.m 0x1ffff + + probe.r r4 = r5, r6 + probe.w r4 = r5, r6 + + probe.r r4 = r5, 0 + probe.w r4 = r5, 1 + + probe.r.fault r3, 2 + probe.w.fault r3, 3 + probe.rw.fault r3, 0 + + { .mmi; itc.d r8;; nop.m 0x0; nop.i 0x0;; } + itc.i r9;; + + sum 0x1234 + rum 0x5aaaaa + ssm 0xffffff + rsm 0x400000 + + ptc.l r4, r5 + { .mmi; ptc.g r4, r5;; nop.m 0x0; nop.i 0x0 } + { .mmi; ptc.ga r4, r5;; nop.m 0x0; nop.i 0x0 } + ptr.d r4, r5 + ptr.i r4, r5 + + thash r4 = r5 + ttag r4 = r5 + tpa r4 = r5 + tak r4 = r5 + diff --git a/gas/testsuite/gas/ia64/opc-x.d b/gas/testsuite/gas/ia64/opc-x.d new file mode 100644 index 0000000..10d82fd --- /dev/null +++ b/gas/testsuite/gas/ia64/opc-x.d @@ -0,0 +1,29 @@ +#objdump: -d +#name: ia64 opc-x + +.*: +file format .* + +Disassembly of section .text: + +0000000000000000 <_start>: + 0: 04 00 00 00 01 00 \[MLX\] nop\.m 0x0 + ... + e: 00 00 04 00 break\.x 0x0 + 12: 00 00 01 c0 ff ff \[MLX\] nop\.m 0x0 + 18: ff ff 7f e0 ff ff break\.x 0x3fffffffffffffff + 1e: 01 08 04 00 + 22: 00 00 01 00 00 00 \[MLX\] nop\.m 0x0 + 28: 00 00 00 00 00 00 nop\.x 0x0 + 2e: 04 00 04 00 + 32: 00 00 01 c0 ff ff \[MLX\] nop\.m 0x0 + 38: ff ff 7f e0 ff ff nop\.x 0x3fffffffffffffff + 3e: 05 08 04 00 + 42: 00 00 01 00 00 00 \[MLX\] nop\.m 0x0 + 48: 00 00 00 80 00 00 movl r4=0x0 + 4e: 00 60 04 00 + 52: 00 00 01 c0 ff ff \[MLX\] nop\.m 0x0 + 58: ff ff 7f 80 f0 f7 movl r4=0xffffffffffffffff + 5e: ff 6f 05 00 + 62: 00 00 01 80 90 78 \[MLX\] nop\.m 0x0 + 68: 56 34 12 80 f0 76 movl r4=0x1234567890abcdef;; + 6e: 6d 66 00 00 diff --git a/gas/testsuite/gas/ia64/opc-x.s b/gas/testsuite/gas/ia64/opc-x.s new file mode 100644 index 0000000..ec1f5f2 --- /dev/null +++ b/gas/testsuite/gas/ia64/opc-x.s @@ -0,0 +1,14 @@ +.text + .type _start,@function +_start: + + break.x 0 + break.x 0x3fffffffffffffff + + nop.x 0 + nop.x 0x3fffffffffffffff + + movl r4 = 0 + movl r4 = 0xffffffffffffffff + movl r4 = 0x1234567890abcdef + diff --git a/gas/testsuite/gas/ia64/regs.d b/gas/testsuite/gas/ia64/regs.d new file mode 100644 index 0000000..4687b68 --- /dev/null +++ b/gas/testsuite/gas/ia64/regs.d @@ -0,0 +1,2333 @@ +#objdump: -d +#name: ia64 regs + +.*: +file format .* + +Disassembly of section \.text: + +0000000000000000 <_start>: + 0: 01 08 00 00 00 21 \[MII\] mov r1=r0 + 6: 00 00 00 02 00 00 nop\.i 0x0 + c: 00 00 04 00 nop\.i 0x0;; + 10: 01 10 00 00 00 21 \[MII\] mov r2=r0 + 16: 00 00 00 02 00 00 nop\.i 0x0 + 1c: 00 00 04 00 nop\.i 0x0;; + 20: 01 18 00 00 00 21 \[MII\] mov r3=r0 + 26: 00 00 00 02 00 00 nop\.i 0x0 + 2c: 00 00 04 00 nop\.i 0x0;; + 30: 01 20 00 00 00 21 \[MII\] mov r4=r0 + 36: 00 00 00 02 00 00 nop\.i 0x0 + 3c: 00 00 04 00 nop\.i 0x0;; + 40: 01 28 00 00 00 21 \[MII\] mov r5=r0 + 46: 00 00 00 02 00 00 nop\.i 0x0 + 4c: 00 00 04 00 nop\.i 0x0;; + 50: 01 30 00 00 00 21 \[MII\] mov r6=r0 + 56: 00 00 00 02 00 00 nop\.i 0x0 + 5c: 00 00 04 00 nop\.i 0x0;; + 60: 01 38 00 00 00 21 \[MII\] mov r7=r0 + 66: 00 00 00 02 00 00 nop\.i 0x0 + 6c: 00 00 04 00 nop\.i 0x0;; + 70: 01 40 00 00 00 21 \[MII\] mov r8=r0 + 76: 00 00 00 02 00 00 nop\.i 0x0 + 7c: 00 00 04 00 nop\.i 0x0;; + 80: 01 48 00 00 00 21 \[MII\] mov r9=r0 + 86: 00 00 00 02 00 00 nop\.i 0x0 + 8c: 00 00 04 00 nop\.i 0x0;; + 90: 01 50 00 00 00 21 \[MII\] mov r10=r0 + 96: 00 00 00 02 00 00 nop\.i 0x0 + 9c: 00 00 04 00 nop\.i 0x0;; + a0: 01 58 00 00 00 21 \[MII\] mov r11=r0 + a6: 00 00 00 02 00 00 nop\.i 0x0 + ac: 00 00 04 00 nop\.i 0x0;; + b0: 01 60 00 00 00 21 \[MII\] mov r12=r0 + b6: 00 00 00 02 00 00 nop\.i 0x0 + bc: 00 00 04 00 nop\.i 0x0;; + c0: 01 68 00 00 00 21 \[MII\] mov r13=r0 + c6: 00 00 00 02 00 00 nop\.i 0x0 + cc: 00 00 04 00 nop\.i 0x0;; + d0: 01 70 00 00 00 21 \[MII\] mov r14=r0 + d6: 00 00 00 02 00 00 nop\.i 0x0 + dc: 00 00 04 00 nop\.i 0x0;; + e0: 01 78 00 00 00 21 \[MII\] mov r15=r0 + e6: 00 00 00 02 00 00 nop\.i 0x0 + ec: 00 00 04 00 nop\.i 0x0;; + f0: 01 80 00 00 00 21 \[MII\] mov r16=r0 + f6: 00 00 00 02 00 00 nop\.i 0x0 + fc: 00 00 04 00 nop\.i 0x0;; + 100: 01 88 00 00 00 21 \[MII\] mov r17=r0 + 106: 00 00 00 02 00 00 nop\.i 0x0 + 10c: 00 00 04 00 nop\.i 0x0;; + 110: 01 90 00 00 00 21 \[MII\] mov r18=r0 + 116: 00 00 00 02 00 00 nop\.i 0x0 + 11c: 00 00 04 00 nop\.i 0x0;; + 120: 01 98 00 00 00 21 \[MII\] mov r19=r0 + 126: 00 00 00 02 00 00 nop\.i 0x0 + 12c: 00 00 04 00 nop\.i 0x0;; + 130: 01 a0 00 00 00 21 \[MII\] mov r20=r0 + 136: 00 00 00 02 00 00 nop\.i 0x0 + 13c: 00 00 04 00 nop\.i 0x0;; + 140: 01 a8 00 00 00 21 \[MII\] mov r21=r0 + 146: 00 00 00 02 00 00 nop\.i 0x0 + 14c: 00 00 04 00 nop\.i 0x0;; + 150: 01 b0 00 00 00 21 \[MII\] mov r22=r0 + 156: 00 00 00 02 00 00 nop\.i 0x0 + 15c: 00 00 04 00 nop\.i 0x0;; + 160: 01 b8 00 00 00 21 \[MII\] mov r23=r0 + 166: 00 00 00 02 00 00 nop\.i 0x0 + 16c: 00 00 04 00 nop\.i 0x0;; + 170: 01 c0 00 00 00 21 \[MII\] mov r24=r0 + 176: 00 00 00 02 00 00 nop\.i 0x0 + 17c: 00 00 04 00 nop\.i 0x0;; + 180: 01 c8 00 00 00 21 \[MII\] mov r25=r0 + 186: 00 00 00 02 00 00 nop\.i 0x0 + 18c: 00 00 04 00 nop\.i 0x0;; + 190: 01 d0 00 00 00 21 \[MII\] mov r26=r0 + 196: 00 00 00 02 00 00 nop\.i 0x0 + 19c: 00 00 04 00 nop\.i 0x0;; + 1a0: 01 d8 00 00 00 21 \[MII\] mov r27=r0 + 1a6: 00 00 00 02 00 00 nop\.i 0x0 + 1ac: 00 00 04 00 nop\.i 0x0;; + 1b0: 01 e0 00 00 00 21 \[MII\] mov r28=r0 + 1b6: 00 00 00 02 00 00 nop\.i 0x0 + 1bc: 00 00 04 00 nop\.i 0x0;; + 1c0: 01 e8 00 00 00 21 \[MII\] mov r29=r0 + 1c6: 00 00 00 02 00 00 nop\.i 0x0 + 1cc: 00 00 04 00 nop\.i 0x0;; + 1d0: 01 f0 00 00 00 21 \[MII\] mov r30=r0 + 1d6: 00 00 00 02 00 00 nop\.i 0x0 + 1dc: 00 00 04 00 nop\.i 0x0;; + 1e0: 01 f8 00 00 00 21 \[MII\] mov r31=r0 + 1e6: 00 00 00 02 00 00 nop\.i 0x0 + 1ec: 00 00 04 00 nop\.i 0x0;; + 1f0: 01 00 01 00 00 21 \[MII\] mov r32=r0 + 1f6: 00 00 00 02 00 00 nop\.i 0x0 + 1fc: 00 00 04 00 nop\.i 0x0;; + 200: 01 08 01 00 00 21 \[MII\] mov r33=r0 + 206: 00 00 00 02 00 00 nop\.i 0x0 + 20c: 00 00 04 00 nop\.i 0x0;; + 210: 01 10 01 00 00 21 \[MII\] mov r34=r0 + 216: 00 00 00 02 00 00 nop\.i 0x0 + 21c: 00 00 04 00 nop\.i 0x0;; + 220: 01 18 01 00 00 21 \[MII\] mov r35=r0 + 226: 00 00 00 02 00 00 nop\.i 0x0 + 22c: 00 00 04 00 nop\.i 0x0;; + 230: 01 20 01 00 00 21 \[MII\] mov r36=r0 + 236: 00 00 00 02 00 00 nop\.i 0x0 + 23c: 00 00 04 00 nop\.i 0x0;; + 240: 01 28 01 00 00 21 \[MII\] mov r37=r0 + 246: 00 00 00 02 00 00 nop\.i 0x0 + 24c: 00 00 04 00 nop\.i 0x0;; + 250: 01 30 01 00 00 21 \[MII\] mov r38=r0 + 256: 00 00 00 02 00 00 nop\.i 0x0 + 25c: 00 00 04 00 nop\.i 0x0;; + 260: 01 38 01 00 00 21 \[MII\] mov r39=r0 + 266: 00 00 00 02 00 00 nop\.i 0x0 + 26c: 00 00 04 00 nop\.i 0x0;; + 270: 01 40 01 00 00 21 \[MII\] mov r40=r0 + 276: 00 00 00 02 00 00 nop\.i 0x0 + 27c: 00 00 04 00 nop\.i 0x0;; + 280: 01 48 01 00 00 21 \[MII\] mov r41=r0 + 286: 00 00 00 02 00 00 nop\.i 0x0 + 28c: 00 00 04 00 nop\.i 0x0;; + 290: 01 50 01 00 00 21 \[MII\] mov r42=r0 + 296: 00 00 00 02 00 00 nop\.i 0x0 + 29c: 00 00 04 00 nop\.i 0x0;; + 2a0: 01 58 01 00 00 21 \[MII\] mov r43=r0 + 2a6: 00 00 00 02 00 00 nop\.i 0x0 + 2ac: 00 00 04 00 nop\.i 0x0;; + 2b0: 01 60 01 00 00 21 \[MII\] mov r44=r0 + 2b6: 00 00 00 02 00 00 nop\.i 0x0 + 2bc: 00 00 04 00 nop\.i 0x0;; + 2c0: 01 68 01 00 00 21 \[MII\] mov r45=r0 + 2c6: 00 00 00 02 00 00 nop\.i 0x0 + 2cc: 00 00 04 00 nop\.i 0x0;; + 2d0: 01 70 01 00 00 21 \[MII\] mov r46=r0 + 2d6: 00 00 00 02 00 00 nop\.i 0x0 + 2dc: 00 00 04 00 nop\.i 0x0;; + 2e0: 01 78 01 00 00 21 \[MII\] mov r47=r0 + 2e6: 00 00 00 02 00 00 nop\.i 0x0 + 2ec: 00 00 04 00 nop\.i 0x0;; + 2f0: 01 80 01 00 00 21 \[MII\] mov r48=r0 + 2f6: 00 00 00 02 00 00 nop\.i 0x0 + 2fc: 00 00 04 00 nop\.i 0x0;; + 300: 01 88 01 00 00 21 \[MII\] mov r49=r0 + 306: 00 00 00 02 00 00 nop\.i 0x0 + 30c: 00 00 04 00 nop\.i 0x0;; + 310: 01 90 01 00 00 21 \[MII\] mov r50=r0 + 316: 00 00 00 02 00 00 nop\.i 0x0 + 31c: 00 00 04 00 nop\.i 0x0;; + 320: 01 98 01 00 00 21 \[MII\] mov r51=r0 + 326: 00 00 00 02 00 00 nop\.i 0x0 + 32c: 00 00 04 00 nop\.i 0x0;; + 330: 01 a0 01 00 00 21 \[MII\] mov r52=r0 + 336: 00 00 00 02 00 00 nop\.i 0x0 + 33c: 00 00 04 00 nop\.i 0x0;; + 340: 01 a8 01 00 00 21 \[MII\] mov r53=r0 + 346: 00 00 00 02 00 00 nop\.i 0x0 + 34c: 00 00 04 00 nop\.i 0x0;; + 350: 01 b0 01 00 00 21 \[MII\] mov r54=r0 + 356: 00 00 00 02 00 00 nop\.i 0x0 + 35c: 00 00 04 00 nop\.i 0x0;; + 360: 01 b8 01 00 00 21 \[MII\] mov r55=r0 + 366: 00 00 00 02 00 00 nop\.i 0x0 + 36c: 00 00 04 00 nop\.i 0x0;; + 370: 01 c0 01 00 00 21 \[MII\] mov r56=r0 + 376: 00 00 00 02 00 00 nop\.i 0x0 + 37c: 00 00 04 00 nop\.i 0x0;; + 380: 01 c8 01 00 00 21 \[MII\] mov r57=r0 + 386: 00 00 00 02 00 00 nop\.i 0x0 + 38c: 00 00 04 00 nop\.i 0x0;; + 390: 01 d0 01 00 00 21 \[MII\] mov r58=r0 + 396: 00 00 00 02 00 00 nop\.i 0x0 + 39c: 00 00 04 00 nop\.i 0x0;; + 3a0: 01 d8 01 00 00 21 \[MII\] mov r59=r0 + 3a6: 00 00 00 02 00 00 nop\.i 0x0 + 3ac: 00 00 04 00 nop\.i 0x0;; + 3b0: 01 e0 01 00 00 21 \[MII\] mov r60=r0 + 3b6: 00 00 00 02 00 00 nop\.i 0x0 + 3bc: 00 00 04 00 nop\.i 0x0;; + 3c0: 01 e8 01 00 00 21 \[MII\] mov r61=r0 + 3c6: 00 00 00 02 00 00 nop\.i 0x0 + 3cc: 00 00 04 00 nop\.i 0x0;; + 3d0: 01 f0 01 00 00 21 \[MII\] mov r62=r0 + 3d6: 00 00 00 02 00 00 nop\.i 0x0 + 3dc: 00 00 04 00 nop\.i 0x0;; + 3e0: 01 f8 01 00 00 21 \[MII\] mov r63=r0 + 3e6: 00 00 00 02 00 00 nop\.i 0x0 + 3ec: 00 00 04 00 nop\.i 0x0;; + 3f0: 01 00 02 00 00 21 \[MII\] mov r64=r0 + 3f6: 00 00 00 02 00 00 nop\.i 0x0 + 3fc: 00 00 04 00 nop\.i 0x0;; + 400: 01 08 02 00 00 21 \[MII\] mov r65=r0 + 406: 00 00 00 02 00 00 nop\.i 0x0 + 40c: 00 00 04 00 nop\.i 0x0;; + 410: 01 10 02 00 00 21 \[MII\] mov r66=r0 + 416: 00 00 00 02 00 00 nop\.i 0x0 + 41c: 00 00 04 00 nop\.i 0x0;; + 420: 01 18 02 00 00 21 \[MII\] mov r67=r0 + 426: 00 00 00 02 00 00 nop\.i 0x0 + 42c: 00 00 04 00 nop\.i 0x0;; + 430: 01 20 02 00 00 21 \[MII\] mov r68=r0 + 436: 00 00 00 02 00 00 nop\.i 0x0 + 43c: 00 00 04 00 nop\.i 0x0;; + 440: 01 28 02 00 00 21 \[MII\] mov r69=r0 + 446: 00 00 00 02 00 00 nop\.i 0x0 + 44c: 00 00 04 00 nop\.i 0x0;; + 450: 01 30 02 00 00 21 \[MII\] mov r70=r0 + 456: 00 00 00 02 00 00 nop\.i 0x0 + 45c: 00 00 04 00 nop\.i 0x0;; + 460: 01 38 02 00 00 21 \[MII\] mov r71=r0 + 466: 00 00 00 02 00 00 nop\.i 0x0 + 46c: 00 00 04 00 nop\.i 0x0;; + 470: 01 40 02 00 00 21 \[MII\] mov r72=r0 + 476: 00 00 00 02 00 00 nop\.i 0x0 + 47c: 00 00 04 00 nop\.i 0x0;; + 480: 01 48 02 00 00 21 \[MII\] mov r73=r0 + 486: 00 00 00 02 00 00 nop\.i 0x0 + 48c: 00 00 04 00 nop\.i 0x0;; + 490: 01 50 02 00 00 21 \[MII\] mov r74=r0 + 496: 00 00 00 02 00 00 nop\.i 0x0 + 49c: 00 00 04 00 nop\.i 0x0;; + 4a0: 01 58 02 00 00 21 \[MII\] mov r75=r0 + 4a6: 00 00 00 02 00 00 nop\.i 0x0 + 4ac: 00 00 04 00 nop\.i 0x0;; + 4b0: 01 60 02 00 00 21 \[MII\] mov r76=r0 + 4b6: 00 00 00 02 00 00 nop\.i 0x0 + 4bc: 00 00 04 00 nop\.i 0x0;; + 4c0: 01 68 02 00 00 21 \[MII\] mov r77=r0 + 4c6: 00 00 00 02 00 00 nop\.i 0x0 + 4cc: 00 00 04 00 nop\.i 0x0;; + 4d0: 01 70 02 00 00 21 \[MII\] mov r78=r0 + 4d6: 00 00 00 02 00 00 nop\.i 0x0 + 4dc: 00 00 04 00 nop\.i 0x0;; + 4e0: 01 78 02 00 00 21 \[MII\] mov r79=r0 + 4e6: 00 00 00 02 00 00 nop\.i 0x0 + 4ec: 00 00 04 00 nop\.i 0x0;; + 4f0: 01 80 02 00 00 21 \[MII\] mov r80=r0 + 4f6: 00 00 00 02 00 00 nop\.i 0x0 + 4fc: 00 00 04 00 nop\.i 0x0;; + 500: 01 88 02 00 00 21 \[MII\] mov r81=r0 + 506: 00 00 00 02 00 00 nop\.i 0x0 + 50c: 00 00 04 00 nop\.i 0x0;; + 510: 01 90 02 00 00 21 \[MII\] mov r82=r0 + 516: 00 00 00 02 00 00 nop\.i 0x0 + 51c: 00 00 04 00 nop\.i 0x0;; + 520: 01 98 02 00 00 21 \[MII\] mov r83=r0 + 526: 00 00 00 02 00 00 nop\.i 0x0 + 52c: 00 00 04 00 nop\.i 0x0;; + 530: 01 a0 02 00 00 21 \[MII\] mov r84=r0 + 536: 00 00 00 02 00 00 nop\.i 0x0 + 53c: 00 00 04 00 nop\.i 0x0;; + 540: 01 a8 02 00 00 21 \[MII\] mov r85=r0 + 546: 00 00 00 02 00 00 nop\.i 0x0 + 54c: 00 00 04 00 nop\.i 0x0;; + 550: 01 b0 02 00 00 21 \[MII\] mov r86=r0 + 556: 00 00 00 02 00 00 nop\.i 0x0 + 55c: 00 00 04 00 nop\.i 0x0;; + 560: 01 b8 02 00 00 21 \[MII\] mov r87=r0 + 566: 00 00 00 02 00 00 nop\.i 0x0 + 56c: 00 00 04 00 nop\.i 0x0;; + 570: 01 c0 02 00 00 21 \[MII\] mov r88=r0 + 576: 00 00 00 02 00 00 nop\.i 0x0 + 57c: 00 00 04 00 nop\.i 0x0;; + 580: 01 c8 02 00 00 21 \[MII\] mov r89=r0 + 586: 00 00 00 02 00 00 nop\.i 0x0 + 58c: 00 00 04 00 nop\.i 0x0;; + 590: 01 d0 02 00 00 21 \[MII\] mov r90=r0 + 596: 00 00 00 02 00 00 nop\.i 0x0 + 59c: 00 00 04 00 nop\.i 0x0;; + 5a0: 01 d8 02 00 00 21 \[MII\] mov r91=r0 + 5a6: 00 00 00 02 00 00 nop\.i 0x0 + 5ac: 00 00 04 00 nop\.i 0x0;; + 5b0: 01 e0 02 00 00 21 \[MII\] mov r92=r0 + 5b6: 00 00 00 02 00 00 nop\.i 0x0 + 5bc: 00 00 04 00 nop\.i 0x0;; + 5c0: 01 e8 02 00 00 21 \[MII\] mov r93=r0 + 5c6: 00 00 00 02 00 00 nop\.i 0x0 + 5cc: 00 00 04 00 nop\.i 0x0;; + 5d0: 01 f0 02 00 00 21 \[MII\] mov r94=r0 + 5d6: 00 00 00 02 00 00 nop\.i 0x0 + 5dc: 00 00 04 00 nop\.i 0x0;; + 5e0: 01 f8 02 00 00 21 \[MII\] mov r95=r0 + 5e6: 00 00 00 02 00 00 nop\.i 0x0 + 5ec: 00 00 04 00 nop\.i 0x0;; + 5f0: 01 00 03 00 00 21 \[MII\] mov r96=r0 + 5f6: 00 00 00 02 00 00 nop\.i 0x0 + 5fc: 00 00 04 00 nop\.i 0x0;; + 600: 01 08 03 00 00 21 \[MII\] mov r97=r0 + 606: 00 00 00 02 00 00 nop\.i 0x0 + 60c: 00 00 04 00 nop\.i 0x0;; + 610: 01 10 03 00 00 21 \[MII\] mov r98=r0 + 616: 00 00 00 02 00 00 nop\.i 0x0 + 61c: 00 00 04 00 nop\.i 0x0;; + 620: 01 18 03 00 00 21 \[MII\] mov r99=r0 + 626: 00 00 00 02 00 00 nop\.i 0x0 + 62c: 00 00 04 00 nop\.i 0x0;; + 630: 01 20 03 00 00 21 \[MII\] mov r100=r0 + 636: 00 00 00 02 00 00 nop\.i 0x0 + 63c: 00 00 04 00 nop\.i 0x0;; + 640: 01 28 03 00 00 21 \[MII\] mov r101=r0 + 646: 00 00 00 02 00 00 nop\.i 0x0 + 64c: 00 00 04 00 nop\.i 0x0;; + 650: 01 30 03 00 00 21 \[MII\] mov r102=r0 + 656: 00 00 00 02 00 00 nop\.i 0x0 + 65c: 00 00 04 00 nop\.i 0x0;; + 660: 01 38 03 00 00 21 \[MII\] mov r103=r0 + 666: 00 00 00 02 00 00 nop\.i 0x0 + 66c: 00 00 04 00 nop\.i 0x0;; + 670: 01 40 03 00 00 21 \[MII\] mov r104=r0 + 676: 00 00 00 02 00 00 nop\.i 0x0 + 67c: 00 00 04 00 nop\.i 0x0;; + 680: 01 48 03 00 00 21 \[MII\] mov r105=r0 + 686: 00 00 00 02 00 00 nop\.i 0x0 + 68c: 00 00 04 00 nop\.i 0x0;; + 690: 01 50 03 00 00 21 \[MII\] mov r106=r0 + 696: 00 00 00 02 00 00 nop\.i 0x0 + 69c: 00 00 04 00 nop\.i 0x0;; + 6a0: 01 58 03 00 00 21 \[MII\] mov r107=r0 + 6a6: 00 00 00 02 00 00 nop\.i 0x0 + 6ac: 00 00 04 00 nop\.i 0x0;; + 6b0: 01 60 03 00 00 21 \[MII\] mov r108=r0 + 6b6: 00 00 00 02 00 00 nop\.i 0x0 + 6bc: 00 00 04 00 nop\.i 0x0;; + 6c0: 01 68 03 00 00 21 \[MII\] mov r109=r0 + 6c6: 00 00 00 02 00 00 nop\.i 0x0 + 6cc: 00 00 04 00 nop\.i 0x0;; + 6d0: 01 70 03 00 00 21 \[MII\] mov r110=r0 + 6d6: 00 00 00 02 00 00 nop\.i 0x0 + 6dc: 00 00 04 00 nop\.i 0x0;; + 6e0: 01 78 03 00 00 21 \[MII\] mov r111=r0 + 6e6: 00 00 00 02 00 00 nop\.i 0x0 + 6ec: 00 00 04 00 nop\.i 0x0;; + 6f0: 01 80 03 00 00 21 \[MII\] mov r112=r0 + 6f6: 00 00 00 02 00 00 nop\.i 0x0 + 6fc: 00 00 04 00 nop\.i 0x0;; + 700: 01 88 03 00 00 21 \[MII\] mov r113=r0 + 706: 00 00 00 02 00 00 nop\.i 0x0 + 70c: 00 00 04 00 nop\.i 0x0;; + 710: 01 90 03 00 00 21 \[MII\] mov r114=r0 + 716: 00 00 00 02 00 00 nop\.i 0x0 + 71c: 00 00 04 00 nop\.i 0x0;; + 720: 01 98 03 00 00 21 \[MII\] mov r115=r0 + 726: 00 00 00 02 00 00 nop\.i 0x0 + 72c: 00 00 04 00 nop\.i 0x0;; + 730: 01 a0 03 00 00 21 \[MII\] mov r116=r0 + 736: 00 00 00 02 00 00 nop\.i 0x0 + 73c: 00 00 04 00 nop\.i 0x0;; + 740: 01 a8 03 00 00 21 \[MII\] mov r117=r0 + 746: 00 00 00 02 00 00 nop\.i 0x0 + 74c: 00 00 04 00 nop\.i 0x0;; + 750: 01 b0 03 00 00 21 \[MII\] mov r118=r0 + 756: 00 00 00 02 00 00 nop\.i 0x0 + 75c: 00 00 04 00 nop\.i 0x0;; + 760: 01 b8 03 00 00 21 \[MII\] mov r119=r0 + 766: 00 00 00 02 00 00 nop\.i 0x0 + 76c: 00 00 04 00 nop\.i 0x0;; + 770: 01 c0 03 00 00 21 \[MII\] mov r120=r0 + 776: 00 00 00 02 00 00 nop\.i 0x0 + 77c: 00 00 04 00 nop\.i 0x0;; + 780: 01 c8 03 00 00 21 \[MII\] mov r121=r0 + 786: 00 00 00 02 00 00 nop\.i 0x0 + 78c: 00 00 04 00 nop\.i 0x0;; + 790: 01 d0 03 00 00 21 \[MII\] mov r122=r0 + 796: 00 00 00 02 00 00 nop\.i 0x0 + 79c: 00 00 04 00 nop\.i 0x0;; + 7a0: 01 d8 03 00 00 21 \[MII\] mov r123=r0 + 7a6: 00 00 00 02 00 00 nop\.i 0x0 + 7ac: 00 00 04 00 nop\.i 0x0;; + 7b0: 01 e0 03 00 00 21 \[MII\] mov r124=r0 + 7b6: 00 00 00 02 00 00 nop\.i 0x0 + 7bc: 00 00 04 00 nop\.i 0x0;; + 7c0: 01 e8 03 00 00 21 \[MII\] mov r125=r0 + 7c6: 00 00 00 02 00 00 nop\.i 0x0 + 7cc: 00 00 04 00 nop\.i 0x0;; + 7d0: 01 f0 03 00 00 21 \[MII\] mov r126=r0 + 7d6: 00 00 00 02 00 00 nop\.i 0x0 + 7dc: 00 00 04 00 nop\.i 0x0;; + 7e0: 01 f8 03 00 00 21 \[MII\] mov r127=r0 + 7e6: 00 00 00 02 00 00 nop\.i 0x0 + 7ec: 00 00 04 00 nop\.i 0x0;; + 7f0: 01 00 01 00 00 21 \[MII\] mov r32=r0 + 7f6: 00 00 00 02 00 00 nop\.i 0x0 + 7fc: 00 00 04 00 nop\.i 0x0;; + 800: 01 08 01 00 00 21 \[MII\] mov r33=r0 + 806: 00 00 00 02 00 00 nop\.i 0x0 + 80c: 00 00 04 00 nop\.i 0x0;; + 810: 01 10 01 00 00 21 \[MII\] mov r34=r0 + 816: 00 00 00 02 00 00 nop\.i 0x0 + 81c: 00 00 04 00 nop\.i 0x0;; + 820: 01 18 01 00 00 21 \[MII\] mov r35=r0 + 826: 00 00 00 02 00 00 nop\.i 0x0 + 82c: 00 00 04 00 nop\.i 0x0;; + 830: 01 20 01 00 00 21 \[MII\] mov r36=r0 + 836: 00 00 00 02 00 00 nop\.i 0x0 + 83c: 00 00 04 00 nop\.i 0x0;; + 840: 01 28 01 00 00 21 \[MII\] mov r37=r0 + 846: 00 00 00 02 00 00 nop\.i 0x0 + 84c: 00 00 04 00 nop\.i 0x0;; + 850: 01 30 01 00 00 21 \[MII\] mov r38=r0 + 856: 00 00 00 02 00 00 nop\.i 0x0 + 85c: 00 00 04 00 nop\.i 0x0;; + 860: 01 38 01 00 00 21 \[MII\] mov r39=r0 + 866: 00 00 00 02 00 00 nop\.i 0x0 + 86c: 00 00 04 00 nop\.i 0x0;; + 870: 01 40 01 00 00 21 \[MII\] mov r40=r0 + 876: 00 00 00 02 00 00 nop\.i 0x0 + 87c: 00 00 04 00 nop\.i 0x0;; + 880: 01 48 01 00 00 21 \[MII\] mov r41=r0 + 886: 00 00 00 02 00 00 nop\.i 0x0 + 88c: 00 00 04 00 nop\.i 0x0;; + 890: 01 50 01 00 00 21 \[MII\] mov r42=r0 + 896: 00 00 00 02 00 00 nop\.i 0x0 + 89c: 00 00 04 00 nop\.i 0x0;; + 8a0: 01 58 01 00 00 21 \[MII\] mov r43=r0 + 8a6: 00 00 00 02 00 00 nop\.i 0x0 + 8ac: 00 00 04 00 nop\.i 0x0;; + 8b0: 01 60 01 00 00 21 \[MII\] mov r44=r0 + 8b6: 00 00 00 02 00 00 nop\.i 0x0 + 8bc: 00 00 04 00 nop\.i 0x0;; + 8c0: 01 68 01 00 00 21 \[MII\] mov r45=r0 + 8c6: 00 00 00 02 00 00 nop\.i 0x0 + 8cc: 00 00 04 00 nop\.i 0x0;; + 8d0: 01 70 01 00 00 21 \[MII\] mov r46=r0 + 8d6: 00 00 00 02 00 00 nop\.i 0x0 + 8dc: 00 00 04 00 nop\.i 0x0;; + 8e0: 01 78 01 00 00 21 \[MII\] mov r47=r0 + 8e6: 00 00 00 02 00 00 nop\.i 0x0 + 8ec: 00 00 04 00 nop\.i 0x0;; + 8f0: 01 80 01 00 00 21 \[MII\] mov r48=r0 + 8f6: 00 00 00 02 00 00 nop\.i 0x0 + 8fc: 00 00 04 00 nop\.i 0x0;; + 900: 01 88 01 00 00 21 \[MII\] mov r49=r0 + 906: 00 00 00 02 00 00 nop\.i 0x0 + 90c: 00 00 04 00 nop\.i 0x0;; + 910: 01 90 01 00 00 21 \[MII\] mov r50=r0 + 916: 00 00 00 02 00 00 nop\.i 0x0 + 91c: 00 00 04 00 nop\.i 0x0;; + 920: 01 98 01 00 00 21 \[MII\] mov r51=r0 + 926: 00 00 00 02 00 00 nop\.i 0x0 + 92c: 00 00 04 00 nop\.i 0x0;; + 930: 01 a0 01 00 00 21 \[MII\] mov r52=r0 + 936: 00 00 00 02 00 00 nop\.i 0x0 + 93c: 00 00 04 00 nop\.i 0x0;; + 940: 01 a8 01 00 00 21 \[MII\] mov r53=r0 + 946: 00 00 00 02 00 00 nop\.i 0x0 + 94c: 00 00 04 00 nop\.i 0x0;; + 950: 01 b0 01 00 00 21 \[MII\] mov r54=r0 + 956: 00 00 00 02 00 00 nop\.i 0x0 + 95c: 00 00 04 00 nop\.i 0x0;; + 960: 01 b8 01 00 00 21 \[MII\] mov r55=r0 + 966: 00 00 00 02 00 00 nop\.i 0x0 + 96c: 00 00 04 00 nop\.i 0x0;; + 970: 01 c0 01 00 00 21 \[MII\] mov r56=r0 + 976: 00 00 00 02 00 00 nop\.i 0x0 + 97c: 00 00 04 00 nop\.i 0x0;; + 980: 01 c8 01 00 00 21 \[MII\] mov r57=r0 + 986: 00 00 00 02 00 00 nop\.i 0x0 + 98c: 00 00 04 00 nop\.i 0x0;; + 990: 01 d0 01 00 00 21 \[MII\] mov r58=r0 + 996: 00 00 00 02 00 00 nop\.i 0x0 + 99c: 00 00 04 00 nop\.i 0x0;; + 9a0: 01 d8 01 00 00 21 \[MII\] mov r59=r0 + 9a6: 00 00 00 02 00 00 nop\.i 0x0 + 9ac: 00 00 04 00 nop\.i 0x0;; + 9b0: 01 e0 01 00 00 21 \[MII\] mov r60=r0 + 9b6: 00 00 00 02 00 00 nop\.i 0x0 + 9bc: 00 00 04 00 nop\.i 0x0;; + 9c0: 01 e8 01 00 00 21 \[MII\] mov r61=r0 + 9c6: 00 00 00 02 00 00 nop\.i 0x0 + 9cc: 00 00 04 00 nop\.i 0x0;; + 9d0: 01 f0 01 00 00 21 \[MII\] mov r62=r0 + 9d6: 00 00 00 02 00 00 nop\.i 0x0 + 9dc: 00 00 04 00 nop\.i 0x0;; + 9e0: 01 f8 01 00 00 21 \[MII\] mov r63=r0 + 9e6: 00 00 00 02 00 00 nop\.i 0x0 + 9ec: 00 00 04 00 nop\.i 0x0;; + 9f0: 01 00 02 00 00 21 \[MII\] mov r64=r0 + 9f6: 00 00 00 02 00 00 nop\.i 0x0 + 9fc: 00 00 04 00 nop\.i 0x0;; + a00: 01 08 02 00 00 21 \[MII\] mov r65=r0 + a06: 00 00 00 02 00 00 nop\.i 0x0 + a0c: 00 00 04 00 nop\.i 0x0;; + a10: 01 10 02 00 00 21 \[MII\] mov r66=r0 + a16: 00 00 00 02 00 00 nop\.i 0x0 + a1c: 00 00 04 00 nop\.i 0x0;; + a20: 01 18 02 00 00 21 \[MII\] mov r67=r0 + a26: 00 00 00 02 00 00 nop\.i 0x0 + a2c: 00 00 04 00 nop\.i 0x0;; + a30: 01 20 02 00 00 21 \[MII\] mov r68=r0 + a36: 00 00 00 02 00 00 nop\.i 0x0 + a3c: 00 00 04 00 nop\.i 0x0;; + a40: 01 28 02 00 00 21 \[MII\] mov r69=r0 + a46: 00 00 00 02 00 00 nop\.i 0x0 + a4c: 00 00 04 00 nop\.i 0x0;; + a50: 01 30 02 00 00 21 \[MII\] mov r70=r0 + a56: 00 00 00 02 00 00 nop\.i 0x0 + a5c: 00 00 04 00 nop\.i 0x0;; + a60: 01 38 02 00 00 21 \[MII\] mov r71=r0 + a66: 00 00 00 02 00 00 nop\.i 0x0 + a6c: 00 00 04 00 nop\.i 0x0;; + a70: 01 40 02 00 00 21 \[MII\] mov r72=r0 + a76: 00 00 00 02 00 00 nop\.i 0x0 + a7c: 00 00 04 00 nop\.i 0x0;; + a80: 01 48 02 00 00 21 \[MII\] mov r73=r0 + a86: 00 00 00 02 00 00 nop\.i 0x0 + a8c: 00 00 04 00 nop\.i 0x0;; + a90: 01 50 02 00 00 21 \[MII\] mov r74=r0 + a96: 00 00 00 02 00 00 nop\.i 0x0 + a9c: 00 00 04 00 nop\.i 0x0;; + aa0: 01 58 02 00 00 21 \[MII\] mov r75=r0 + aa6: 00 00 00 02 00 00 nop\.i 0x0 + aac: 00 00 04 00 nop\.i 0x0;; + ab0: 01 60 02 00 00 21 \[MII\] mov r76=r0 + ab6: 00 00 00 02 00 00 nop\.i 0x0 + abc: 00 00 04 00 nop\.i 0x0;; + ac0: 01 68 02 00 00 21 \[MII\] mov r77=r0 + ac6: 00 00 00 02 00 00 nop\.i 0x0 + acc: 00 00 04 00 nop\.i 0x0;; + ad0: 01 70 02 00 00 21 \[MII\] mov r78=r0 + ad6: 00 00 00 02 00 00 nop\.i 0x0 + adc: 00 00 04 00 nop\.i 0x0;; + ae0: 01 78 02 00 00 21 \[MII\] mov r79=r0 + ae6: 00 00 00 02 00 00 nop\.i 0x0 + aec: 00 00 04 00 nop\.i 0x0;; + af0: 01 80 02 00 00 21 \[MII\] mov r80=r0 + af6: 00 00 00 02 00 00 nop\.i 0x0 + afc: 00 00 04 00 nop\.i 0x0;; + b00: 01 88 02 00 00 21 \[MII\] mov r81=r0 + b06: 00 00 00 02 00 00 nop\.i 0x0 + b0c: 00 00 04 00 nop\.i 0x0;; + b10: 01 90 02 00 00 21 \[MII\] mov r82=r0 + b16: 00 00 00 02 00 00 nop\.i 0x0 + b1c: 00 00 04 00 nop\.i 0x0;; + b20: 01 98 02 00 00 21 \[MII\] mov r83=r0 + b26: 00 00 00 02 00 00 nop\.i 0x0 + b2c: 00 00 04 00 nop\.i 0x0;; + b30: 01 a0 02 00 00 21 \[MII\] mov r84=r0 + b36: 00 00 00 02 00 00 nop\.i 0x0 + b3c: 00 00 04 00 nop\.i 0x0;; + b40: 01 a8 02 00 00 21 \[MII\] mov r85=r0 + b46: 00 00 00 02 00 00 nop\.i 0x0 + b4c: 00 00 04 00 nop\.i 0x0;; + b50: 01 b0 02 00 00 21 \[MII\] mov r86=r0 + b56: 00 00 00 02 00 00 nop\.i 0x0 + b5c: 00 00 04 00 nop\.i 0x0;; + b60: 01 b8 02 00 00 21 \[MII\] mov r87=r0 + b66: 00 00 00 02 00 00 nop\.i 0x0 + b6c: 00 00 04 00 nop\.i 0x0;; + b70: 01 c0 02 00 00 21 \[MII\] mov r88=r0 + b76: 00 00 00 02 00 00 nop\.i 0x0 + b7c: 00 00 04 00 nop\.i 0x0;; + b80: 01 c8 02 00 00 21 \[MII\] mov r89=r0 + b86: 00 00 00 02 00 00 nop\.i 0x0 + b8c: 00 00 04 00 nop\.i 0x0;; + b90: 01 d0 02 00 00 21 \[MII\] mov r90=r0 + b96: 00 00 00 02 00 00 nop\.i 0x0 + b9c: 00 00 04 00 nop\.i 0x0;; + ba0: 01 d8 02 00 00 21 \[MII\] mov r91=r0 + ba6: 00 00 00 02 00 00 nop\.i 0x0 + bac: 00 00 04 00 nop\.i 0x0;; + bb0: 01 e0 02 00 00 21 \[MII\] mov r92=r0 + bb6: 00 00 00 02 00 00 nop\.i 0x0 + bbc: 00 00 04 00 nop\.i 0x0;; + bc0: 01 e8 02 00 00 21 \[MII\] mov r93=r0 + bc6: 00 00 00 02 00 00 nop\.i 0x0 + bcc: 00 00 04 00 nop\.i 0x0;; + bd0: 01 f0 02 00 00 21 \[MII\] mov r94=r0 + bd6: 00 00 00 02 00 00 nop\.i 0x0 + bdc: 00 00 04 00 nop\.i 0x0;; + be0: 01 f8 02 00 00 21 \[MII\] mov r95=r0 + be6: 00 00 00 02 00 00 nop\.i 0x0 + bec: 00 00 04 00 nop\.i 0x0;; + bf0: 01 00 03 00 00 21 \[MII\] mov r96=r0 + bf6: 00 00 00 02 00 00 nop\.i 0x0 + bfc: 00 00 04 00 nop\.i 0x0;; + c00: 01 08 03 00 00 21 \[MII\] mov r97=r0 + c06: 00 00 00 02 00 00 nop\.i 0x0 + c0c: 00 00 04 00 nop\.i 0x0;; + c10: 01 10 03 00 00 21 \[MII\] mov r98=r0 + c16: 00 00 00 02 00 00 nop\.i 0x0 + c1c: 00 00 04 00 nop\.i 0x0;; + c20: 01 18 03 00 00 21 \[MII\] mov r99=r0 + c26: 00 00 00 02 00 00 nop\.i 0x0 + c2c: 00 00 04 00 nop\.i 0x0;; + c30: 01 20 03 00 00 21 \[MII\] mov r100=r0 + c36: 00 00 00 02 00 00 nop\.i 0x0 + c3c: 00 00 04 00 nop\.i 0x0;; + c40: 01 28 03 00 00 21 \[MII\] mov r101=r0 + c46: 00 00 00 02 00 00 nop\.i 0x0 + c4c: 00 00 04 00 nop\.i 0x0;; + c50: 01 30 03 00 00 21 \[MII\] mov r102=r0 + c56: 00 00 00 02 00 00 nop\.i 0x0 + c5c: 00 00 04 00 nop\.i 0x0;; + c60: 01 38 03 00 00 21 \[MII\] mov r103=r0 + c66: 00 00 00 02 00 00 nop\.i 0x0 + c6c: 00 00 04 00 nop\.i 0x0;; + c70: 01 40 03 00 00 21 \[MII\] mov r104=r0 + c76: 00 00 00 02 00 00 nop\.i 0x0 + c7c: 00 00 04 00 nop\.i 0x0;; + c80: 01 48 03 00 00 21 \[MII\] mov r105=r0 + c86: 00 00 00 02 00 00 nop\.i 0x0 + c8c: 00 00 04 00 nop\.i 0x0;; + c90: 01 50 03 00 00 21 \[MII\] mov r106=r0 + c96: 00 00 00 02 00 00 nop\.i 0x0 + c9c: 00 00 04 00 nop\.i 0x0;; + ca0: 01 58 03 00 00 21 \[MII\] mov r107=r0 + ca6: 00 00 00 02 00 00 nop\.i 0x0 + cac: 00 00 04 00 nop\.i 0x0;; + cb0: 01 60 03 00 00 21 \[MII\] mov r108=r0 + cb6: 00 00 00 02 00 00 nop\.i 0x0 + cbc: 00 00 04 00 nop\.i 0x0;; + cc0: 01 68 03 00 00 21 \[MII\] mov r109=r0 + cc6: 00 00 00 02 00 00 nop\.i 0x0 + ccc: 00 00 04 00 nop\.i 0x0;; + cd0: 01 70 03 00 00 21 \[MII\] mov r110=r0 + cd6: 00 00 00 02 00 00 nop\.i 0x0 + cdc: 00 00 04 00 nop\.i 0x0;; + ce0: 01 78 03 00 00 21 \[MII\] mov r111=r0 + ce6: 00 00 00 02 00 00 nop\.i 0x0 + cec: 00 00 04 00 nop\.i 0x0;; + cf0: 01 80 03 00 00 21 \[MII\] mov r112=r0 + cf6: 00 00 00 02 00 00 nop\.i 0x0 + cfc: 00 00 04 00 nop\.i 0x0;; + d00: 01 88 03 00 00 21 \[MII\] mov r113=r0 + d06: 00 00 00 02 00 00 nop\.i 0x0 + d0c: 00 00 04 00 nop\.i 0x0;; + d10: 01 90 03 00 00 21 \[MII\] mov r114=r0 + d16: 00 00 00 02 00 00 nop\.i 0x0 + d1c: 00 00 04 00 nop\.i 0x0;; + d20: 01 98 03 00 00 21 \[MII\] mov r115=r0 + d26: 00 00 00 02 00 00 nop\.i 0x0 + d2c: 00 00 04 00 nop\.i 0x0;; + d30: 01 a0 03 00 00 21 \[MII\] mov r116=r0 + d36: 00 00 00 02 00 00 nop\.i 0x0 + d3c: 00 00 04 00 nop\.i 0x0;; + d40: 01 a8 03 00 00 21 \[MII\] mov r117=r0 + d46: 00 00 00 02 00 00 nop\.i 0x0 + d4c: 00 00 04 00 nop\.i 0x0;; + d50: 01 b0 03 00 00 21 \[MII\] mov r118=r0 + d56: 00 00 00 02 00 00 nop\.i 0x0 + d5c: 00 00 04 00 nop\.i 0x0;; + d60: 01 b8 03 00 00 21 \[MII\] mov r119=r0 + d66: 00 00 00 02 00 00 nop\.i 0x0 + d6c: 00 00 04 00 nop\.i 0x0;; + d70: 01 c0 03 00 00 21 \[MII\] mov r120=r0 + d76: 00 00 00 02 00 00 nop\.i 0x0 + d7c: 00 00 04 00 nop\.i 0x0;; + d80: 01 c8 03 00 00 21 \[MII\] mov r121=r0 + d86: 00 00 00 02 00 00 nop\.i 0x0 + d8c: 00 00 04 00 nop\.i 0x0;; + d90: 01 d0 03 00 00 21 \[MII\] mov r122=r0 + d96: 00 00 00 02 00 00 nop\.i 0x0 + d9c: 00 00 04 00 nop\.i 0x0;; + da0: 01 d8 03 00 00 21 \[MII\] mov r123=r0 + da6: 00 00 00 02 00 00 nop\.i 0x0 + dac: 00 00 04 00 nop\.i 0x0;; + db0: 01 e0 03 00 00 21 \[MII\] mov r124=r0 + db6: 00 00 00 02 00 00 nop\.i 0x0 + dbc: 00 00 04 00 nop\.i 0x0;; + dc0: 01 e8 03 00 00 21 \[MII\] mov r125=r0 + dc6: 00 00 00 02 00 00 nop\.i 0x0 + dcc: 00 00 04 00 nop\.i 0x0;; + dd0: 01 f0 03 00 00 21 \[MII\] mov r126=r0 + dd6: 00 00 00 02 00 00 nop\.i 0x0 + ddc: 00 00 04 00 nop\.i 0x0;; + de0: 01 f8 03 00 00 21 \[MII\] mov r127=r0 + de6: 00 00 00 02 00 00 nop\.i 0x0 + dec: 00 00 04 00 nop\.i 0x0;; + df0: 01 00 01 00 00 21 \[MII\] mov r32=r0 + df6: 00 00 00 02 00 00 nop\.i 0x0 + dfc: 00 00 04 00 nop\.i 0x0;; + e00: 01 08 01 00 00 21 \[MII\] mov r33=r0 + e06: 00 00 00 02 00 00 nop\.i 0x0 + e0c: 00 00 04 00 nop\.i 0x0;; + e10: 01 10 01 00 00 21 \[MII\] mov r34=r0 + e16: 00 00 00 02 00 00 nop\.i 0x0 + e1c: 00 00 04 00 nop\.i 0x0;; + e20: 01 18 01 00 00 21 \[MII\] mov r35=r0 + e26: 00 00 00 02 00 00 nop\.i 0x0 + e2c: 00 00 04 00 nop\.i 0x0;; + e30: 01 20 01 00 00 21 \[MII\] mov r36=r0 + e36: 00 00 00 02 00 00 nop\.i 0x0 + e3c: 00 00 04 00 nop\.i 0x0;; + e40: 01 28 01 00 00 21 \[MII\] mov r37=r0 + e46: 00 00 00 02 00 00 nop\.i 0x0 + e4c: 00 00 04 00 nop\.i 0x0;; + e50: 01 30 01 00 00 21 \[MII\] mov r38=r0 + e56: 00 00 00 02 00 00 nop\.i 0x0 + e5c: 00 00 04 00 nop\.i 0x0;; + e60: 01 38 01 00 00 21 \[MII\] mov r39=r0 + e66: 00 00 00 02 00 00 nop\.i 0x0 + e6c: 00 00 04 00 nop\.i 0x0;; + e70: 01 40 01 00 00 21 \[MII\] mov r40=r0 + e76: 00 00 00 02 00 00 nop\.i 0x0 + e7c: 00 00 04 00 nop\.i 0x0;; + e80: 01 48 01 00 00 21 \[MII\] mov r41=r0 + e86: 00 00 00 02 00 00 nop\.i 0x0 + e8c: 00 00 04 00 nop\.i 0x0;; + e90: 01 50 01 00 00 21 \[MII\] mov r42=r0 + e96: 00 00 00 02 00 00 nop\.i 0x0 + e9c: 00 00 04 00 nop\.i 0x0;; + ea0: 01 58 01 00 00 21 \[MII\] mov r43=r0 + ea6: 00 00 00 02 00 00 nop\.i 0x0 + eac: 00 00 04 00 nop\.i 0x0;; + eb0: 01 60 01 00 00 21 \[MII\] mov r44=r0 + eb6: 00 00 00 02 00 00 nop\.i 0x0 + ebc: 00 00 04 00 nop\.i 0x0;; + ec0: 01 68 01 00 00 21 \[MII\] mov r45=r0 + ec6: 00 00 00 02 00 00 nop\.i 0x0 + ecc: 00 00 04 00 nop\.i 0x0;; + ed0: 01 70 01 00 00 21 \[MII\] mov r46=r0 + ed6: 00 00 00 02 00 00 nop\.i 0x0 + edc: 00 00 04 00 nop\.i 0x0;; + ee0: 01 78 01 00 00 21 \[MII\] mov r47=r0 + ee6: 00 00 00 02 00 00 nop\.i 0x0 + eec: 00 00 04 00 nop\.i 0x0;; + ef0: 01 80 01 00 00 21 \[MII\] mov r48=r0 + ef6: 00 00 00 02 00 00 nop\.i 0x0 + efc: 00 00 04 00 nop\.i 0x0;; + f00: 01 88 01 00 00 21 \[MII\] mov r49=r0 + f06: 00 00 00 02 00 00 nop\.i 0x0 + f0c: 00 00 04 00 nop\.i 0x0;; + f10: 01 90 01 00 00 21 \[MII\] mov r50=r0 + f16: 00 00 00 02 00 00 nop\.i 0x0 + f1c: 00 00 04 00 nop\.i 0x0;; + f20: 01 98 01 00 00 21 \[MII\] mov r51=r0 + f26: 00 00 00 02 00 00 nop\.i 0x0 + f2c: 00 00 04 00 nop\.i 0x0;; + f30: 01 a0 01 00 00 21 \[MII\] mov r52=r0 + f36: 00 00 00 02 00 00 nop\.i 0x0 + f3c: 00 00 04 00 nop\.i 0x0;; + f40: 01 a8 01 00 00 21 \[MII\] mov r53=r0 + f46: 00 00 00 02 00 00 nop\.i 0x0 + f4c: 00 00 04 00 nop\.i 0x0;; + f50: 01 b0 01 00 00 21 \[MII\] mov r54=r0 + f56: 00 00 00 02 00 00 nop\.i 0x0 + f5c: 00 00 04 00 nop\.i 0x0;; + f60: 01 b8 01 00 00 21 \[MII\] mov r55=r0 + f66: 00 00 00 02 00 00 nop\.i 0x0 + f6c: 00 00 04 00 nop\.i 0x0;; + f70: 01 c0 01 00 00 21 \[MII\] mov r56=r0 + f76: 00 00 00 02 00 00 nop\.i 0x0 + f7c: 00 00 04 00 nop\.i 0x0;; + f80: 01 c8 01 00 00 21 \[MII\] mov r57=r0 + f86: 00 00 00 02 00 00 nop\.i 0x0 + f8c: 00 00 04 00 nop\.i 0x0;; + f90: 01 d0 01 00 00 21 \[MII\] mov r58=r0 + f96: 00 00 00 02 00 00 nop\.i 0x0 + f9c: 00 00 04 00 nop\.i 0x0;; + fa0: 01 d8 01 00 00 21 \[MII\] mov r59=r0 + fa6: 00 00 00 02 00 00 nop\.i 0x0 + fac: 00 00 04 00 nop\.i 0x0;; + fb0: 01 e0 01 00 00 21 \[MII\] mov r60=r0 + fb6: 00 00 00 02 00 00 nop\.i 0x0 + fbc: 00 00 04 00 nop\.i 0x0;; + fc0: 01 e8 01 00 00 21 \[MII\] mov r61=r0 + fc6: 00 00 00 02 00 00 nop\.i 0x0 + fcc: 00 00 04 00 nop\.i 0x0;; + fd0: 01 f0 01 00 00 21 \[MII\] mov r62=r0 + fd6: 00 00 00 02 00 00 nop\.i 0x0 + fdc: 00 00 04 00 nop\.i 0x0;; + fe0: 01 f8 01 00 00 21 \[MII\] mov r63=r0 + fe6: 00 00 00 02 00 00 nop\.i 0x0 + fec: 00 00 04 00 nop\.i 0x0;; + ff0: 01 00 02 00 00 21 \[MII\] mov r64=r0 + ff6: 00 00 00 02 00 00 nop\.i 0x0 + ffc: 00 00 04 00 nop\.i 0x0;; + 1000: 01 08 02 00 00 21 \[MII\] mov r65=r0 + 1006: 00 00 00 02 00 00 nop\.i 0x0 + 100c: 00 00 04 00 nop\.i 0x0;; + 1010: 01 10 02 00 00 21 \[MII\] mov r66=r0 + 1016: 00 00 00 02 00 00 nop\.i 0x0 + 101c: 00 00 04 00 nop\.i 0x0;; + 1020: 01 18 02 00 00 21 \[MII\] mov r67=r0 + 1026: 00 00 00 02 00 00 nop\.i 0x0 + 102c: 00 00 04 00 nop\.i 0x0;; + 1030: 01 20 02 00 00 21 \[MII\] mov r68=r0 + 1036: 00 00 00 02 00 00 nop\.i 0x0 + 103c: 00 00 04 00 nop\.i 0x0;; + 1040: 01 28 02 00 00 21 \[MII\] mov r69=r0 + 1046: 00 00 00 02 00 00 nop\.i 0x0 + 104c: 00 00 04 00 nop\.i 0x0;; + 1050: 01 30 02 00 00 21 \[MII\] mov r70=r0 + 1056: 00 00 00 02 00 00 nop\.i 0x0 + 105c: 00 00 04 00 nop\.i 0x0;; + 1060: 01 38 02 00 00 21 \[MII\] mov r71=r0 + 1066: 00 00 00 02 00 00 nop\.i 0x0 + 106c: 00 00 04 00 nop\.i 0x0;; + 1070: 01 40 02 00 00 21 \[MII\] mov r72=r0 + 1076: 00 00 00 02 00 00 nop\.i 0x0 + 107c: 00 00 04 00 nop\.i 0x0;; + 1080: 01 48 02 00 00 21 \[MII\] mov r73=r0 + 1086: 00 00 00 02 00 00 nop\.i 0x0 + 108c: 00 00 04 00 nop\.i 0x0;; + 1090: 01 50 02 00 00 21 \[MII\] mov r74=r0 + 1096: 00 00 00 02 00 00 nop\.i 0x0 + 109c: 00 00 04 00 nop\.i 0x0;; + 10a0: 01 58 02 00 00 21 \[MII\] mov r75=r0 + 10a6: 00 00 00 02 00 00 nop\.i 0x0 + 10ac: 00 00 04 00 nop\.i 0x0;; + 10b0: 01 60 02 00 00 21 \[MII\] mov r76=r0 + 10b6: 00 00 00 02 00 00 nop\.i 0x0 + 10bc: 00 00 04 00 nop\.i 0x0;; + 10c0: 01 68 02 00 00 21 \[MII\] mov r77=r0 + 10c6: 00 00 00 02 00 00 nop\.i 0x0 + 10cc: 00 00 04 00 nop\.i 0x0;; + 10d0: 01 70 02 00 00 21 \[MII\] mov r78=r0 + 10d6: 00 00 00 02 00 00 nop\.i 0x0 + 10dc: 00 00 04 00 nop\.i 0x0;; + 10e0: 01 78 02 00 00 21 \[MII\] mov r79=r0 + 10e6: 00 00 00 02 00 00 nop\.i 0x0 + 10ec: 00 00 04 00 nop\.i 0x0;; + 10f0: 01 80 02 00 00 21 \[MII\] mov r80=r0 + 10f6: 00 00 00 02 00 00 nop\.i 0x0 + 10fc: 00 00 04 00 nop\.i 0x0;; + 1100: 01 88 02 00 00 21 \[MII\] mov r81=r0 + 1106: 00 00 00 02 00 00 nop\.i 0x0 + 110c: 00 00 04 00 nop\.i 0x0;; + 1110: 01 90 02 00 00 21 \[MII\] mov r82=r0 + 1116: 00 00 00 02 00 00 nop\.i 0x0 + 111c: 00 00 04 00 nop\.i 0x0;; + 1120: 01 98 02 00 00 21 \[MII\] mov r83=r0 + 1126: 00 00 00 02 00 00 nop\.i 0x0 + 112c: 00 00 04 00 nop\.i 0x0;; + 1130: 01 a0 02 00 00 21 \[MII\] mov r84=r0 + 1136: 00 00 00 02 00 00 nop\.i 0x0 + 113c: 00 00 04 00 nop\.i 0x0;; + 1140: 01 a8 02 00 00 21 \[MII\] mov r85=r0 + 1146: 00 00 00 02 00 00 nop\.i 0x0 + 114c: 00 00 04 00 nop\.i 0x0;; + 1150: 01 b0 02 00 00 21 \[MII\] mov r86=r0 + 1156: 00 00 00 02 00 00 nop\.i 0x0 + 115c: 00 00 04 00 nop\.i 0x0;; + 1160: 01 b8 02 00 00 21 \[MII\] mov r87=r0 + 1166: 00 00 00 02 00 00 nop\.i 0x0 + 116c: 00 00 04 00 nop\.i 0x0;; + 1170: 01 c0 02 00 00 21 \[MII\] mov r88=r0 + 1176: 00 00 00 02 00 00 nop\.i 0x0 + 117c: 00 00 04 00 nop\.i 0x0;; + 1180: 01 c8 02 00 00 21 \[MII\] mov r89=r0 + 1186: 00 00 00 02 00 00 nop\.i 0x0 + 118c: 00 00 04 00 nop\.i 0x0;; + 1190: 01 d0 02 00 00 21 \[MII\] mov r90=r0 + 1196: 00 00 00 02 00 00 nop\.i 0x0 + 119c: 00 00 04 00 nop\.i 0x0;; + 11a0: 01 d8 02 00 00 21 \[MII\] mov r91=r0 + 11a6: 00 00 00 02 00 00 nop\.i 0x0 + 11ac: 00 00 04 00 nop\.i 0x0;; + 11b0: 01 e0 02 00 00 21 \[MII\] mov r92=r0 + 11b6: 00 00 00 02 00 00 nop\.i 0x0 + 11bc: 00 00 04 00 nop\.i 0x0;; + 11c0: 01 e8 02 00 00 21 \[MII\] mov r93=r0 + 11c6: 00 00 00 02 00 00 nop\.i 0x0 + 11cc: 00 00 04 00 nop\.i 0x0;; + 11d0: 01 f0 02 00 00 21 \[MII\] mov r94=r0 + 11d6: 00 00 00 02 00 00 nop\.i 0x0 + 11dc: 00 00 04 00 nop\.i 0x0;; + 11e0: 01 f8 02 00 00 21 \[MII\] mov r95=r0 + 11e6: 00 00 00 02 00 00 nop\.i 0x0 + 11ec: 00 00 04 00 nop\.i 0x0;; + 11f0: 01 00 03 00 00 21 \[MII\] mov r96=r0 + 11f6: 00 00 00 02 00 00 nop\.i 0x0 + 11fc: 00 00 04 00 nop\.i 0x0;; + 1200: 01 08 03 00 00 21 \[MII\] mov r97=r0 + 1206: 00 00 00 02 00 00 nop\.i 0x0 + 120c: 00 00 04 00 nop\.i 0x0;; + 1210: 01 10 03 00 00 21 \[MII\] mov r98=r0 + 1216: 00 00 00 02 00 00 nop\.i 0x0 + 121c: 00 00 04 00 nop\.i 0x0;; + 1220: 01 18 03 00 00 21 \[MII\] mov r99=r0 + 1226: 00 00 00 02 00 00 nop\.i 0x0 + 122c: 00 00 04 00 nop\.i 0x0;; + 1230: 01 20 03 00 00 21 \[MII\] mov r100=r0 + 1236: 00 00 00 02 00 00 nop\.i 0x0 + 123c: 00 00 04 00 nop\.i 0x0;; + 1240: 01 28 03 00 00 21 \[MII\] mov r101=r0 + 1246: 00 00 00 02 00 00 nop\.i 0x0 + 124c: 00 00 04 00 nop\.i 0x0;; + 1250: 01 30 03 00 00 21 \[MII\] mov r102=r0 + 1256: 00 00 00 02 00 00 nop\.i 0x0 + 125c: 00 00 04 00 nop\.i 0x0;; + 1260: 01 38 03 00 00 21 \[MII\] mov r103=r0 + 1266: 00 00 00 02 00 00 nop\.i 0x0 + 126c: 00 00 04 00 nop\.i 0x0;; + 1270: 01 40 03 00 00 21 \[MII\] mov r104=r0 + 1276: 00 00 00 02 00 00 nop\.i 0x0 + 127c: 00 00 04 00 nop\.i 0x0;; + 1280: 01 48 03 00 00 21 \[MII\] mov r105=r0 + 1286: 00 00 00 02 00 00 nop\.i 0x0 + 128c: 00 00 04 00 nop\.i 0x0;; + 1290: 01 50 03 00 00 21 \[MII\] mov r106=r0 + 1296: 00 00 00 02 00 00 nop\.i 0x0 + 129c: 00 00 04 00 nop\.i 0x0;; + 12a0: 01 58 03 00 00 21 \[MII\] mov r107=r0 + 12a6: 00 00 00 02 00 00 nop\.i 0x0 + 12ac: 00 00 04 00 nop\.i 0x0;; + 12b0: 01 60 03 00 00 21 \[MII\] mov r108=r0 + 12b6: 00 00 00 02 00 00 nop\.i 0x0 + 12bc: 00 00 04 00 nop\.i 0x0;; + 12c0: 01 68 03 00 00 21 \[MII\] mov r109=r0 + 12c6: 00 00 00 02 00 00 nop\.i 0x0 + 12cc: 00 00 04 00 nop\.i 0x0;; + 12d0: 01 70 03 00 00 21 \[MII\] mov r110=r0 + 12d6: 00 00 00 02 00 00 nop\.i 0x0 + 12dc: 00 00 04 00 nop\.i 0x0;; + 12e0: 01 78 03 00 00 21 \[MII\] mov r111=r0 + 12e6: 00 00 00 02 00 00 nop\.i 0x0 + 12ec: 00 00 04 00 nop\.i 0x0;; + 12f0: 01 80 03 00 00 21 \[MII\] mov r112=r0 + 12f6: 00 00 00 02 00 00 nop\.i 0x0 + 12fc: 00 00 04 00 nop\.i 0x0;; + 1300: 01 88 03 00 00 21 \[MII\] mov r113=r0 + 1306: 00 00 00 02 00 00 nop\.i 0x0 + 130c: 00 00 04 00 nop\.i 0x0;; + 1310: 01 90 03 00 00 21 \[MII\] mov r114=r0 + 1316: 00 00 00 02 00 00 nop\.i 0x0 + 131c: 00 00 04 00 nop\.i 0x0;; + 1320: 01 98 03 00 00 21 \[MII\] mov r115=r0 + 1326: 00 00 00 02 00 00 nop\.i 0x0 + 132c: 00 00 04 00 nop\.i 0x0;; + 1330: 01 a0 03 00 00 21 \[MII\] mov r116=r0 + 1336: 00 00 00 02 00 00 nop\.i 0x0 + 133c: 00 00 04 00 nop\.i 0x0;; + 1340: 01 a8 03 00 00 21 \[MII\] mov r117=r0 + 1346: 00 00 00 02 00 00 nop\.i 0x0 + 134c: 00 00 04 00 nop\.i 0x0;; + 1350: 01 b0 03 00 00 21 \[MII\] mov r118=r0 + 1356: 00 00 00 02 00 00 nop\.i 0x0 + 135c: 00 00 04 00 nop\.i 0x0;; + 1360: 01 b8 03 00 00 21 \[MII\] mov r119=r0 + 1366: 00 00 00 02 00 00 nop\.i 0x0 + 136c: 00 00 04 00 nop\.i 0x0;; + 1370: 01 c0 03 00 00 21 \[MII\] mov r120=r0 + 1376: 00 00 00 02 00 00 nop\.i 0x0 + 137c: 00 00 04 00 nop\.i 0x0;; + 1380: 01 c8 03 00 00 21 \[MII\] mov r121=r0 + 1386: 00 00 00 02 00 00 nop\.i 0x0 + 138c: 00 00 04 00 nop\.i 0x0;; + 1390: 01 d0 03 00 00 21 \[MII\] mov r122=r0 + 1396: 00 00 00 02 00 00 nop\.i 0x0 + 139c: 00 00 04 00 nop\.i 0x0;; + 13a0: 01 d8 03 00 00 21 \[MII\] mov r123=r0 + 13a6: 00 00 00 02 00 00 nop\.i 0x0 + 13ac: 00 00 04 00 nop\.i 0x0;; + 13b0: 01 e0 03 00 00 21 \[MII\] mov r124=r0 + 13b6: 00 00 00 02 00 00 nop\.i 0x0 + 13bc: 00 00 04 00 nop\.i 0x0;; + 13c0: 01 e8 03 00 00 21 \[MII\] mov r125=r0 + 13c6: 00 00 00 02 00 00 nop\.i 0x0 + 13cc: 00 00 04 00 nop\.i 0x0;; + 13d0: 01 f0 03 00 00 21 \[MII\] mov r126=r0 + 13d6: 00 00 00 02 00 00 nop\.i 0x0 + 13dc: 00 00 04 00 nop\.i 0x0;; + 13e0: 01 f8 03 00 00 21 \[MII\] mov r127=r0 + 13e6: 00 00 00 02 00 00 nop\.i 0x0 + 13ec: 00 00 04 00 nop\.i 0x0;; + 13f0: 01 00 01 00 00 21 \[MII\] mov r32=r0 + 13f6: 00 00 00 02 00 00 nop\.i 0x0 + 13fc: 00 00 04 00 nop\.i 0x0;; + 1400: 01 08 01 00 00 21 \[MII\] mov r33=r0 + 1406: 00 00 00 02 00 00 nop\.i 0x0 + 140c: 00 00 04 00 nop\.i 0x0;; + 1410: 01 10 01 00 00 21 \[MII\] mov r34=r0 + 1416: 00 00 00 02 00 00 nop\.i 0x0 + 141c: 00 00 04 00 nop\.i 0x0;; + 1420: 01 18 01 00 00 21 \[MII\] mov r35=r0 + 1426: 00 00 00 02 00 00 nop\.i 0x0 + 142c: 00 00 04 00 nop\.i 0x0;; + 1430: 01 20 01 00 00 21 \[MII\] mov r36=r0 + 1436: 00 00 00 02 00 00 nop\.i 0x0 + 143c: 00 00 04 00 nop\.i 0x0;; + 1440: 01 28 01 00 00 21 \[MII\] mov r37=r0 + 1446: 00 00 00 02 00 00 nop\.i 0x0 + 144c: 00 00 04 00 nop\.i 0x0;; + 1450: 01 30 01 00 00 21 \[MII\] mov r38=r0 + 1456: 00 00 00 02 00 00 nop\.i 0x0 + 145c: 00 00 04 00 nop\.i 0x0;; + 1460: 01 38 01 00 00 21 \[MII\] mov r39=r0 + 1466: 00 00 00 02 00 00 nop\.i 0x0 + 146c: 00 00 04 00 nop\.i 0x0;; + 1470: 01 40 01 00 00 21 \[MII\] mov r40=r0 + 1476: 00 00 00 02 00 00 nop\.i 0x0 + 147c: 00 00 04 00 nop\.i 0x0;; + 1480: 01 48 01 00 00 21 \[MII\] mov r41=r0 + 1486: 00 00 00 02 00 00 nop\.i 0x0 + 148c: 00 00 04 00 nop\.i 0x0;; + 1490: 01 50 01 00 00 21 \[MII\] mov r42=r0 + 1496: 00 00 00 02 00 00 nop\.i 0x0 + 149c: 00 00 04 00 nop\.i 0x0;; + 14a0: 01 58 01 00 00 21 \[MII\] mov r43=r0 + 14a6: 00 00 00 02 00 00 nop\.i 0x0 + 14ac: 00 00 04 00 nop\.i 0x0;; + 14b0: 01 60 01 00 00 21 \[MII\] mov r44=r0 + 14b6: 00 00 00 02 00 00 nop\.i 0x0 + 14bc: 00 00 04 00 nop\.i 0x0;; + 14c0: 01 68 01 00 00 21 \[MII\] mov r45=r0 + 14c6: 00 00 00 02 00 00 nop\.i 0x0 + 14cc: 00 00 04 00 nop\.i 0x0;; + 14d0: 01 70 01 00 00 21 \[MII\] mov r46=r0 + 14d6: 00 00 00 02 00 00 nop\.i 0x0 + 14dc: 00 00 04 00 nop\.i 0x0;; + 14e0: 01 78 01 00 00 21 \[MII\] mov r47=r0 + 14e6: 00 00 00 02 00 00 nop\.i 0x0 + 14ec: 00 00 04 00 nop\.i 0x0;; + 14f0: 01 80 01 00 00 21 \[MII\] mov r48=r0 + 14f6: 00 00 00 02 00 00 nop\.i 0x0 + 14fc: 00 00 04 00 nop\.i 0x0;; + 1500: 01 88 01 00 00 21 \[MII\] mov r49=r0 + 1506: 00 00 00 02 00 00 nop\.i 0x0 + 150c: 00 00 04 00 nop\.i 0x0;; + 1510: 01 90 01 00 00 21 \[MII\] mov r50=r0 + 1516: 00 00 00 02 00 00 nop\.i 0x0 + 151c: 00 00 04 00 nop\.i 0x0;; + 1520: 01 98 01 00 00 21 \[MII\] mov r51=r0 + 1526: 00 00 00 02 00 00 nop\.i 0x0 + 152c: 00 00 04 00 nop\.i 0x0;; + 1530: 01 a0 01 00 00 21 \[MII\] mov r52=r0 + 1536: 00 00 00 02 00 00 nop\.i 0x0 + 153c: 00 00 04 00 nop\.i 0x0;; + 1540: 01 a8 01 00 00 21 \[MII\] mov r53=r0 + 1546: 00 00 00 02 00 00 nop\.i 0x0 + 154c: 00 00 04 00 nop\.i 0x0;; + 1550: 01 b0 01 00 00 21 \[MII\] mov r54=r0 + 1556: 00 00 00 02 00 00 nop\.i 0x0 + 155c: 00 00 04 00 nop\.i 0x0;; + 1560: 01 b8 01 00 00 21 \[MII\] mov r55=r0 + 1566: 00 00 00 02 00 00 nop\.i 0x0 + 156c: 00 00 04 00 nop\.i 0x0;; + 1570: 01 c0 01 00 00 21 \[MII\] mov r56=r0 + 1576: 00 00 00 02 00 00 nop\.i 0x0 + 157c: 00 00 04 00 nop\.i 0x0;; + 1580: 01 c8 01 00 00 21 \[MII\] mov r57=r0 + 1586: 00 00 00 02 00 00 nop\.i 0x0 + 158c: 00 00 04 00 nop\.i 0x0;; + 1590: 01 d0 01 00 00 21 \[MII\] mov r58=r0 + 1596: 00 00 00 02 00 00 nop\.i 0x0 + 159c: 00 00 04 00 nop\.i 0x0;; + 15a0: 01 d8 01 00 00 21 \[MII\] mov r59=r0 + 15a6: 00 00 00 02 00 00 nop\.i 0x0 + 15ac: 00 00 04 00 nop\.i 0x0;; + 15b0: 01 e0 01 00 00 21 \[MII\] mov r60=r0 + 15b6: 00 00 00 02 00 00 nop\.i 0x0 + 15bc: 00 00 04 00 nop\.i 0x0;; + 15c0: 01 e8 01 00 00 21 \[MII\] mov r61=r0 + 15c6: 00 00 00 02 00 00 nop\.i 0x0 + 15cc: 00 00 04 00 nop\.i 0x0;; + 15d0: 01 f0 01 00 00 21 \[MII\] mov r62=r0 + 15d6: 00 00 00 02 00 00 nop\.i 0x0 + 15dc: 00 00 04 00 nop\.i 0x0;; + 15e0: 01 f8 01 00 00 21 \[MII\] mov r63=r0 + 15e6: 00 00 00 02 00 00 nop\.i 0x0 + 15ec: 00 00 04 00 nop\.i 0x0;; + 15f0: 01 00 02 00 00 21 \[MII\] mov r64=r0 + 15f6: 00 00 00 02 00 00 nop\.i 0x0 + 15fc: 00 00 04 00 nop\.i 0x0;; + 1600: 01 08 02 00 00 21 \[MII\] mov r65=r0 + 1606: 00 00 00 02 00 00 nop\.i 0x0 + 160c: 00 00 04 00 nop\.i 0x0;; + 1610: 01 10 02 00 00 21 \[MII\] mov r66=r0 + 1616: 00 00 00 02 00 00 nop\.i 0x0 + 161c: 00 00 04 00 nop\.i 0x0;; + 1620: 01 18 02 00 00 21 \[MII\] mov r67=r0 + 1626: 00 00 00 02 00 00 nop\.i 0x0 + 162c: 00 00 04 00 nop\.i 0x0;; + 1630: 01 20 02 00 00 21 \[MII\] mov r68=r0 + 1636: 00 00 00 02 00 00 nop\.i 0x0 + 163c: 00 00 04 00 nop\.i 0x0;; + 1640: 01 28 02 00 00 21 \[MII\] mov r69=r0 + 1646: 00 00 00 02 00 00 nop\.i 0x0 + 164c: 00 00 04 00 nop\.i 0x0;; + 1650: 01 30 02 00 00 21 \[MII\] mov r70=r0 + 1656: 00 00 00 02 00 00 nop\.i 0x0 + 165c: 00 00 04 00 nop\.i 0x0;; + 1660: 01 38 02 00 00 21 \[MII\] mov r71=r0 + 1666: 00 00 00 02 00 00 nop\.i 0x0 + 166c: 00 00 04 00 nop\.i 0x0;; + 1670: 01 40 02 00 00 21 \[MII\] mov r72=r0 + 1676: 00 00 00 02 00 00 nop\.i 0x0 + 167c: 00 00 04 00 nop\.i 0x0;; + 1680: 01 48 02 00 00 21 \[MII\] mov r73=r0 + 1686: 00 00 00 02 00 00 nop\.i 0x0 + 168c: 00 00 04 00 nop\.i 0x0;; + 1690: 01 50 02 00 00 21 \[MII\] mov r74=r0 + 1696: 00 00 00 02 00 00 nop\.i 0x0 + 169c: 00 00 04 00 nop\.i 0x0;; + 16a0: 01 58 02 00 00 21 \[MII\] mov r75=r0 + 16a6: 00 00 00 02 00 00 nop\.i 0x0 + 16ac: 00 00 04 00 nop\.i 0x0;; + 16b0: 01 60 02 00 00 21 \[MII\] mov r76=r0 + 16b6: 00 00 00 02 00 00 nop\.i 0x0 + 16bc: 00 00 04 00 nop\.i 0x0;; + 16c0: 01 68 02 00 00 21 \[MII\] mov r77=r0 + 16c6: 00 00 00 02 00 00 nop\.i 0x0 + 16cc: 00 00 04 00 nop\.i 0x0;; + 16d0: 01 70 02 00 00 21 \[MII\] mov r78=r0 + 16d6: 00 00 00 02 00 00 nop\.i 0x0 + 16dc: 00 00 04 00 nop\.i 0x0;; + 16e0: 01 78 02 00 00 21 \[MII\] mov r79=r0 + 16e6: 00 00 00 02 00 00 nop\.i 0x0 + 16ec: 00 00 04 00 nop\.i 0x0;; + 16f0: 01 80 02 00 00 21 \[MII\] mov r80=r0 + 16f6: 00 00 00 02 00 00 nop\.i 0x0 + 16fc: 00 00 04 00 nop\.i 0x0;; + 1700: 01 88 02 00 00 21 \[MII\] mov r81=r0 + 1706: 00 00 00 02 00 00 nop\.i 0x0 + 170c: 00 00 04 00 nop\.i 0x0;; + 1710: 01 90 02 00 00 21 \[MII\] mov r82=r0 + 1716: 00 00 00 02 00 00 nop\.i 0x0 + 171c: 00 00 04 00 nop\.i 0x0;; + 1720: 01 98 02 00 00 21 \[MII\] mov r83=r0 + 1726: 00 00 00 02 00 00 nop\.i 0x0 + 172c: 00 00 04 00 nop\.i 0x0;; + 1730: 01 a0 02 00 00 21 \[MII\] mov r84=r0 + 1736: 00 00 00 02 00 00 nop\.i 0x0 + 173c: 00 00 04 00 nop\.i 0x0;; + 1740: 01 a8 02 00 00 21 \[MII\] mov r85=r0 + 1746: 00 00 00 02 00 00 nop\.i 0x0 + 174c: 00 00 04 00 nop\.i 0x0;; + 1750: 01 b0 02 00 00 21 \[MII\] mov r86=r0 + 1756: 00 00 00 02 00 00 nop\.i 0x0 + 175c: 00 00 04 00 nop\.i 0x0;; + 1760: 01 b8 02 00 00 21 \[MII\] mov r87=r0 + 1766: 00 00 00 02 00 00 nop\.i 0x0 + 176c: 00 00 04 00 nop\.i 0x0;; + 1770: 01 c0 02 00 00 21 \[MII\] mov r88=r0 + 1776: 00 00 00 02 00 00 nop\.i 0x0 + 177c: 00 00 04 00 nop\.i 0x0;; + 1780: 01 c8 02 00 00 21 \[MII\] mov r89=r0 + 1786: 00 00 00 02 00 00 nop\.i 0x0 + 178c: 00 00 04 00 nop\.i 0x0;; + 1790: 01 d0 02 00 00 21 \[MII\] mov r90=r0 + 1796: 00 00 00 02 00 00 nop\.i 0x0 + 179c: 00 00 04 00 nop\.i 0x0;; + 17a0: 01 d8 02 00 00 21 \[MII\] mov r91=r0 + 17a6: 00 00 00 02 00 00 nop\.i 0x0 + 17ac: 00 00 04 00 nop\.i 0x0;; + 17b0: 01 e0 02 00 00 21 \[MII\] mov r92=r0 + 17b6: 00 00 00 02 00 00 nop\.i 0x0 + 17bc: 00 00 04 00 nop\.i 0x0;; + 17c0: 01 e8 02 00 00 21 \[MII\] mov r93=r0 + 17c6: 00 00 00 02 00 00 nop\.i 0x0 + 17cc: 00 00 04 00 nop\.i 0x0;; + 17d0: 01 f0 02 00 00 21 \[MII\] mov r94=r0 + 17d6: 00 00 00 02 00 00 nop\.i 0x0 + 17dc: 00 00 04 00 nop\.i 0x0;; + 17e0: 01 f8 02 00 00 21 \[MII\] mov r95=r0 + 17e6: 00 00 00 02 00 00 nop\.i 0x0 + 17ec: 00 00 04 00 nop\.i 0x0;; + 17f0: 01 00 03 00 00 21 \[MII\] mov r96=r0 + 17f6: 00 00 00 02 00 00 nop\.i 0x0 + 17fc: 00 00 04 00 nop\.i 0x0;; + 1800: 01 08 03 00 00 21 \[MII\] mov r97=r0 + 1806: 00 00 00 02 00 00 nop\.i 0x0 + 180c: 00 00 04 00 nop\.i 0x0;; + 1810: 01 10 03 00 00 21 \[MII\] mov r98=r0 + 1816: 00 00 00 02 00 00 nop\.i 0x0 + 181c: 00 00 04 00 nop\.i 0x0;; + 1820: 01 18 03 00 00 21 \[MII\] mov r99=r0 + 1826: 00 00 00 02 00 00 nop\.i 0x0 + 182c: 00 00 04 00 nop\.i 0x0;; + 1830: 01 20 03 00 00 21 \[MII\] mov r100=r0 + 1836: 00 00 00 02 00 00 nop\.i 0x0 + 183c: 00 00 04 00 nop\.i 0x0;; + 1840: 01 28 03 00 00 21 \[MII\] mov r101=r0 + 1846: 00 00 00 02 00 00 nop\.i 0x0 + 184c: 00 00 04 00 nop\.i 0x0;; + 1850: 01 30 03 00 00 21 \[MII\] mov r102=r0 + 1856: 00 00 00 02 00 00 nop\.i 0x0 + 185c: 00 00 04 00 nop\.i 0x0;; + 1860: 01 38 03 00 00 21 \[MII\] mov r103=r0 + 1866: 00 00 00 02 00 00 nop\.i 0x0 + 186c: 00 00 04 00 nop\.i 0x0;; + 1870: 01 40 03 00 00 21 \[MII\] mov r104=r0 + 1876: 00 00 00 02 00 00 nop\.i 0x0 + 187c: 00 00 04 00 nop\.i 0x0;; + 1880: 01 48 03 00 00 21 \[MII\] mov r105=r0 + 1886: 00 00 00 02 00 00 nop\.i 0x0 + 188c: 00 00 04 00 nop\.i 0x0;; + 1890: 01 50 03 00 00 21 \[MII\] mov r106=r0 + 1896: 00 00 00 02 00 00 nop\.i 0x0 + 189c: 00 00 04 00 nop\.i 0x0;; + 18a0: 01 58 03 00 00 21 \[MII\] mov r107=r0 + 18a6: 00 00 00 02 00 00 nop\.i 0x0 + 18ac: 00 00 04 00 nop\.i 0x0;; + 18b0: 01 60 03 00 00 21 \[MII\] mov r108=r0 + 18b6: 00 00 00 02 00 00 nop\.i 0x0 + 18bc: 00 00 04 00 nop\.i 0x0;; + 18c0: 01 68 03 00 00 21 \[MII\] mov r109=r0 + 18c6: 00 00 00 02 00 00 nop\.i 0x0 + 18cc: 00 00 04 00 nop\.i 0x0;; + 18d0: 01 70 03 00 00 21 \[MII\] mov r110=r0 + 18d6: 00 00 00 02 00 00 nop\.i 0x0 + 18dc: 00 00 04 00 nop\.i 0x0;; + 18e0: 01 78 03 00 00 21 \[MII\] mov r111=r0 + 18e6: 00 00 00 02 00 00 nop\.i 0x0 + 18ec: 00 00 04 00 nop\.i 0x0;; + 18f0: 01 80 03 00 00 21 \[MII\] mov r112=r0 + 18f6: 00 00 00 02 00 00 nop\.i 0x0 + 18fc: 00 00 04 00 nop\.i 0x0;; + 1900: 01 88 03 00 00 21 \[MII\] mov r113=r0 + 1906: 00 00 00 02 00 00 nop\.i 0x0 + 190c: 00 00 04 00 nop\.i 0x0;; + 1910: 01 90 03 00 00 21 \[MII\] mov r114=r0 + 1916: 00 00 00 02 00 00 nop\.i 0x0 + 191c: 00 00 04 00 nop\.i 0x0;; + 1920: 01 98 03 00 00 21 \[MII\] mov r115=r0 + 1926: 00 00 00 02 00 00 nop\.i 0x0 + 192c: 00 00 04 00 nop\.i 0x0;; + 1930: 01 a0 03 00 00 21 \[MII\] mov r116=r0 + 1936: 00 00 00 02 00 00 nop\.i 0x0 + 193c: 00 00 04 00 nop\.i 0x0;; + 1940: 01 a8 03 00 00 21 \[MII\] mov r117=r0 + 1946: 00 00 00 02 00 00 nop\.i 0x0 + 194c: 00 00 04 00 nop\.i 0x0;; + 1950: 01 b0 03 00 00 21 \[MII\] mov r118=r0 + 1956: 00 00 00 02 00 00 nop\.i 0x0 + 195c: 00 00 04 00 nop\.i 0x0;; + 1960: 01 b8 03 00 00 21 \[MII\] mov r119=r0 + 1966: 00 00 00 02 00 00 nop\.i 0x0 + 196c: 00 00 04 00 nop\.i 0x0;; + 1970: 01 c0 03 00 00 21 \[MII\] mov r120=r0 + 1976: 00 00 00 02 00 00 nop\.i 0x0 + 197c: 00 00 04 00 nop\.i 0x0;; + 1980: 01 c8 03 00 00 21 \[MII\] mov r121=r0 + 1986: 00 00 00 02 00 00 nop\.i 0x0 + 198c: 00 00 04 00 nop\.i 0x0;; + 1990: 01 d0 03 00 00 21 \[MII\] mov r122=r0 + 1996: 00 00 00 02 00 00 nop\.i 0x0 + 199c: 00 00 04 00 nop\.i 0x0;; + 19a0: 01 d8 03 00 00 21 \[MII\] mov r123=r0 + 19a6: 00 00 00 02 00 00 nop\.i 0x0 + 19ac: 00 00 04 00 nop\.i 0x0;; + 19b0: 01 e0 03 00 00 21 \[MII\] mov r124=r0 + 19b6: 00 00 00 02 00 00 nop\.i 0x0 + 19bc: 00 00 04 00 nop\.i 0x0;; + 19c0: 01 e8 03 00 00 21 \[MII\] mov r125=r0 + 19c6: 00 00 00 02 00 00 nop\.i 0x0 + 19cc: 00 00 04 00 nop\.i 0x0;; + 19d0: 01 f0 03 00 00 21 \[MII\] mov r126=r0 + 19d6: 00 00 00 02 00 00 nop\.i 0x0 + 19dc: 00 00 04 00 nop\.i 0x0;; + 19e0: 01 f8 03 00 00 21 \[MII\] mov r127=r0 + 19e6: 00 00 00 02 00 00 nop\.i 0x0 + 19ec: 00 00 04 00 nop\.i 0x0;; + 19f0: 01 40 00 00 00 21 \[MII\] mov r8=r0 + 19f6: 00 00 00 02 00 00 nop\.i 0x0 + 19fc: 00 00 04 00 nop\.i 0x0;; + 1a00: 01 48 00 00 00 21 \[MII\] mov r9=r0 + 1a06: 00 00 00 02 00 00 nop\.i 0x0 + 1a0c: 00 00 04 00 nop\.i 0x0;; + 1a10: 01 50 00 00 00 21 \[MII\] mov r10=r0 + 1a16: 00 00 00 02 00 00 nop\.i 0x0 + 1a1c: 00 00 04 00 nop\.i 0x0;; + 1a20: 01 58 00 00 00 21 \[MII\] mov r11=r0 + 1a26: 00 00 00 02 00 00 nop\.i 0x0 + 1a2c: 00 00 04 00 nop\.i 0x0;; + 1a30: 01 08 00 00 00 21 \[MII\] mov r1=r0 + 1a36: c0 00 00 00 42 00 mov r12=r0 + 1a3c: 00 00 04 00 nop\.i 0x0;; + 1a40: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1a46: 20 00 00 20 00 00 mov f2=f0 + 1a4c: 00 00 04 00 nop\.i 0x0;; + 1a50: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1a56: 30 00 00 20 00 00 mov f3=f0 + 1a5c: 00 00 04 00 nop\.i 0x0;; + 1a60: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1a66: 40 00 00 20 00 00 mov f4=f0 + 1a6c: 00 00 04 00 nop\.i 0x0;; + 1a70: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1a76: 50 00 00 20 00 00 mov f5=f0 + 1a7c: 00 00 04 00 nop\.i 0x0;; + 1a80: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1a86: 60 00 00 20 00 00 mov f6=f0 + 1a8c: 00 00 04 00 nop\.i 0x0;; + 1a90: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1a96: 70 00 00 20 00 00 mov f7=f0 + 1a9c: 00 00 04 00 nop\.i 0x0;; + 1aa0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1aa6: 80 00 00 20 00 00 mov f8=f0 + 1aac: 00 00 04 00 nop\.i 0x0;; + 1ab0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1ab6: 90 00 00 20 00 00 mov f9=f0 + 1abc: 00 00 04 00 nop\.i 0x0;; + 1ac0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1ac6: a0 00 00 20 00 00 mov f10=f0 + 1acc: 00 00 04 00 nop\.i 0x0;; + 1ad0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1ad6: b0 00 00 20 00 00 mov f11=f0 + 1adc: 00 00 04 00 nop\.i 0x0;; + 1ae0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1ae6: c0 00 00 20 00 00 mov f12=f0 + 1aec: 00 00 04 00 nop\.i 0x0;; + 1af0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1af6: d0 00 00 20 00 00 mov f13=f0 + 1afc: 00 00 04 00 nop\.i 0x0;; + 1b00: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1b06: e0 00 00 20 00 00 mov f14=f0 + 1b0c: 00 00 04 00 nop\.i 0x0;; + 1b10: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1b16: f0 00 00 20 00 00 mov f15=f0 + 1b1c: 00 00 04 00 nop\.i 0x0;; + 1b20: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1b26: 00 01 00 20 00 00 mov f16=f0 + 1b2c: 00 00 04 00 nop\.i 0x0;; + 1b30: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1b36: 10 01 00 20 00 00 mov f17=f0 + 1b3c: 00 00 04 00 nop\.i 0x0;; + 1b40: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1b46: 20 01 00 20 00 00 mov f18=f0 + 1b4c: 00 00 04 00 nop\.i 0x0;; + 1b50: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1b56: 30 01 00 20 00 00 mov f19=f0 + 1b5c: 00 00 04 00 nop\.i 0x0;; + 1b60: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1b66: 40 01 00 20 00 00 mov f20=f0 + 1b6c: 00 00 04 00 nop\.i 0x0;; + 1b70: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1b76: 50 01 00 20 00 00 mov f21=f0 + 1b7c: 00 00 04 00 nop\.i 0x0;; + 1b80: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1b86: 60 01 00 20 00 00 mov f22=f0 + 1b8c: 00 00 04 00 nop\.i 0x0;; + 1b90: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1b96: 70 01 00 20 00 00 mov f23=f0 + 1b9c: 00 00 04 00 nop\.i 0x0;; + 1ba0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1ba6: 80 01 00 20 00 00 mov f24=f0 + 1bac: 00 00 04 00 nop\.i 0x0;; + 1bb0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1bb6: 90 01 00 20 00 00 mov f25=f0 + 1bbc: 00 00 04 00 nop\.i 0x0;; + 1bc0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1bc6: a0 01 00 20 00 00 mov f26=f0 + 1bcc: 00 00 04 00 nop\.i 0x0;; + 1bd0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1bd6: b0 01 00 20 00 00 mov f27=f0 + 1bdc: 00 00 04 00 nop\.i 0x0;; + 1be0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1be6: c0 01 00 20 00 00 mov f28=f0 + 1bec: 00 00 04 00 nop\.i 0x0;; + 1bf0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1bf6: d0 01 00 20 00 00 mov f29=f0 + 1bfc: 00 00 04 00 nop\.i 0x0;; + 1c00: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1c06: e0 01 00 20 00 00 mov f30=f0 + 1c0c: 00 00 04 00 nop\.i 0x0;; + 1c10: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1c16: f0 01 00 20 00 00 mov f31=f0 + 1c1c: 00 00 04 00 nop\.i 0x0;; + 1c20: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1c26: 00 02 00 20 00 00 mov f32=f0 + 1c2c: 00 00 04 00 nop\.i 0x0;; + 1c30: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1c36: 10 02 00 20 00 00 mov f33=f0 + 1c3c: 00 00 04 00 nop\.i 0x0;; + 1c40: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1c46: 20 02 00 20 00 00 mov f34=f0 + 1c4c: 00 00 04 00 nop\.i 0x0;; + 1c50: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1c56: 30 02 00 20 00 00 mov f35=f0 + 1c5c: 00 00 04 00 nop\.i 0x0;; + 1c60: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1c66: 40 02 00 20 00 00 mov f36=f0 + 1c6c: 00 00 04 00 nop\.i 0x0;; + 1c70: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1c76: 50 02 00 20 00 00 mov f37=f0 + 1c7c: 00 00 04 00 nop\.i 0x0;; + 1c80: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1c86: 60 02 00 20 00 00 mov f38=f0 + 1c8c: 00 00 04 00 nop\.i 0x0;; + 1c90: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1c96: 70 02 00 20 00 00 mov f39=f0 + 1c9c: 00 00 04 00 nop\.i 0x0;; + 1ca0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1ca6: 80 02 00 20 00 00 mov f40=f0 + 1cac: 00 00 04 00 nop\.i 0x0;; + 1cb0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1cb6: 90 02 00 20 00 00 mov f41=f0 + 1cbc: 00 00 04 00 nop\.i 0x0;; + 1cc0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1cc6: a0 02 00 20 00 00 mov f42=f0 + 1ccc: 00 00 04 00 nop\.i 0x0;; + 1cd0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1cd6: b0 02 00 20 00 00 mov f43=f0 + 1cdc: 00 00 04 00 nop\.i 0x0;; + 1ce0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1ce6: c0 02 00 20 00 00 mov f44=f0 + 1cec: 00 00 04 00 nop\.i 0x0;; + 1cf0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1cf6: d0 02 00 20 00 00 mov f45=f0 + 1cfc: 00 00 04 00 nop\.i 0x0;; + 1d00: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1d06: e0 02 00 20 00 00 mov f46=f0 + 1d0c: 00 00 04 00 nop\.i 0x0;; + 1d10: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1d16: f0 02 00 20 00 00 mov f47=f0 + 1d1c: 00 00 04 00 nop\.i 0x0;; + 1d20: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1d26: 00 03 00 20 00 00 mov f48=f0 + 1d2c: 00 00 04 00 nop\.i 0x0;; + 1d30: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1d36: 10 03 00 20 00 00 mov f49=f0 + 1d3c: 00 00 04 00 nop\.i 0x0;; + 1d40: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1d46: 20 03 00 20 00 00 mov f50=f0 + 1d4c: 00 00 04 00 nop\.i 0x0;; + 1d50: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1d56: 30 03 00 20 00 00 mov f51=f0 + 1d5c: 00 00 04 00 nop\.i 0x0;; + 1d60: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1d66: 40 03 00 20 00 00 mov f52=f0 + 1d6c: 00 00 04 00 nop\.i 0x0;; + 1d70: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1d76: 50 03 00 20 00 00 mov f53=f0 + 1d7c: 00 00 04 00 nop\.i 0x0;; + 1d80: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1d86: 60 03 00 20 00 00 mov f54=f0 + 1d8c: 00 00 04 00 nop\.i 0x0;; + 1d90: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1d96: 70 03 00 20 00 00 mov f55=f0 + 1d9c: 00 00 04 00 nop\.i 0x0;; + 1da0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1da6: 80 03 00 20 00 00 mov f56=f0 + 1dac: 00 00 04 00 nop\.i 0x0;; + 1db0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1db6: 90 03 00 20 00 00 mov f57=f0 + 1dbc: 00 00 04 00 nop\.i 0x0;; + 1dc0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1dc6: a0 03 00 20 00 00 mov f58=f0 + 1dcc: 00 00 04 00 nop\.i 0x0;; + 1dd0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1dd6: b0 03 00 20 00 00 mov f59=f0 + 1ddc: 00 00 04 00 nop\.i 0x0;; + 1de0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1de6: c0 03 00 20 00 00 mov f60=f0 + 1dec: 00 00 04 00 nop\.i 0x0;; + 1df0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1df6: d0 03 00 20 00 00 mov f61=f0 + 1dfc: 00 00 04 00 nop\.i 0x0;; + 1e00: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1e06: e0 03 00 20 00 00 mov f62=f0 + 1e0c: 00 00 04 00 nop\.i 0x0;; + 1e10: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1e16: f0 03 00 20 00 00 mov f63=f0 + 1e1c: 00 00 04 00 nop\.i 0x0;; + 1e20: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1e26: 00 04 00 20 00 00 mov f64=f0 + 1e2c: 00 00 04 00 nop\.i 0x0;; + 1e30: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1e36: 10 04 00 20 00 00 mov f65=f0 + 1e3c: 00 00 04 00 nop\.i 0x0;; + 1e40: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1e46: 20 04 00 20 00 00 mov f66=f0 + 1e4c: 00 00 04 00 nop\.i 0x0;; + 1e50: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1e56: 30 04 00 20 00 00 mov f67=f0 + 1e5c: 00 00 04 00 nop\.i 0x0;; + 1e60: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1e66: 40 04 00 20 00 00 mov f68=f0 + 1e6c: 00 00 04 00 nop\.i 0x0;; + 1e70: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1e76: 50 04 00 20 00 00 mov f69=f0 + 1e7c: 00 00 04 00 nop\.i 0x0;; + 1e80: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1e86: 60 04 00 20 00 00 mov f70=f0 + 1e8c: 00 00 04 00 nop\.i 0x0;; + 1e90: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1e96: 70 04 00 20 00 00 mov f71=f0 + 1e9c: 00 00 04 00 nop\.i 0x0;; + 1ea0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1ea6: 80 04 00 20 00 00 mov f72=f0 + 1eac: 00 00 04 00 nop\.i 0x0;; + 1eb0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1eb6: 90 04 00 20 00 00 mov f73=f0 + 1ebc: 00 00 04 00 nop\.i 0x0;; + 1ec0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1ec6: a0 04 00 20 00 00 mov f74=f0 + 1ecc: 00 00 04 00 nop\.i 0x0;; + 1ed0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1ed6: b0 04 00 20 00 00 mov f75=f0 + 1edc: 00 00 04 00 nop\.i 0x0;; + 1ee0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1ee6: c0 04 00 20 00 00 mov f76=f0 + 1eec: 00 00 04 00 nop\.i 0x0;; + 1ef0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1ef6: d0 04 00 20 00 00 mov f77=f0 + 1efc: 00 00 04 00 nop\.i 0x0;; + 1f00: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1f06: e0 04 00 20 00 00 mov f78=f0 + 1f0c: 00 00 04 00 nop\.i 0x0;; + 1f10: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1f16: f0 04 00 20 00 00 mov f79=f0 + 1f1c: 00 00 04 00 nop\.i 0x0;; + 1f20: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1f26: 00 05 00 20 00 00 mov f80=f0 + 1f2c: 00 00 04 00 nop\.i 0x0;; + 1f30: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1f36: 10 05 00 20 00 00 mov f81=f0 + 1f3c: 00 00 04 00 nop\.i 0x0;; + 1f40: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1f46: 20 05 00 20 00 00 mov f82=f0 + 1f4c: 00 00 04 00 nop\.i 0x0;; + 1f50: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1f56: 30 05 00 20 00 00 mov f83=f0 + 1f5c: 00 00 04 00 nop\.i 0x0;; + 1f60: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1f66: 40 05 00 20 00 00 mov f84=f0 + 1f6c: 00 00 04 00 nop\.i 0x0;; + 1f70: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1f76: 50 05 00 20 00 00 mov f85=f0 + 1f7c: 00 00 04 00 nop\.i 0x0;; + 1f80: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1f86: 60 05 00 20 00 00 mov f86=f0 + 1f8c: 00 00 04 00 nop\.i 0x0;; + 1f90: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1f96: 70 05 00 20 00 00 mov f87=f0 + 1f9c: 00 00 04 00 nop\.i 0x0;; + 1fa0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1fa6: 80 05 00 20 00 00 mov f88=f0 + 1fac: 00 00 04 00 nop\.i 0x0;; + 1fb0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1fb6: 90 05 00 20 00 00 mov f89=f0 + 1fbc: 00 00 04 00 nop\.i 0x0;; + 1fc0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1fc6: a0 05 00 20 00 00 mov f90=f0 + 1fcc: 00 00 04 00 nop\.i 0x0;; + 1fd0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1fd6: b0 05 00 20 00 00 mov f91=f0 + 1fdc: 00 00 04 00 nop\.i 0x0;; + 1fe0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1fe6: c0 05 00 20 00 00 mov f92=f0 + 1fec: 00 00 04 00 nop\.i 0x0;; + 1ff0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 1ff6: d0 05 00 20 00 00 mov f93=f0 + 1ffc: 00 00 04 00 nop\.i 0x0;; + 2000: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2006: e0 05 00 20 00 00 mov f94=f0 + 200c: 00 00 04 00 nop\.i 0x0;; + 2010: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2016: f0 05 00 20 00 00 mov f95=f0 + 201c: 00 00 04 00 nop\.i 0x0;; + 2020: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2026: 00 06 00 20 00 00 mov f96=f0 + 202c: 00 00 04 00 nop\.i 0x0;; + 2030: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2036: 10 06 00 20 00 00 mov f97=f0 + 203c: 00 00 04 00 nop\.i 0x0;; + 2040: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2046: 20 06 00 20 00 00 mov f98=f0 + 204c: 00 00 04 00 nop\.i 0x0;; + 2050: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2056: 30 06 00 20 00 00 mov f99=f0 + 205c: 00 00 04 00 nop\.i 0x0;; + 2060: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2066: 40 06 00 20 00 00 mov f100=f0 + 206c: 00 00 04 00 nop\.i 0x0;; + 2070: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2076: 50 06 00 20 00 00 mov f101=f0 + 207c: 00 00 04 00 nop\.i 0x0;; + 2080: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2086: 60 06 00 20 00 00 mov f102=f0 + 208c: 00 00 04 00 nop\.i 0x0;; + 2090: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2096: 70 06 00 20 00 00 mov f103=f0 + 209c: 00 00 04 00 nop\.i 0x0;; + 20a0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 20a6: 80 06 00 20 00 00 mov f104=f0 + 20ac: 00 00 04 00 nop\.i 0x0;; + 20b0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 20b6: 90 06 00 20 00 00 mov f105=f0 + 20bc: 00 00 04 00 nop\.i 0x0;; + 20c0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 20c6: a0 06 00 20 00 00 mov f106=f0 + 20cc: 00 00 04 00 nop\.i 0x0;; + 20d0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 20d6: b0 06 00 20 00 00 mov f107=f0 + 20dc: 00 00 04 00 nop\.i 0x0;; + 20e0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 20e6: c0 06 00 20 00 00 mov f108=f0 + 20ec: 00 00 04 00 nop\.i 0x0;; + 20f0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 20f6: d0 06 00 20 00 00 mov f109=f0 + 20fc: 00 00 04 00 nop\.i 0x0;; + 2100: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2106: e0 06 00 20 00 00 mov f110=f0 + 210c: 00 00 04 00 nop\.i 0x0;; + 2110: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2116: f0 06 00 20 00 00 mov f111=f0 + 211c: 00 00 04 00 nop\.i 0x0;; + 2120: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2126: 00 07 00 20 00 00 mov f112=f0 + 212c: 00 00 04 00 nop\.i 0x0;; + 2130: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2136: 10 07 00 20 00 00 mov f113=f0 + 213c: 00 00 04 00 nop\.i 0x0;; + 2140: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2146: 20 07 00 20 00 00 mov f114=f0 + 214c: 00 00 04 00 nop\.i 0x0;; + 2150: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2156: 30 07 00 20 00 00 mov f115=f0 + 215c: 00 00 04 00 nop\.i 0x0;; + 2160: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2166: 40 07 00 20 00 00 mov f116=f0 + 216c: 00 00 04 00 nop\.i 0x0;; + 2170: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2176: 50 07 00 20 00 00 mov f117=f0 + 217c: 00 00 04 00 nop\.i 0x0;; + 2180: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2186: 60 07 00 20 00 00 mov f118=f0 + 218c: 00 00 04 00 nop\.i 0x0;; + 2190: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2196: 70 07 00 20 00 00 mov f119=f0 + 219c: 00 00 04 00 nop\.i 0x0;; + 21a0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 21a6: 80 07 00 20 00 00 mov f120=f0 + 21ac: 00 00 04 00 nop\.i 0x0;; + 21b0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 21b6: 90 07 00 20 00 00 mov f121=f0 + 21bc: 00 00 04 00 nop\.i 0x0;; + 21c0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 21c6: a0 07 00 20 00 00 mov f122=f0 + 21cc: 00 00 04 00 nop\.i 0x0;; + 21d0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 21d6: b0 07 00 20 00 00 mov f123=f0 + 21dc: 00 00 04 00 nop\.i 0x0;; + 21e0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 21e6: c0 07 00 20 00 00 mov f124=f0 + 21ec: 00 00 04 00 nop\.i 0x0;; + 21f0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 21f6: d0 07 00 20 00 00 mov f125=f0 + 21fc: 00 00 04 00 nop\.i 0x0;; + 2200: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2206: e0 07 00 20 00 00 mov f126=f0 + 220c: 00 00 04 00 nop\.i 0x0;; + 2210: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2216: f0 07 00 20 00 00 mov f127=f0 + 221c: 00 00 04 00 nop\.i 0x0;; + 2220: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2226: 80 08 04 20 00 00 mov f8=f1 + 222c: 00 00 04 00 nop\.i 0x0;; + 2230: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2236: 90 08 04 20 00 00 mov f9=f1 + 223c: 00 00 04 00 nop\.i 0x0;; + 2240: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2246: a0 08 04 20 00 00 mov f10=f1 + 224c: 00 00 04 00 nop\.i 0x0;; + 2250: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2256: b0 08 04 20 00 00 mov f11=f1 + 225c: 00 00 04 00 nop\.i 0x0;; + 2260: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2266: c0 08 04 20 00 00 mov f12=f1 + 226c: 00 00 04 00 nop\.i 0x0;; + 2270: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2276: d0 08 04 20 00 00 mov f13=f1 + 227c: 00 00 04 00 nop\.i 0x0;; + 2280: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2286: e0 08 04 20 00 00 mov f14=f1 + 228c: 00 00 04 00 nop\.i 0x0;; + 2290: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2296: f0 08 04 20 00 00 mov f15=f1 + 229c: 00 00 04 00 nop\.i 0x0;; + 22a0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 22a6: 80 08 04 20 00 00 mov f8=f1 + 22ac: 00 00 04 00 nop\.i 0x0;; + 22b0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 22b6: 90 08 04 20 00 00 mov f9=f1 + 22bc: 00 00 04 00 nop\.i 0x0;; + 22c0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 22c6: a0 08 04 20 00 00 mov f10=f1 + 22cc: 00 00 04 00 nop\.i 0x0;; + 22d0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 22d6: b0 08 04 20 00 00 mov f11=f1 + 22dc: 00 00 04 00 nop\.i 0x0;; + 22e0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 22e6: c0 08 04 20 00 00 mov f12=f1 + 22ec: 00 00 04 00 nop\.i 0x0;; + 22f0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 22f6: d0 08 04 20 00 00 mov f13=f1 + 22fc: 00 00 04 00 nop\.i 0x0;; + 2300: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2306: e0 08 04 20 00 00 mov f14=f1 + 230c: 00 00 04 00 nop\.i 0x0;; + 2310: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 + 2316: f0 08 04 20 00 00 mov f15=f1 + 231c: 00 00 04 00 nop\.i 0x0;; + 2320: 01 08 00 00 00 21 \[MII\] mov r1=r0 + 2326: 00 00 00 02 00 00 nop\.i 0x0 + 232c: 00 00 04 00 nop\.i 0x0;; + 2330: 21 10 00 00 00 21 \[MII\] \(p01\) mov r2=r0 + 2336: 00 00 00 02 00 00 nop\.i 0x0 + 233c: 00 00 04 00 nop\.i 0x0;; + 2340: 41 18 00 00 00 21 \[MII\] \(p02\) mov r3=r0 + 2346: 00 00 00 02 00 00 nop\.i 0x0 + 234c: 00 00 04 00 nop\.i 0x0;; + 2350: 61 20 00 00 00 21 \[MII\] \(p03\) mov r4=r0 + 2356: 00 00 00 02 00 00 nop\.i 0x0 + 235c: 00 00 04 00 nop\.i 0x0;; + 2360: 81 28 00 00 00 21 \[MII\] \(p04\) mov r5=r0 + 2366: 00 00 00 02 00 00 nop\.i 0x0 + 236c: 00 00 04 00 nop\.i 0x0;; + 2370: a1 30 00 00 00 21 \[MII\] \(p05\) mov r6=r0 + 2376: 00 00 00 02 00 00 nop\.i 0x0 + 237c: 00 00 04 00 nop\.i 0x0;; + 2380: c1 38 00 00 00 21 \[MII\] \(p06\) mov r7=r0 + 2386: 00 00 00 02 00 00 nop\.i 0x0 + 238c: 00 00 04 00 nop\.i 0x0;; + 2390: e1 40 00 00 00 21 \[MII\] \(p07\) mov r8=r0 + 2396: 00 00 00 02 00 00 nop\.i 0x0 + 239c: 00 00 04 00 nop\.i 0x0;; + 23a0: 01 49 00 00 00 21 \[MII\] \(p08\) mov r9=r0 + 23a6: 00 00 00 02 00 00 nop\.i 0x0 + 23ac: 00 00 04 00 nop\.i 0x0;; + 23b0: 21 51 00 00 00 21 \[MII\] \(p09\) mov r10=r0 + 23b6: 00 00 00 02 00 00 nop\.i 0x0 + 23bc: 00 00 04 00 nop\.i 0x0;; + 23c0: 41 59 00 00 00 21 \[MII\] \(p10\) mov r11=r0 + 23c6: 00 00 00 02 00 00 nop\.i 0x0 + 23cc: 00 00 04 00 nop\.i 0x0;; + 23d0: 61 61 00 00 00 21 \[MII\] \(p11\) mov r12=r0 + 23d6: 00 00 00 02 00 00 nop\.i 0x0 + 23dc: 00 00 04 00 nop\.i 0x0;; + 23e0: 81 69 00 00 00 21 \[MII\] \(p12\) mov r13=r0 + 23e6: 00 00 00 02 00 00 nop\.i 0x0 + 23ec: 00 00 04 00 nop\.i 0x0;; + 23f0: a1 71 00 00 00 21 \[MII\] \(p13\) mov r14=r0 + 23f6: 00 00 00 02 00 00 nop\.i 0x0 + 23fc: 00 00 04 00 nop\.i 0x0;; + 2400: c1 79 00 00 00 21 \[MII\] \(p14\) mov r15=r0 + 2406: 00 00 00 02 00 00 nop\.i 0x0 + 240c: 00 00 04 00 nop\.i 0x0;; + 2410: e1 81 00 00 00 21 \[MII\] \(p15\) mov r16=r0 + 2416: 00 00 00 02 00 00 nop\.i 0x0 + 241c: 00 00 04 00 nop\.i 0x0;; + 2420: 01 8a 00 00 00 21 \[MII\] \(p16\) mov r17=r0 + 2426: 00 00 00 02 00 00 nop\.i 0x0 + 242c: 00 00 04 00 nop\.i 0x0;; + 2430: 21 92 00 00 00 21 \[MII\] \(p17\) mov r18=r0 + 2436: 00 00 00 02 00 00 nop\.i 0x0 + 243c: 00 00 04 00 nop\.i 0x0;; + 2440: 41 9a 00 00 00 21 \[MII\] \(p18\) mov r19=r0 + 2446: 00 00 00 02 00 00 nop\.i 0x0 + 244c: 00 00 04 00 nop\.i 0x0;; + 2450: 61 a2 00 00 00 21 \[MII\] \(p19\) mov r20=r0 + 2456: 00 00 00 02 00 00 nop\.i 0x0 + 245c: 00 00 04 00 nop\.i 0x0;; + 2460: 81 aa 00 00 00 21 \[MII\] \(p20\) mov r21=r0 + 2466: 00 00 00 02 00 00 nop\.i 0x0 + 246c: 00 00 04 00 nop\.i 0x0;; + 2470: a1 b2 00 00 00 21 \[MII\] \(p21\) mov r22=r0 + 2476: 00 00 00 02 00 00 nop\.i 0x0 + 247c: 00 00 04 00 nop\.i 0x0;; + 2480: c1 ba 00 00 00 21 \[MII\] \(p22\) mov r23=r0 + 2486: 00 00 00 02 00 00 nop\.i 0x0 + 248c: 00 00 04 00 nop\.i 0x0;; + 2490: e1 c2 00 00 00 21 \[MII\] \(p23\) mov r24=r0 + 2496: 00 00 00 02 00 00 nop\.i 0x0 + 249c: 00 00 04 00 nop\.i 0x0;; + 24a0: 01 cb 00 00 00 21 \[MII\] \(p24\) mov r25=r0 + 24a6: 00 00 00 02 00 00 nop\.i 0x0 + 24ac: 00 00 04 00 nop\.i 0x0;; + 24b0: 21 d3 00 00 00 21 \[MII\] \(p25\) mov r26=r0 + 24b6: 00 00 00 02 00 00 nop\.i 0x0 + 24bc: 00 00 04 00 nop\.i 0x0;; + 24c0: 41 db 00 00 00 21 \[MII\] \(p26\) mov r27=r0 + 24c6: 00 00 00 02 00 00 nop\.i 0x0 + 24cc: 00 00 04 00 nop\.i 0x0;; + 24d0: 61 e3 00 00 00 21 \[MII\] \(p27\) mov r28=r0 + 24d6: 00 00 00 02 00 00 nop\.i 0x0 + 24dc: 00 00 04 00 nop\.i 0x0;; + 24e0: 81 eb 00 00 00 21 \[MII\] \(p28\) mov r29=r0 + 24e6: 00 00 00 02 00 00 nop\.i 0x0 + 24ec: 00 00 04 00 nop\.i 0x0;; + 24f0: a1 f3 00 00 00 21 \[MII\] \(p29\) mov r30=r0 + 24f6: 00 00 00 02 00 00 nop\.i 0x0 + 24fc: 00 00 04 00 nop\.i 0x0;; + 2500: c1 fb 00 00 00 21 \[MII\] \(p30\) mov r31=r0 + 2506: 00 00 00 02 00 00 nop\.i 0x0 + 250c: 00 00 04 00 nop\.i 0x0;; + 2510: e1 03 01 00 00 21 \[MII\] \(p31\) mov r32=r0 + 2516: 00 00 00 02 00 00 nop\.i 0x0 + 251c: 00 00 04 00 nop\.i 0x0;; + 2520: 01 0c 01 00 00 21 \[MII\] \(p32\) mov r33=r0 + 2526: 00 00 00 02 00 00 nop\.i 0x0 + 252c: 00 00 04 00 nop\.i 0x0;; + 2530: 21 14 01 00 00 21 \[MII\] \(p33\) mov r34=r0 + 2536: 00 00 00 02 00 00 nop\.i 0x0 + 253c: 00 00 04 00 nop\.i 0x0;; + 2540: 41 1c 01 00 00 21 \[MII\] \(p34\) mov r35=r0 + 2546: 00 00 00 02 00 00 nop\.i 0x0 + 254c: 00 00 04 00 nop\.i 0x0;; + 2550: 61 24 01 00 00 21 \[MII\] \(p35\) mov r36=r0 + 2556: 00 00 00 02 00 00 nop\.i 0x0 + 255c: 00 00 04 00 nop\.i 0x0;; + 2560: 81 2c 01 00 00 21 \[MII\] \(p36\) mov r37=r0 + 2566: 00 00 00 02 00 00 nop\.i 0x0 + 256c: 00 00 04 00 nop\.i 0x0;; + 2570: a1 34 01 00 00 21 \[MII\] \(p37\) mov r38=r0 + 2576: 00 00 00 02 00 00 nop\.i 0x0 + 257c: 00 00 04 00 nop\.i 0x0;; + 2580: c1 3c 01 00 00 21 \[MII\] \(p38\) mov r39=r0 + 2586: 00 00 00 02 00 00 nop\.i 0x0 + 258c: 00 00 04 00 nop\.i 0x0;; + 2590: e1 44 01 00 00 21 \[MII\] \(p39\) mov r40=r0 + 2596: 00 00 00 02 00 00 nop\.i 0x0 + 259c: 00 00 04 00 nop\.i 0x0;; + 25a0: 01 4d 01 00 00 21 \[MII\] \(p40\) mov r41=r0 + 25a6: 00 00 00 02 00 00 nop\.i 0x0 + 25ac: 00 00 04 00 nop\.i 0x0;; + 25b0: 21 55 01 00 00 21 \[MII\] \(p41\) mov r42=r0 + 25b6: 00 00 00 02 00 00 nop\.i 0x0 + 25bc: 00 00 04 00 nop\.i 0x0;; + 25c0: 41 5d 01 00 00 21 \[MII\] \(p42\) mov r43=r0 + 25c6: 00 00 00 02 00 00 nop\.i 0x0 + 25cc: 00 00 04 00 nop\.i 0x0;; + 25d0: 61 65 01 00 00 21 \[MII\] \(p43\) mov r44=r0 + 25d6: 00 00 00 02 00 00 nop\.i 0x0 + 25dc: 00 00 04 00 nop\.i 0x0;; + 25e0: 81 6d 01 00 00 21 \[MII\] \(p44\) mov r45=r0 + 25e6: 00 00 00 02 00 00 nop\.i 0x0 + 25ec: 00 00 04 00 nop\.i 0x0;; + 25f0: a1 75 01 00 00 21 \[MII\] \(p45\) mov r46=r0 + 25f6: 00 00 00 02 00 00 nop\.i 0x0 + 25fc: 00 00 04 00 nop\.i 0x0;; + 2600: c1 7d 01 00 00 21 \[MII\] \(p46\) mov r47=r0 + 2606: 00 00 00 02 00 00 nop\.i 0x0 + 260c: 00 00 04 00 nop\.i 0x0;; + 2610: e1 85 01 00 00 21 \[MII\] \(p47\) mov r48=r0 + 2616: 00 00 00 02 00 00 nop\.i 0x0 + 261c: 00 00 04 00 nop\.i 0x0;; + 2620: 01 8e 01 00 00 21 \[MII\] \(p48\) mov r49=r0 + 2626: 00 00 00 02 00 00 nop\.i 0x0 + 262c: 00 00 04 00 nop\.i 0x0;; + 2630: 21 96 01 00 00 21 \[MII\] \(p49\) mov r50=r0 + 2636: 00 00 00 02 00 00 nop\.i 0x0 + 263c: 00 00 04 00 nop\.i 0x0;; + 2640: 41 9e 01 00 00 21 \[MII\] \(p50\) mov r51=r0 + 2646: 00 00 00 02 00 00 nop\.i 0x0 + 264c: 00 00 04 00 nop\.i 0x0;; + 2650: 61 a6 01 00 00 21 \[MII\] \(p51\) mov r52=r0 + 2656: 00 00 00 02 00 00 nop\.i 0x0 + 265c: 00 00 04 00 nop\.i 0x0;; + 2660: 81 ae 01 00 00 21 \[MII\] \(p52\) mov r53=r0 + 2666: 00 00 00 02 00 00 nop\.i 0x0 + 266c: 00 00 04 00 nop\.i 0x0;; + 2670: a1 b6 01 00 00 21 \[MII\] \(p53\) mov r54=r0 + 2676: 00 00 00 02 00 00 nop\.i 0x0 + 267c: 00 00 04 00 nop\.i 0x0;; + 2680: c1 be 01 00 00 21 \[MII\] \(p54\) mov r55=r0 + 2686: 00 00 00 02 00 00 nop\.i 0x0 + 268c: 00 00 04 00 nop\.i 0x0;; + 2690: e1 c6 01 00 00 21 \[MII\] \(p55\) mov r56=r0 + 2696: 00 00 00 02 00 00 nop\.i 0x0 + 269c: 00 00 04 00 nop\.i 0x0;; + 26a0: 01 cf 01 00 00 21 \[MII\] \(p56\) mov r57=r0 + 26a6: 00 00 00 02 00 00 nop\.i 0x0 + 26ac: 00 00 04 00 nop\.i 0x0;; + 26b0: 21 d7 01 00 00 21 \[MII\] \(p57\) mov r58=r0 + 26b6: 00 00 00 02 00 00 nop\.i 0x0 + 26bc: 00 00 04 00 nop\.i 0x0;; + 26c0: 41 df 01 00 00 21 \[MII\] \(p58\) mov r59=r0 + 26c6: 00 00 00 02 00 00 nop\.i 0x0 + 26cc: 00 00 04 00 nop\.i 0x0;; + 26d0: 61 e7 01 00 00 21 \[MII\] \(p59\) mov r60=r0 + 26d6: 00 00 00 02 00 00 nop\.i 0x0 + 26dc: 00 00 04 00 nop\.i 0x0;; + 26e0: 81 ef 01 00 00 21 \[MII\] \(p60\) mov r61=r0 + 26e6: 00 00 00 02 00 00 nop\.i 0x0 + 26ec: 00 00 04 00 nop\.i 0x0;; + 26f0: a1 f7 01 00 00 21 \[MII\] \(p61\) mov r62=r0 + 26f6: 00 00 00 02 00 00 nop\.i 0x0 + 26fc: 00 00 04 00 nop\.i 0x0;; + 2700: c1 ff 01 00 00 21 \[MII\] \(p62\) mov r63=r0 + 2706: 00 00 00 02 00 00 nop\.i 0x0 + 270c: 00 00 04 00 nop\.i 0x0;; + 2710: e1 07 02 00 00 21 \[MII\] \(p63\) mov r64=r0 + 2716: 00 00 00 02 00 00 nop\.i 0x0 + 271c: 00 00 04 00 nop\.i 0x0;; + 2720: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2726: 00 00 00 02 00 20 nop\.m 0x0 + 272c: 00 00 cc 00 mov r1=pr;; + 2730: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2736: 00 00 00 02 00 00 nop\.m 0x0 + 273c: 00 08 00 07 mov b0=r0;; + 2740: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2746: 00 00 00 02 00 20 nop\.m 0x0 + 274c: 00 08 00 07 mov b1=r0;; + 2750: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2756: 00 00 00 02 00 40 nop\.m 0x0 + 275c: 00 08 00 07 mov b2=r0;; + 2760: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2766: 00 00 00 02 00 60 nop\.m 0x0 + 276c: 00 08 00 07 mov b3=r0;; + 2770: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2776: 00 00 00 02 00 80 nop\.m 0x0 + 277c: 00 08 00 07 mov b4=r0;; + 2780: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2786: 00 00 00 02 00 a0 nop\.m 0x0 + 278c: 00 08 00 07 mov b5=r0;; + 2790: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2796: 00 00 00 02 00 c0 nop\.m 0x0 + 279c: 00 08 00 07 mov b6=r0;; + 27a0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 27a6: 00 00 00 02 00 e0 nop\.m 0x0 + 27ac: 00 08 00 07 mov b7=r0;; + 27b0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 27b6: 00 00 00 02 00 00 nop\.m 0x0 + 27bc: 00 08 00 07 mov b0=r0;; + 27c0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 27c6: 10 00 00 44 08 00 mov\.m r1=ar\.k0 + 27cc: 00 00 04 00 nop\.i 0x0;; + 27d0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 27d6: 10 00 04 44 08 00 mov\.m r1=ar\.k1 + 27dc: 00 00 04 00 nop\.i 0x0;; + 27e0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 27e6: 10 00 08 44 08 00 mov\.m r1=ar\.k2 + 27ec: 00 00 04 00 nop\.i 0x0;; + 27f0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 27f6: 10 00 0c 44 08 00 mov\.m r1=ar\.k3 + 27fc: 00 00 04 00 nop\.i 0x0;; + 2800: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2806: 10 00 10 44 08 00 mov\.m r1=ar\.k4 + 280c: 00 00 04 00 nop\.i 0x0;; + 2810: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2816: 10 00 14 44 08 00 mov\.m r1=ar\.k5 + 281c: 00 00 04 00 nop\.i 0x0;; + 2820: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2826: 10 00 18 44 08 00 mov\.m r1=ar\.k6 + 282c: 00 00 04 00 nop\.i 0x0;; + 2830: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2836: 10 00 1c 44 08 00 mov\.m r1=ar\.k7 + 283c: 00 00 04 00 nop\.i 0x0;; + 2840: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2846: 10 00 40 44 08 00 mov\.m r1=ar\.rsc + 284c: 00 00 04 00 nop\.i 0x0;; + 2850: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2856: 10 00 44 44 08 00 mov\.m r1=ar\.bsp + 285c: 00 00 04 00 nop\.i 0x0;; + 2860: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2866: 10 00 48 44 08 00 mov\.m r1=ar\.bspstore + 286c: 00 00 04 00 nop\.i 0x0;; + 2870: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2876: 10 00 4c 44 08 00 mov\.m r1=ar\.rnat + 287c: 00 00 04 00 nop\.i 0x0;; + 2880: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2886: 10 00 54 44 08 00 mov\.m r1=ar21 + 288c: 00 00 04 00 nop\.i 0x0;; + 2890: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2896: 10 00 60 44 08 00 mov\.m r1=ar24 + 289c: 00 00 04 00 nop\.i 0x0;; + 28a0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 28a6: 10 00 64 44 08 00 mov\.m r1=ar25 + 28ac: 00 00 04 00 nop\.i 0x0;; + 28b0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 28b6: 10 00 68 44 08 00 mov\.m r1=ar26 + 28bc: 00 00 04 00 nop\.i 0x0;; + 28c0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 28c6: 10 00 6c 44 08 00 mov\.m r1=ar27 + 28cc: 00 00 04 00 nop\.i 0x0;; + 28d0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 28d6: 10 00 70 44 08 00 mov\.m r1=ar28 + 28dc: 00 00 04 00 nop\.i 0x0;; + 28e0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 28e6: 10 00 74 44 08 00 mov\.m r1=ar29 + 28ec: 00 00 04 00 nop\.i 0x0;; + 28f0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 28f6: 10 00 78 44 08 00 mov\.m r1=ar30 + 28fc: 00 00 04 00 nop\.i 0x0;; + 2900: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2906: 10 00 80 44 08 00 mov\.m r1=ar\.ccv + 290c: 00 00 04 00 nop\.i 0x0;; + 2910: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2916: 10 00 90 44 08 00 mov\.m r1=ar\.unat + 291c: 00 00 04 00 nop\.i 0x0;; + 2920: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2926: 10 00 a0 44 08 00 mov\.m r1=ar\.fpsr + 292c: 00 00 04 00 nop\.i 0x0;; + 2930: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2936: 10 00 c0 44 08 00 mov\.m r1=ar48 + 293c: 00 00 04 00 nop\.i 0x0;; + 2940: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2946: 10 00 c4 44 08 00 mov\.m r1=ar49 + 294c: 00 00 04 00 nop\.i 0x0;; + 2950: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2956: 10 00 c8 44 08 00 mov\.m r1=ar50 + 295c: 00 00 04 00 nop\.i 0x0;; + 2960: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2966: 10 00 cc 44 08 00 mov\.m r1=ar51 + 296c: 00 00 04 00 nop\.i 0x0;; + 2970: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2976: 10 00 d0 44 08 00 mov\.m r1=ar52 + 297c: 00 00 04 00 nop\.i 0x0;; + 2980: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2986: 10 00 d4 44 08 00 mov\.m r1=ar53 + 298c: 00 00 04 00 nop\.i 0x0;; + 2990: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2996: 10 00 d8 44 08 00 mov\.m r1=ar54 + 299c: 00 00 04 00 nop\.i 0x0;; + 29a0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 29a6: 10 00 dc 44 08 00 mov\.m r1=ar55 + 29ac: 00 00 04 00 nop\.i 0x0;; + 29b0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 29b6: 10 00 e0 44 08 00 mov\.m r1=ar56 + 29bc: 00 00 04 00 nop\.i 0x0;; + 29c0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 29c6: 10 00 e4 44 08 00 mov\.m r1=ar57 + 29cc: 00 00 04 00 nop\.i 0x0;; + 29d0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 29d6: 10 00 e8 44 08 00 mov\.m r1=ar58 + 29dc: 00 00 04 00 nop\.i 0x0;; + 29e0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 29e6: 10 00 ec 44 08 00 mov\.m r1=ar59 + 29ec: 00 00 04 00 nop\.i 0x0;; + 29f0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 29f6: 10 00 f0 44 08 00 mov\.m r1=ar60 + 29fc: 00 00 04 00 nop\.i 0x0;; + 2a00: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2a06: 10 00 f4 44 08 00 mov\.m r1=ar61 + 2a0c: 00 00 04 00 nop\.i 0x0;; + 2a10: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2a16: 10 00 f8 44 08 00 mov\.m r1=ar62 + 2a1c: 00 00 04 00 nop\.i 0x0;; + 2a20: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2a26: 10 00 fc 44 08 00 mov\.m r1=ar63 + 2a2c: 00 00 04 00 nop\.i 0x0;; + 2a30: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2a36: 00 00 00 02 00 20 nop\.m 0x0 + 2a3c: 00 00 ca 00 mov\.i r1=ar\.pfs;; + 2a40: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2a46: 00 00 00 02 00 20 nop\.m 0x0 + 2a4c: 00 08 ca 00 mov\.i r1=ar\.lc;; + 2a50: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2a56: 00 00 00 02 00 20 nop\.m 0x0 + 2a5c: 00 10 ca 00 mov\.i r1=ar\.ec;; + 2a60: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2a66: 00 00 00 02 00 20 nop\.m 0x0 + 2a6c: 00 80 cb 00 mov\.i r1=ar112;; + 2a70: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2a76: 00 00 00 02 00 20 nop\.m 0x0 + 2a7c: 00 88 cb 00 mov\.i r1=ar113;; + 2a80: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2a86: 00 00 00 02 00 20 nop\.m 0x0 + 2a8c: 00 90 cb 00 mov\.i r1=ar114;; + 2a90: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2a96: 00 00 00 02 00 20 nop\.m 0x0 + 2a9c: 00 98 cb 00 mov\.i r1=ar115;; + 2aa0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2aa6: 00 00 00 02 00 20 nop\.m 0x0 + 2aac: 00 a0 cb 00 mov\.i r1=ar116;; + 2ab0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2ab6: 00 00 00 02 00 20 nop\.m 0x0 + 2abc: 00 a8 cb 00 mov\.i r1=ar117;; + 2ac0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2ac6: 00 00 00 02 00 20 nop\.m 0x0 + 2acc: 00 b0 cb 00 mov\.i r1=ar118;; + 2ad0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2ad6: 00 00 00 02 00 20 nop\.m 0x0 + 2adc: 00 b8 cb 00 mov\.i r1=ar119;; + 2ae0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2ae6: 00 00 00 02 00 20 nop\.m 0x0 + 2aec: 00 c0 cb 00 mov\.i r1=ar120;; + 2af0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2af6: 00 00 00 02 00 20 nop\.m 0x0 + 2afc: 00 c8 cb 00 mov\.i r1=ar121;; + 2b00: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2b06: 00 00 00 02 00 20 nop\.m 0x0 + 2b0c: 00 d0 cb 00 mov\.i r1=ar122;; + 2b10: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2b16: 00 00 00 02 00 20 nop\.m 0x0 + 2b1c: 00 d8 cb 00 mov\.i r1=ar123;; + 2b20: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2b26: 00 00 00 02 00 20 nop\.m 0x0 + 2b2c: 00 e0 cb 00 mov\.i r1=ar124;; + 2b30: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2b36: 00 00 00 02 00 20 nop\.m 0x0 + 2b3c: 00 e8 cb 00 mov\.i r1=ar125;; + 2b40: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2b46: 00 00 00 02 00 20 nop\.m 0x0 + 2b4c: 00 f0 cb 00 mov\.i r1=ar126;; + 2b50: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2b56: 00 00 00 02 00 20 nop\.m 0x0 + 2b5c: 00 f8 cb 00 mov\.i r1=ar127;; + 2b60: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2b66: 10 00 00 44 08 00 mov\.m r1=ar\.k0 + 2b6c: 00 00 04 00 nop\.i 0x0;; + 2b70: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2b76: 10 00 04 44 08 00 mov\.m r1=ar\.k1 + 2b7c: 00 00 04 00 nop\.i 0x0;; + 2b80: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2b86: 10 00 08 44 08 00 mov\.m r1=ar\.k2 + 2b8c: 00 00 04 00 nop\.i 0x0;; + 2b90: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2b96: 10 00 0c 44 08 00 mov\.m r1=ar\.k3 + 2b9c: 00 00 04 00 nop\.i 0x0;; + 2ba0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2ba6: 10 00 10 44 08 00 mov\.m r1=ar\.k4 + 2bac: 00 00 04 00 nop\.i 0x0;; + 2bb0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2bb6: 10 00 14 44 08 00 mov\.m r1=ar\.k5 + 2bbc: 00 00 04 00 nop\.i 0x0;; + 2bc0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2bc6: 10 00 18 44 08 00 mov\.m r1=ar\.k6 + 2bcc: 00 00 04 00 nop\.i 0x0;; + 2bd0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2bd6: 10 00 1c 44 08 00 mov\.m r1=ar\.k7 + 2bdc: 00 00 04 00 nop\.i 0x0;; + 2be0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2be6: 10 00 40 44 08 00 mov\.m r1=ar\.rsc + 2bec: 00 00 04 00 nop\.i 0x0;; + 2bf0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2bf6: 10 00 44 44 08 00 mov\.m r1=ar\.bsp + 2bfc: 00 00 04 00 nop\.i 0x0;; + 2c00: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2c06: 10 00 48 44 08 00 mov\.m r1=ar\.bspstore + 2c0c: 00 00 04 00 nop\.i 0x0;; + 2c10: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2c16: 10 00 4c 44 08 00 mov\.m r1=ar\.rnat + 2c1c: 00 00 04 00 nop\.i 0x0;; + 2c20: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2c26: 10 00 80 44 08 00 mov\.m r1=ar\.ccv + 2c2c: 00 00 04 00 nop\.i 0x0;; + 2c30: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2c36: 10 00 90 44 08 00 mov\.m r1=ar\.unat + 2c3c: 00 00 04 00 nop\.i 0x0;; + 2c40: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2c46: 10 00 a0 44 08 00 mov\.m r1=ar\.fpsr + 2c4c: 00 00 04 00 nop\.i 0x0;; + 2c50: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2c56: 10 00 b0 44 08 00 mov\.m r1=ar\.itc + 2c5c: 00 00 04 00 nop\.i 0x0;; + 2c60: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2c66: 00 00 00 02 00 20 nop\.m 0x0 + 2c6c: 00 00 ca 00 mov\.i r1=ar\.pfs;; + 2c70: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2c76: 00 00 00 02 00 20 nop\.m 0x0 + 2c7c: 00 08 ca 00 mov\.i r1=ar\.lc;; + 2c80: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2c86: 00 00 00 02 00 20 nop\.m 0x0 + 2c8c: 00 10 ca 00 mov\.i r1=ar\.ec;; + 2c90: 1d 08 00 00 24 04 \[MFB\] mov r1=cr0 + 2c96: 00 00 00 02 00 00 nop\.f 0x0 + 2c9c: 00 00 00 20 nop\.b 0x0;; + 2ca0: 1d 08 00 02 24 04 \[MFB\] mov r1=cr1 + 2ca6: 00 00 00 02 00 00 nop\.f 0x0 + 2cac: 00 00 00 20 nop\.b 0x0;; + 2cb0: 1d 08 00 04 24 04 \[MFB\] mov r1=cr2 + 2cb6: 00 00 00 02 00 00 nop\.f 0x0 + 2cbc: 00 00 00 20 nop\.b 0x0;; + 2cc0: 1d 08 00 10 24 04 \[MFB\] mov r1=cr8 + 2cc6: 00 00 00 02 00 00 nop\.f 0x0 + 2ccc: 00 00 00 20 nop\.b 0x0;; + 2cd0: 1d 08 00 12 24 04 \[MFB\] mov r1=cr9 + 2cd6: 00 00 00 02 00 00 nop\.f 0x0 + 2cdc: 00 00 00 20 nop\.b 0x0;; + 2ce0: 1d 08 00 20 24 04 \[MFB\] mov r1=cr16 + 2ce6: 00 00 00 02 00 00 nop\.f 0x0 + 2cec: 00 00 00 20 nop\.b 0x0;; + 2cf0: 1d 08 00 22 24 04 \[MFB\] mov r1=cr17 + 2cf6: 00 00 00 02 00 00 nop\.f 0x0 + 2cfc: 00 00 00 20 nop\.b 0x0;; + 2d00: 1d 08 00 26 24 04 \[MFB\] mov r1=cr19 + 2d06: 00 00 00 02 00 00 nop\.f 0x0 + 2d0c: 00 00 00 20 nop\.b 0x0;; + 2d10: 1d 08 00 28 24 04 \[MFB\] mov r1=cr20 + 2d16: 00 00 00 02 00 00 nop\.f 0x0 + 2d1c: 00 00 00 20 nop\.b 0x0;; + 2d20: 1d 08 00 2a 24 04 \[MFB\] mov r1=cr21 + 2d26: 00 00 00 02 00 00 nop\.f 0x0 + 2d2c: 00 00 00 20 nop\.b 0x0;; + 2d30: 1d 08 00 2c 24 04 \[MFB\] mov r1=cr22 + 2d36: 00 00 00 02 00 00 nop\.f 0x0 + 2d3c: 00 00 00 20 nop\.b 0x0;; + 2d40: 1d 08 00 2e 24 04 \[MFB\] mov r1=cr23 + 2d46: 00 00 00 02 00 00 nop\.f 0x0 + 2d4c: 00 00 00 20 nop\.b 0x0;; + 2d50: 1d 08 00 30 24 04 \[MFB\] mov r1=cr24 + 2d56: 00 00 00 02 00 00 nop\.f 0x0 + 2d5c: 00 00 00 20 nop\.b 0x0;; + 2d60: 1d 08 00 32 24 04 \[MFB\] mov r1=cr25 + 2d66: 00 00 00 02 00 00 nop\.f 0x0 + 2d6c: 00 00 00 20 nop\.b 0x0;; + 2d70: 1d 08 00 80 24 04 \[MFB\] mov r1=cr64 + 2d76: 00 00 00 02 00 00 nop\.f 0x0 + 2d7c: 00 00 00 20 nop\.b 0x0;; + 2d80: 1d 08 00 82 24 04 \[MFB\] mov r1=cr65 + 2d86: 00 00 00 02 00 00 nop\.f 0x0 + 2d8c: 00 00 00 20 nop\.b 0x0;; + 2d90: 1d 08 00 84 24 04 \[MFB\] mov r1=cr66 + 2d96: 00 00 00 02 00 00 nop\.f 0x0 + 2d9c: 00 00 00 20 nop\.b 0x0;; + 2da0: 1d 08 00 86 24 04 \[MFB\] mov r1=cr67 + 2da6: 00 00 00 02 00 00 nop\.f 0x0 + 2dac: 00 00 00 20 nop\.b 0x0;; + 2db0: 1d 08 00 88 24 04 \[MFB\] mov r1=cr68 + 2db6: 00 00 00 02 00 00 nop\.f 0x0 + 2dbc: 00 00 00 20 nop\.b 0x0;; + 2dc0: 1d 08 00 8a 24 04 \[MFB\] mov r1=cr69 + 2dc6: 00 00 00 02 00 00 nop\.f 0x0 + 2dcc: 00 00 00 20 nop\.b 0x0;; + 2dd0: 1d 08 00 8c 24 04 \[MFB\] mov r1=cr70 + 2dd6: 00 00 00 02 00 00 nop\.f 0x0 + 2ddc: 00 00 00 20 nop\.b 0x0;; + 2de0: 1d 08 00 8e 24 04 \[MFB\] mov r1=cr71 + 2de6: 00 00 00 02 00 00 nop\.f 0x0 + 2dec: 00 00 00 20 nop\.b 0x0;; + 2df0: 1d 08 00 90 24 04 \[MFB\] mov r1=cr72 + 2df6: 00 00 00 02 00 00 nop\.f 0x0 + 2dfc: 00 00 00 20 nop\.b 0x0;; + 2e00: 1d 08 00 92 24 04 \[MFB\] mov r1=cr73 + 2e06: 00 00 00 02 00 00 nop\.f 0x0 + 2e0c: 00 00 00 20 nop\.b 0x0;; + 2e10: 1d 08 00 94 24 04 \[MFB\] mov r1=cr74 + 2e16: 00 00 00 02 00 00 nop\.f 0x0 + 2e1c: 00 00 00 20 nop\.b 0x0;; + 2e20: 1d 08 00 a0 24 04 \[MFB\] mov r1=cr80 + 2e26: 00 00 00 02 00 00 nop\.f 0x0 + 2e2c: 00 00 00 20 nop\.b 0x0;; + 2e30: 1d 08 00 a2 24 04 \[MFB\] mov r1=cr81 + 2e36: 00 00 00 02 00 00 nop\.f 0x0 + 2e3c: 00 00 00 20 nop\.b 0x0;; + 2e40: 1d 08 00 00 24 04 \[MFB\] mov r1=cr0 + 2e46: 00 00 00 02 00 00 nop\.f 0x0 + 2e4c: 00 00 00 20 nop\.b 0x0;; + 2e50: 1d 08 00 02 24 04 \[MFB\] mov r1=cr1 + 2e56: 00 00 00 02 00 00 nop\.f 0x0 + 2e5c: 00 00 00 20 nop\.b 0x0;; + 2e60: 1d 08 00 04 24 04 \[MFB\] mov r1=cr2 + 2e66: 00 00 00 02 00 00 nop\.f 0x0 + 2e6c: 00 00 00 20 nop\.b 0x0;; + 2e70: 1d 08 00 10 24 04 \[MFB\] mov r1=cr8 + 2e76: 00 00 00 02 00 00 nop\.f 0x0 + 2e7c: 00 00 00 20 nop\.b 0x0;; + 2e80: 1d 08 00 20 24 04 \[MFB\] mov r1=cr16 + 2e86: 00 00 00 02 00 00 nop\.f 0x0 + 2e8c: 00 00 00 20 nop\.b 0x0;; + 2e90: 1d 08 00 22 24 04 \[MFB\] mov r1=cr17 + 2e96: 00 00 00 02 00 00 nop\.f 0x0 + 2e9c: 00 00 00 20 nop\.b 0x0;; + 2ea0: 1d 08 00 26 24 04 \[MFB\] mov r1=cr19 + 2ea6: 00 00 00 02 00 00 nop\.f 0x0 + 2eac: 00 00 00 20 nop\.b 0x0;; + 2eb0: 1d 08 00 2c 24 04 \[MFB\] mov r1=cr22 + 2eb6: 00 00 00 02 00 00 nop\.f 0x0 + 2ebc: 00 00 00 20 nop\.b 0x0;; + 2ec0: 1d 08 00 2e 24 04 \[MFB\] mov r1=cr23 + 2ec6: 00 00 00 02 00 00 nop\.f 0x0 + 2ecc: 00 00 00 20 nop\.b 0x0;; + 2ed0: 1d 08 00 30 24 04 \[MFB\] mov r1=cr24 + 2ed6: 00 00 00 02 00 00 nop\.f 0x0 + 2edc: 00 00 00 20 nop\.b 0x0;; + 2ee0: 1d 08 00 32 24 04 \[MFB\] mov r1=cr25 + 2ee6: 00 00 00 02 00 00 nop\.f 0x0 + 2eec: 00 00 00 20 nop\.b 0x0;; + 2ef0: 1d 08 00 80 24 04 \[MFB\] mov r1=cr64 + 2ef6: 00 00 00 02 00 00 nop\.f 0x0 + 2efc: 00 00 00 20 nop\.b 0x0;; + 2f00: 1d 08 00 82 24 04 \[MFB\] mov r1=cr65 + 2f06: 00 00 00 02 00 00 nop\.f 0x0 + 2f0c: 00 00 00 20 nop\.b 0x0;; + 2f10: 1d 08 00 84 24 04 \[MFB\] mov r1=cr66 + 2f16: 00 00 00 02 00 00 nop\.f 0x0 + 2f1c: 00 00 00 20 nop\.b 0x0;; + 2f20: 1d 08 00 86 24 04 \[MFB\] mov r1=cr67 + 2f26: 00 00 00 02 00 00 nop\.f 0x0 + 2f2c: 00 00 00 20 nop\.b 0x0;; + 2f30: 1d 08 00 88 24 04 \[MFB\] mov r1=cr68 + 2f36: 00 00 00 02 00 00 nop\.f 0x0 + 2f3c: 00 00 00 20 nop\.b 0x0;; + 2f40: 1d 08 00 8a 24 04 \[MFB\] mov r1=cr69 + 2f46: 00 00 00 02 00 00 nop\.f 0x0 + 2f4c: 00 00 00 20 nop\.b 0x0;; + 2f50: 1d 08 00 8c 24 04 \[MFB\] mov r1=cr70 + 2f56: 00 00 00 02 00 00 nop\.f 0x0 + 2f5c: 00 00 00 20 nop\.b 0x0;; + 2f60: 1d 08 00 8e 24 04 \[MFB\] mov r1=cr71 + 2f66: 00 00 00 02 00 00 nop\.f 0x0 + 2f6c: 00 00 00 20 nop\.b 0x0;; + 2f70: 1d 08 00 90 24 04 \[MFB\] mov r1=cr72 + 2f76: 00 00 00 02 00 00 nop\.f 0x0 + 2f7c: 00 00 00 20 nop\.b 0x0;; + 2f80: 1d 08 00 92 24 04 \[MFB\] mov r1=cr73 + 2f86: 00 00 00 02 00 00 nop\.f 0x0 + 2f8c: 00 00 00 20 nop\.b 0x0;; + 2f90: 1d 08 00 a0 24 04 \[MFB\] mov r1=cr80 + 2f96: 00 00 00 02 00 00 nop\.f 0x0 + 2f9c: 00 00 00 20 nop\.b 0x0;; + 2fa0: 1d 08 00 a2 24 04 \[MFB\] mov r1=cr81 + 2fa6: 00 00 00 02 00 00 nop\.f 0x0 + 2fac: 00 00 00 20 nop\.b 0x0;; + 2fb0: 1d 08 00 94 24 04 \[MFB\] mov r1=cr74 + 2fb6: 00 00 00 02 00 00 nop\.f 0x0 + 2fbc: 00 00 00 20 nop\.b 0x0;; + 2fc0: 1d 08 00 00 25 04 \[MFB\] mov r1=psr + 2fc6: 00 00 00 02 00 00 nop\.f 0x0 + 2fcc: 00 00 00 20 nop\.b 0x0;; + 2fd0: 1d 08 00 00 21 04 \[MFB\] mov r1=psr\.um + 2fd6: 00 00 00 02 00 00 nop\.f 0x0 + 2fdc: 00 00 00 20 nop\.b 0x0;; + 2fe0: 09 00 00 00 01 00 \[MMI\] nop\.m 0x0 + 2fe6: 00 00 00 02 00 20 nop\.m 0x0 + 2fec: 00 00 c0 00 mov r1=ip;; + 2ff0: 09 08 00 06 14 04 \[MMI\] mov r1=pmc\[r3\] + 2ff6: 20 00 10 28 08 00 mov r2=pmc\[r4\] + 2ffc: 00 00 04 00 nop\.i 0x0;; + 3000: 09 08 00 06 15 04 \[MMI\] mov r1=pmd\[r3\] + 3006: 20 00 10 2a 08 00 mov r2=pmd\[r4\] + 300c: 00 00 04 00 nop\.i 0x0;; + 3010: 09 08 00 06 13 04 \[MMI\] mov r1=pkr\[r3\] + 3016: 20 00 10 26 08 00 mov r2=pkr\[r4\] + 301c: 00 00 04 00 nop\.i 0x0;; + 3020: 09 08 00 06 10 04 \[MMI\] mov r1=rr\[r3\] + 3026: 20 00 10 20 08 00 mov r2=rr\[r4\] + 302c: 00 00 04 00 nop\.i 0x0;; + 3030: 09 08 00 06 12 04 \[MMI\] mov r1=ibr\[r3\] + 3036: 20 00 10 24 08 00 mov r2=ibr\[r4\] + 303c: 00 00 04 00 nop\.i 0x0;; + 3040: 09 08 00 06 11 04 \[MMI\] mov r1=dbr\[r3\] + 3046: 20 00 10 22 08 00 mov r2=dbr\[r4\] + 304c: 00 00 04 00 nop\.i 0x0;; + 3050: 09 08 00 06 17 04 \[MMI\] mov r1=cpuid\[r3\] + 3056: 20 00 10 2e 08 00 mov r2=cpuid\[r4\] + 305c: 00 00 04 00 nop\.i 0x0;; + 3060: 09 08 00 06 17 04 \[MMI\] mov r1=cpuid\[r3\] + 3066: 20 00 10 2e 08 00 mov r2=cpuid\[r4\] + 306c: 00 00 04 00 nop\.i 0x0;; diff --git a/gas/testsuite/gas/ia64/regs.pl b/gas/testsuite/gas/ia64/regs.pl new file mode 100644 index 0000000..ca51cc0 --- /dev/null +++ b/gas/testsuite/gas/ia64/regs.pl @@ -0,0 +1,150 @@ +print ".text\n"; +print "\t.type _start,@","function\n"; +print "_start:\n\n"; + +print "// Fixed and stacked integer registers.\n"; +for ($i = 1; $i < 128; ++$i) { + print "\t{ .mii; mov r$i = r0; nop.i 0; nop.i 0;; }\n"; +} +print "\n"; + +print "// Alternate names for input registers\n"; +print "\t.regstk 96, 0, 0, 0\n"; +for ($i = 0; $i < 96; ++$i) { + print "\t{ .mii; mov in$i = r0; nop.i 0; nop.i 0;; }\n"; +} +print "\n"; + +print "// Alternate names for output registers\n"; +print "\t.regstk 0, 0, 96, 0\n"; +for ($i = 0; $i < 96; ++$i) { + print "\t{ .mii; mov out$i = r0; nop.i 0; nop.i 0;; }\n"; +} +print "\n"; + +print "// Alternate names for local registers\n"; +print "\t.regstk 0, 96, 0, 0\n"; +for ($i = 0; $i < 96; ++$i) { + print "\t{ .mii; mov loc$i = r0; nop.i 0; nop.i 0;; }\n"; +} +print "\n"; + +print "// Return value registers\n"; +for ($i = 0; $i < 4; ++$i) { + print "\t{ .mii; mov ret$i = r0; nop.i 0; nop.i 0;; }\n"; +} +print "\n"; + +print "\t{ .mii;\n"; +print "\tmov gp = r0\n"; +print "\tmov sp = r0\n"; +print "\tnop.i 0;; }\n\n"; + +print "// Floating point registers\n"; +for ($i = 2; $i < 128; ++$i) { + print "\t{ .mfi; mov f$i = f0 ;; }\n"; +} +print "\n"; + +print "// Floating point argument registers\n"; +for ($i = 0; $i < 8; ++$i) { + print "\t{ .mfi; mov farg$i = f1 ;; }\n"; +} +print "\n"; + +print "// Floating point return value registers\n"; +for ($i = 0; $i < 8; ++$i) { + print "\t{ .mfi; mov fret$i = f1 ;; }\n"; +} +print "\n"; + +print "// Predicate registers\n"; +for ($i = 0; $i < 64; ++$i) { + print "\t{ .mii; (p$i)\tmov r", $i+1, " = r0; nop.i 0; nop.i 0;; }\n"; +} +print "\n"; + +print "// Predicates as a unit\n"; +print "\t{ .mmi; nop.m 0; mov r1 = pr ;; }\n"; +print "//\tmov r2 = pr.rot\n"; +print "\n"; + +print "// Branch registers.\n"; +for ($i = 0; $i < 8; ++$i) { + print "\t{ .mmi; mov b$i = r0;; }\n"; +} +print "\n"; + +print "\t{ .mmi; mov rp = r0;; }\n"; +print "\n"; + +print "// Application registers\n"; +@reserved = ( 8..15, 20, 22..23, 31, 33..35, 37..39, 41..47, 67..111 ); +%reserved = (); +foreach $i (@reserved) { + $reserved{$i} = 1; +} +for ($i = 0; $i < 128; ++$i) { + print "//" if $reserved{$i}; + print "\t{ .mmi; nop.m 0; mov r1 = ar$i ;; }"; + print "\t\t// reserved" if $reserved{$i}; + print "\n"; +} +print "\n"; + +print "// Application registers by name\n"; +for ($i = 0; $i < 8; ++$i) { + print "\t{ .mmi; nop.m 0; mov r1 = ar.k$i ;;}\n"; +} + +@regs = ( "rsc", "bsp", "bspstore", "rnat", "ccv", "unat", "fpsr", "itc", + "pfs", "lc", "ec" ); +foreach $i (@regs) { + print "\t{ .mmi; nop.m 0; mov r1 = ar.$i ;; }\n"; +} +print "\n"; + +print "// Control registers\n"; +@reserved = ( 3..7, 10..15, 18, 26..63, 75..79, 82..127 ); +%reserved = (); +foreach $i (@reserved) { + $reserved{$i} = 1; +} +for ($i = 0; $i < 128; ++$i) { + print "//" if $reserved{$i}; + print "\t{ .mfb; mov r1 = cr$i ;; }"; + print "\t\t// reserved" if $reserved{$i}; + print "\n"; +} +print "\n"; + +print "// Control registers by name\n"; +@regs = ( "dcr", "itm", "iva", "pta", "ipsr", "isr", "iip", + "iipa", "ifs", "iim", "iha", "lid", "ivr", + "tpr", "eoi", "irr0", "irr1", "irr2", "irr3", "itv", "pmv", + "lrr0", "lrr1", "cmcv" ); +# ias doesn't accept these, despite documentation to the contrary. +# push @regs, "ida", "idtr", "iitr" +foreach $i (@regs) { + print "\t{ .mfb; mov r1 = cr.$i ;; }\n"; +} +print "\n"; + + +print "// Other registers\n"; +print "\t{ .mfb; mov r1 = psr ;; }\n"; +print "//\t{ .mfb; mov r1 = psr.l ;; }\n"; +print "\t{ .mfb; mov r1 = psr.um ;; }\n"; +print "\t{ .mmi; mov r1 = ip ;; }\n"; +print "\n"; + +print "// Indirect register files\n"; +@regs = ("pmc", "pmd", "pkr", "rr", "ibr", "dbr", "CPUID", "cpuid"); +# ias doesn't accept these, despite documentation to the contrary. +# push @regs, "itr", "dtr"; +foreach $i (@regs) { + print "\t{ .mmi\n"; + print "\tmov r1 = ${i}[r3]\n"; + print "\tmov r2 = ${i}[r4]\n"; + print "\tnop.i 0;; }\n"; +} diff --git a/gas/testsuite/gas/ia64/regs.s b/gas/testsuite/gas/ia64/regs.s new file mode 100644 index 0000000..06226a5 --- /dev/null +++ b/gas/testsuite/gas/ia64/regs.s @@ -0,0 +1,1017 @@ +.text + .type _start,@function +_start: + +// Fixed and stacked integer registers. + { .mii; mov r1 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r2 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r3 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r4 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r5 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r6 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r7 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r8 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r9 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r10 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r11 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r12 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r13 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r14 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r15 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r16 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r17 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r18 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r19 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r20 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r21 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r22 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r23 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r24 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r25 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r26 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r27 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r28 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r29 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r30 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r31 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r32 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r33 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r34 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r35 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r36 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r37 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r38 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r39 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r40 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r41 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r42 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r43 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r44 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r45 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r46 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r47 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r48 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r49 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r50 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r51 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r52 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r53 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r54 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r55 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r56 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r57 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r58 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r59 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r60 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r61 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r62 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r63 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r64 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r65 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r66 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r67 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r68 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r69 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r70 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r71 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r72 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r73 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r74 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r75 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r76 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r77 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r78 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r79 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r80 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r81 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r82 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r83 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r84 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r85 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r86 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r87 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r88 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r89 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r90 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r91 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r92 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r93 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r94 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r95 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r96 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r97 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r98 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r99 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r100 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r101 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r102 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r103 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r104 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r105 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r106 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r107 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r108 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r109 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r110 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r111 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r112 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r113 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r114 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r115 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r116 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r117 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r118 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r119 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r120 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r121 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r122 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r123 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r124 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r125 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r126 = r0; nop.i 0; nop.i 0;; } + { .mii; mov r127 = r0; nop.i 0; nop.i 0;; } + +// Alternate names for input registers + .regstk 96, 0, 0, 0 + { .mii; mov in0 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in1 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in2 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in3 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in4 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in5 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in6 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in7 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in8 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in9 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in10 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in11 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in12 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in13 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in14 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in15 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in16 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in17 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in18 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in19 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in20 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in21 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in22 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in23 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in24 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in25 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in26 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in27 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in28 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in29 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in30 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in31 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in32 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in33 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in34 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in35 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in36 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in37 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in38 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in39 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in40 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in41 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in42 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in43 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in44 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in45 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in46 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in47 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in48 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in49 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in50 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in51 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in52 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in53 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in54 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in55 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in56 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in57 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in58 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in59 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in60 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in61 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in62 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in63 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in64 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in65 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in66 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in67 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in68 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in69 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in70 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in71 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in72 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in73 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in74 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in75 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in76 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in77 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in78 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in79 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in80 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in81 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in82 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in83 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in84 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in85 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in86 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in87 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in88 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in89 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in90 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in91 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in92 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in93 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in94 = r0; nop.i 0; nop.i 0;; } + { .mii; mov in95 = r0; nop.i 0; nop.i 0;; } + +// Alternate names for output registers + .regstk 0, 0, 96, 0 + { .mii; mov out0 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out1 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out2 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out3 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out4 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out5 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out6 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out7 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out8 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out9 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out10 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out11 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out12 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out13 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out14 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out15 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out16 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out17 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out18 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out19 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out20 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out21 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out22 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out23 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out24 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out25 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out26 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out27 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out28 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out29 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out30 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out31 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out32 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out33 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out34 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out35 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out36 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out37 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out38 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out39 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out40 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out41 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out42 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out43 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out44 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out45 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out46 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out47 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out48 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out49 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out50 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out51 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out52 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out53 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out54 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out55 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out56 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out57 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out58 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out59 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out60 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out61 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out62 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out63 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out64 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out65 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out66 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out67 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out68 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out69 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out70 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out71 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out72 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out73 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out74 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out75 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out76 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out77 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out78 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out79 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out80 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out81 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out82 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out83 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out84 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out85 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out86 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out87 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out88 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out89 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out90 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out91 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out92 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out93 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out94 = r0; nop.i 0; nop.i 0;; } + { .mii; mov out95 = r0; nop.i 0; nop.i 0;; } + +// Alternate names for local registers + .regstk 0, 96, 0, 0 + { .mii; mov loc0 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc1 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc2 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc3 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc4 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc5 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc6 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc7 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc8 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc9 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc10 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc11 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc12 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc13 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc14 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc15 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc16 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc17 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc18 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc19 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc20 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc21 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc22 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc23 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc24 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc25 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc26 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc27 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc28 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc29 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc30 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc31 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc32 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc33 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc34 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc35 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc36 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc37 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc38 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc39 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc40 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc41 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc42 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc43 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc44 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc45 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc46 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc47 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc48 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc49 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc50 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc51 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc52 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc53 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc54 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc55 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc56 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc57 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc58 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc59 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc60 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc61 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc62 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc63 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc64 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc65 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc66 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc67 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc68 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc69 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc70 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc71 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc72 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc73 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc74 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc75 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc76 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc77 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc78 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc79 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc80 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc81 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc82 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc83 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc84 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc85 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc86 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc87 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc88 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc89 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc90 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc91 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc92 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc93 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc94 = r0; nop.i 0; nop.i 0;; } + { .mii; mov loc95 = r0; nop.i 0; nop.i 0;; } + +// Return value registers + { .mii; mov ret0 = r0; nop.i 0; nop.i 0;; } + { .mii; mov ret1 = r0; nop.i 0; nop.i 0;; } + { .mii; mov ret2 = r0; nop.i 0; nop.i 0;; } + { .mii; mov ret3 = r0; nop.i 0; nop.i 0;; } + + { .mii; + mov gp = r0 + mov sp = r0 + nop.i 0;; } + +// Floating point registers + { .mfi; mov f2 = f0 ;; } + { .mfi; mov f3 = f0 ;; } + { .mfi; mov f4 = f0 ;; } + { .mfi; mov f5 = f0 ;; } + { .mfi; mov f6 = f0 ;; } + { .mfi; mov f7 = f0 ;; } + { .mfi; mov f8 = f0 ;; } + { .mfi; mov f9 = f0 ;; } + { .mfi; mov f10 = f0 ;; } + { .mfi; mov f11 = f0 ;; } + { .mfi; mov f12 = f0 ;; } + { .mfi; mov f13 = f0 ;; } + { .mfi; mov f14 = f0 ;; } + { .mfi; mov f15 = f0 ;; } + { .mfi; mov f16 = f0 ;; } + { .mfi; mov f17 = f0 ;; } + { .mfi; mov f18 = f0 ;; } + { .mfi; mov f19 = f0 ;; } + { .mfi; mov f20 = f0 ;; } + { .mfi; mov f21 = f0 ;; } + { .mfi; mov f22 = f0 ;; } + { .mfi; mov f23 = f0 ;; } + { .mfi; mov f24 = f0 ;; } + { .mfi; mov f25 = f0 ;; } + { .mfi; mov f26 = f0 ;; } + { .mfi; mov f27 = f0 ;; } + { .mfi; mov f28 = f0 ;; } + { .mfi; mov f29 = f0 ;; } + { .mfi; mov f30 = f0 ;; } + { .mfi; mov f31 = f0 ;; } + { .mfi; mov f32 = f0 ;; } + { .mfi; mov f33 = f0 ;; } + { .mfi; mov f34 = f0 ;; } + { .mfi; mov f35 = f0 ;; } + { .mfi; mov f36 = f0 ;; } + { .mfi; mov f37 = f0 ;; } + { .mfi; mov f38 = f0 ;; } + { .mfi; mov f39 = f0 ;; } + { .mfi; mov f40 = f0 ;; } + { .mfi; mov f41 = f0 ;; } + { .mfi; mov f42 = f0 ;; } + { .mfi; mov f43 = f0 ;; } + { .mfi; mov f44 = f0 ;; } + { .mfi; mov f45 = f0 ;; } + { .mfi; mov f46 = f0 ;; } + { .mfi; mov f47 = f0 ;; } + { .mfi; mov f48 = f0 ;; } + { .mfi; mov f49 = f0 ;; } + { .mfi; mov f50 = f0 ;; } + { .mfi; mov f51 = f0 ;; } + { .mfi; mov f52 = f0 ;; } + { .mfi; mov f53 = f0 ;; } + { .mfi; mov f54 = f0 ;; } + { .mfi; mov f55 = f0 ;; } + { .mfi; mov f56 = f0 ;; } + { .mfi; mov f57 = f0 ;; } + { .mfi; mov f58 = f0 ;; } + { .mfi; mov f59 = f0 ;; } + { .mfi; mov f60 = f0 ;; } + { .mfi; mov f61 = f0 ;; } + { .mfi; mov f62 = f0 ;; } + { .mfi; mov f63 = f0 ;; } + { .mfi; mov f64 = f0 ;; } + { .mfi; mov f65 = f0 ;; } + { .mfi; mov f66 = f0 ;; } + { .mfi; mov f67 = f0 ;; } + { .mfi; mov f68 = f0 ;; } + { .mfi; mov f69 = f0 ;; } + { .mfi; mov f70 = f0 ;; } + { .mfi; mov f71 = f0 ;; } + { .mfi; mov f72 = f0 ;; } + { .mfi; mov f73 = f0 ;; } + { .mfi; mov f74 = f0 ;; } + { .mfi; mov f75 = f0 ;; } + { .mfi; mov f76 = f0 ;; } + { .mfi; mov f77 = f0 ;; } + { .mfi; mov f78 = f0 ;; } + { .mfi; mov f79 = f0 ;; } + { .mfi; mov f80 = f0 ;; } + { .mfi; mov f81 = f0 ;; } + { .mfi; mov f82 = f0 ;; } + { .mfi; mov f83 = f0 ;; } + { .mfi; mov f84 = f0 ;; } + { .mfi; mov f85 = f0 ;; } + { .mfi; mov f86 = f0 ;; } + { .mfi; mov f87 = f0 ;; } + { .mfi; mov f88 = f0 ;; } + { .mfi; mov f89 = f0 ;; } + { .mfi; mov f90 = f0 ;; } + { .mfi; mov f91 = f0 ;; } + { .mfi; mov f92 = f0 ;; } + { .mfi; mov f93 = f0 ;; } + { .mfi; mov f94 = f0 ;; } + { .mfi; mov f95 = f0 ;; } + { .mfi; mov f96 = f0 ;; } + { .mfi; mov f97 = f0 ;; } + { .mfi; mov f98 = f0 ;; } + { .mfi; mov f99 = f0 ;; } + { .mfi; mov f100 = f0 ;; } + { .mfi; mov f101 = f0 ;; } + { .mfi; mov f102 = f0 ;; } + { .mfi; mov f103 = f0 ;; } + { .mfi; mov f104 = f0 ;; } + { .mfi; mov f105 = f0 ;; } + { .mfi; mov f106 = f0 ;; } + { .mfi; mov f107 = f0 ;; } + { .mfi; mov f108 = f0 ;; } + { .mfi; mov f109 = f0 ;; } + { .mfi; mov f110 = f0 ;; } + { .mfi; mov f111 = f0 ;; } + { .mfi; mov f112 = f0 ;; } + { .mfi; mov f113 = f0 ;; } + { .mfi; mov f114 = f0 ;; } + { .mfi; mov f115 = f0 ;; } + { .mfi; mov f116 = f0 ;; } + { .mfi; mov f117 = f0 ;; } + { .mfi; mov f118 = f0 ;; } + { .mfi; mov f119 = f0 ;; } + { .mfi; mov f120 = f0 ;; } + { .mfi; mov f121 = f0 ;; } + { .mfi; mov f122 = f0 ;; } + { .mfi; mov f123 = f0 ;; } + { .mfi; mov f124 = f0 ;; } + { .mfi; mov f125 = f0 ;; } + { .mfi; mov f126 = f0 ;; } + { .mfi; mov f127 = f0 ;; } + +// Floating point argument registers + { .mfi; mov farg0 = f1 ;; } + { .mfi; mov farg1 = f1 ;; } + { .mfi; mov farg2 = f1 ;; } + { .mfi; mov farg3 = f1 ;; } + { .mfi; mov farg4 = f1 ;; } + { .mfi; mov farg5 = f1 ;; } + { .mfi; mov farg6 = f1 ;; } + { .mfi; mov farg7 = f1 ;; } + +// Floating point return value registers + { .mfi; mov fret0 = f1 ;; } + { .mfi; mov fret1 = f1 ;; } + { .mfi; mov fret2 = f1 ;; } + { .mfi; mov fret3 = f1 ;; } + { .mfi; mov fret4 = f1 ;; } + { .mfi; mov fret5 = f1 ;; } + { .mfi; mov fret6 = f1 ;; } + { .mfi; mov fret7 = f1 ;; } + +// Predicate registers + { .mii; (p0) mov r1 = r0; nop.i 0; nop.i 0;; } + { .mii; (p1) mov r2 = r0; nop.i 0; nop.i 0;; } + { .mii; (p2) mov r3 = r0; nop.i 0; nop.i 0;; } + { .mii; (p3) mov r4 = r0; nop.i 0; nop.i 0;; } + { .mii; (p4) mov r5 = r0; nop.i 0; nop.i 0;; } + { .mii; (p5) mov r6 = r0; nop.i 0; nop.i 0;; } + { .mii; (p6) mov r7 = r0; nop.i 0; nop.i 0;; } + { .mii; (p7) mov r8 = r0; nop.i 0; nop.i 0;; } + { .mii; (p8) mov r9 = r0; nop.i 0; nop.i 0;; } + { .mii; (p9) mov r10 = r0; nop.i 0; nop.i 0;; } + { .mii; (p10) mov r11 = r0; nop.i 0; nop.i 0;; } + { .mii; (p11) mov r12 = r0; nop.i 0; nop.i 0;; } + { .mii; (p12) mov r13 = r0; nop.i 0; nop.i 0;; } + { .mii; (p13) mov r14 = r0; nop.i 0; nop.i 0;; } + { .mii; (p14) mov r15 = r0; nop.i 0; nop.i 0;; } + { .mii; (p15) mov r16 = r0; nop.i 0; nop.i 0;; } + { .mii; (p16) mov r17 = r0; nop.i 0; nop.i 0;; } + { .mii; (p17) mov r18 = r0; nop.i 0; nop.i 0;; } + { .mii; (p18) mov r19 = r0; nop.i 0; nop.i 0;; } + { .mii; (p19) mov r20 = r0; nop.i 0; nop.i 0;; } + { .mii; (p20) mov r21 = r0; nop.i 0; nop.i 0;; } + { .mii; (p21) mov r22 = r0; nop.i 0; nop.i 0;; } + { .mii; (p22) mov r23 = r0; nop.i 0; nop.i 0;; } + { .mii; (p23) mov r24 = r0; nop.i 0; nop.i 0;; } + { .mii; (p24) mov r25 = r0; nop.i 0; nop.i 0;; } + { .mii; (p25) mov r26 = r0; nop.i 0; nop.i 0;; } + { .mii; (p26) mov r27 = r0; nop.i 0; nop.i 0;; } + { .mii; (p27) mov r28 = r0; nop.i 0; nop.i 0;; } + { .mii; (p28) mov r29 = r0; nop.i 0; nop.i 0;; } + { .mii; (p29) mov r30 = r0; nop.i 0; nop.i 0;; } + { .mii; (p30) mov r31 = r0; nop.i 0; nop.i 0;; } + { .mii; (p31) mov r32 = r0; nop.i 0; nop.i 0;; } + { .mii; (p32) mov r33 = r0; nop.i 0; nop.i 0;; } + { .mii; (p33) mov r34 = r0; nop.i 0; nop.i 0;; } + { .mii; (p34) mov r35 = r0; nop.i 0; nop.i 0;; } + { .mii; (p35) mov r36 = r0; nop.i 0; nop.i 0;; } + { .mii; (p36) mov r37 = r0; nop.i 0; nop.i 0;; } + { .mii; (p37) mov r38 = r0; nop.i 0; nop.i 0;; } + { .mii; (p38) mov r39 = r0; nop.i 0; nop.i 0;; } + { .mii; (p39) mov r40 = r0; nop.i 0; nop.i 0;; } + { .mii; (p40) mov r41 = r0; nop.i 0; nop.i 0;; } + { .mii; (p41) mov r42 = r0; nop.i 0; nop.i 0;; } + { .mii; (p42) mov r43 = r0; nop.i 0; nop.i 0;; } + { .mii; (p43) mov r44 = r0; nop.i 0; nop.i 0;; } + { .mii; (p44) mov r45 = r0; nop.i 0; nop.i 0;; } + { .mii; (p45) mov r46 = r0; nop.i 0; nop.i 0;; } + { .mii; (p46) mov r47 = r0; nop.i 0; nop.i 0;; } + { .mii; (p47) mov r48 = r0; nop.i 0; nop.i 0;; } + { .mii; (p48) mov r49 = r0; nop.i 0; nop.i 0;; } + { .mii; (p49) mov r50 = r0; nop.i 0; nop.i 0;; } + { .mii; (p50) mov r51 = r0; nop.i 0; nop.i 0;; } + { .mii; (p51) mov r52 = r0; nop.i 0; nop.i 0;; } + { .mii; (p52) mov r53 = r0; nop.i 0; nop.i 0;; } + { .mii; (p53) mov r54 = r0; nop.i 0; nop.i 0;; } + { .mii; (p54) mov r55 = r0; nop.i 0; nop.i 0;; } + { .mii; (p55) mov r56 = r0; nop.i 0; nop.i 0;; } + { .mii; (p56) mov r57 = r0; nop.i 0; nop.i 0;; } + { .mii; (p57) mov r58 = r0; nop.i 0; nop.i 0;; } + { .mii; (p58) mov r59 = r0; nop.i 0; nop.i 0;; } + { .mii; (p59) mov r60 = r0; nop.i 0; nop.i 0;; } + { .mii; (p60) mov r61 = r0; nop.i 0; nop.i 0;; } + { .mii; (p61) mov r62 = r0; nop.i 0; nop.i 0;; } + { .mii; (p62) mov r63 = r0; nop.i 0; nop.i 0;; } + { .mii; (p63) mov r64 = r0; nop.i 0; nop.i 0;; } + +// Predicates as a unit + { .mmi; nop.m 0; mov r1 = pr ;; } +// mov r2 = pr.rot + +// Branch registers. + { .mmi; mov b0 = r0;; } + { .mmi; mov b1 = r0;; } + { .mmi; mov b2 = r0;; } + { .mmi; mov b3 = r0;; } + { .mmi; mov b4 = r0;; } + { .mmi; mov b5 = r0;; } + { .mmi; mov b6 = r0;; } + { .mmi; mov b7 = r0;; } + + { .mmi; mov rp = r0;; } + +// Application registers + { .mmi; nop.m 0; mov r1 = ar0 ;; } + { .mmi; nop.m 0; mov r1 = ar1 ;; } + { .mmi; nop.m 0; mov r1 = ar2 ;; } + { .mmi; nop.m 0; mov r1 = ar3 ;; } + { .mmi; nop.m 0; mov r1 = ar4 ;; } + { .mmi; nop.m 0; mov r1 = ar5 ;; } + { .mmi; nop.m 0; mov r1 = ar6 ;; } + { .mmi; nop.m 0; mov r1 = ar7 ;; } +// { .mmi; nop.m 0; mov r1 = ar8 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar9 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar10 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar11 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar12 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar13 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar14 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar15 ;; } // reserved + { .mmi; nop.m 0; mov r1 = ar16 ;; } + { .mmi; nop.m 0; mov r1 = ar17 ;; } + { .mmi; nop.m 0; mov r1 = ar18 ;; } + { .mmi; nop.m 0; mov r1 = ar19 ;; } +// { .mmi; nop.m 0; mov r1 = ar20 ;; } // reserved + { .mmi; nop.m 0; mov r1 = ar21 ;; } +// { .mmi; nop.m 0; mov r1 = ar22 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar23 ;; } // reserved + { .mmi; nop.m 0; mov r1 = ar24 ;; } + { .mmi; nop.m 0; mov r1 = ar25 ;; } + { .mmi; nop.m 0; mov r1 = ar26 ;; } + { .mmi; nop.m 0; mov r1 = ar27 ;; } + { .mmi; nop.m 0; mov r1 = ar28 ;; } + { .mmi; nop.m 0; mov r1 = ar29 ;; } + { .mmi; nop.m 0; mov r1 = ar30 ;; } +// { .mmi; nop.m 0; mov r1 = ar31 ;; } // reserved + { .mmi; nop.m 0; mov r1 = ar32 ;; } +// { .mmi; nop.m 0; mov r1 = ar33 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar34 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar35 ;; } // reserved + { .mmi; nop.m 0; mov r1 = ar36 ;; } +// { .mmi; nop.m 0; mov r1 = ar37 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar38 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar39 ;; } // reserved + { .mmi; nop.m 0; mov r1 = ar40 ;; } +// { .mmi; nop.m 0; mov r1 = ar41 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar42 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar43 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar44 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar45 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar46 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar47 ;; } // reserved + { .mmi; nop.m 0; mov r1 = ar48 ;; } + { .mmi; nop.m 0; mov r1 = ar49 ;; } + { .mmi; nop.m 0; mov r1 = ar50 ;; } + { .mmi; nop.m 0; mov r1 = ar51 ;; } + { .mmi; nop.m 0; mov r1 = ar52 ;; } + { .mmi; nop.m 0; mov r1 = ar53 ;; } + { .mmi; nop.m 0; mov r1 = ar54 ;; } + { .mmi; nop.m 0; mov r1 = ar55 ;; } + { .mmi; nop.m 0; mov r1 = ar56 ;; } + { .mmi; nop.m 0; mov r1 = ar57 ;; } + { .mmi; nop.m 0; mov r1 = ar58 ;; } + { .mmi; nop.m 0; mov r1 = ar59 ;; } + { .mmi; nop.m 0; mov r1 = ar60 ;; } + { .mmi; nop.m 0; mov r1 = ar61 ;; } + { .mmi; nop.m 0; mov r1 = ar62 ;; } + { .mmi; nop.m 0; mov r1 = ar63 ;; } + { .mmi; nop.m 0; mov r1 = ar64 ;; } + { .mmi; nop.m 0; mov r1 = ar65 ;; } + { .mmi; nop.m 0; mov r1 = ar66 ;; } +// { .mmi; nop.m 0; mov r1 = ar67 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar68 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar69 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar70 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar71 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar72 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar73 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar74 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar75 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar76 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar77 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar78 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar79 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar80 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar81 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar82 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar83 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar84 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar85 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar86 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar87 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar88 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar89 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar90 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar91 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar92 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar93 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar94 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar95 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar96 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar97 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar98 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar99 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar100 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar101 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar102 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar103 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar104 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar105 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar106 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar107 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar108 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar109 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar110 ;; } // reserved +// { .mmi; nop.m 0; mov r1 = ar111 ;; } // reserved + { .mmi; nop.m 0; mov r1 = ar112 ;; } + { .mmi; nop.m 0; mov r1 = ar113 ;; } + { .mmi; nop.m 0; mov r1 = ar114 ;; } + { .mmi; nop.m 0; mov r1 = ar115 ;; } + { .mmi; nop.m 0; mov r1 = ar116 ;; } + { .mmi; nop.m 0; mov r1 = ar117 ;; } + { .mmi; nop.m 0; mov r1 = ar118 ;; } + { .mmi; nop.m 0; mov r1 = ar119 ;; } + { .mmi; nop.m 0; mov r1 = ar120 ;; } + { .mmi; nop.m 0; mov r1 = ar121 ;; } + { .mmi; nop.m 0; mov r1 = ar122 ;; } + { .mmi; nop.m 0; mov r1 = ar123 ;; } + { .mmi; nop.m 0; mov r1 = ar124 ;; } + { .mmi; nop.m 0; mov r1 = ar125 ;; } + { .mmi; nop.m 0; mov r1 = ar126 ;; } + { .mmi; nop.m 0; mov r1 = ar127 ;; } + +// Application registers by name + { .mmi; nop.m 0; mov r1 = ar.k0 ;;} + { .mmi; nop.m 0; mov r1 = ar.k1 ;;} + { .mmi; nop.m 0; mov r1 = ar.k2 ;;} + { .mmi; nop.m 0; mov r1 = ar.k3 ;;} + { .mmi; nop.m 0; mov r1 = ar.k4 ;;} + { .mmi; nop.m 0; mov r1 = ar.k5 ;;} + { .mmi; nop.m 0; mov r1 = ar.k6 ;;} + { .mmi; nop.m 0; mov r1 = ar.k7 ;;} + { .mmi; nop.m 0; mov r1 = ar.rsc ;; } + { .mmi; nop.m 0; mov r1 = ar.bsp ;; } + { .mmi; nop.m 0; mov r1 = ar.bspstore ;; } + { .mmi; nop.m 0; mov r1 = ar.rnat ;; } + { .mmi; nop.m 0; mov r1 = ar.ccv ;; } + { .mmi; nop.m 0; mov r1 = ar.unat ;; } + { .mmi; nop.m 0; mov r1 = ar.fpsr ;; } + { .mmi; nop.m 0; mov r1 = ar.itc ;; } + { .mmi; nop.m 0; mov r1 = ar.pfs ;; } + { .mmi; nop.m 0; mov r1 = ar.lc ;; } + { .mmi; nop.m 0; mov r1 = ar.ec ;; } + +// Control registers + { .mfb; mov r1 = cr0 ;; } + { .mfb; mov r1 = cr1 ;; } + { .mfb; mov r1 = cr2 ;; } +// { .mfb; mov r1 = cr3 ;; } // reserved +// { .mfb; mov r1 = cr4 ;; } // reserved +// { .mfb; mov r1 = cr5 ;; } // reserved +// { .mfb; mov r1 = cr6 ;; } // reserved +// { .mfb; mov r1 = cr7 ;; } // reserved + { .mfb; mov r1 = cr8 ;; } + { .mfb; mov r1 = cr9 ;; } +// { .mfb; mov r1 = cr10 ;; } // reserved +// { .mfb; mov r1 = cr11 ;; } // reserved +// { .mfb; mov r1 = cr12 ;; } // reserved +// { .mfb; mov r1 = cr13 ;; } // reserved +// { .mfb; mov r1 = cr14 ;; } // reserved +// { .mfb; mov r1 = cr15 ;; } // reserved + { .mfb; mov r1 = cr16 ;; } + { .mfb; mov r1 = cr17 ;; } +// { .mfb; mov r1 = cr18 ;; } // reserved + { .mfb; mov r1 = cr19 ;; } + { .mfb; mov r1 = cr20 ;; } + { .mfb; mov r1 = cr21 ;; } + { .mfb; mov r1 = cr22 ;; } + { .mfb; mov r1 = cr23 ;; } + { .mfb; mov r1 = cr24 ;; } + { .mfb; mov r1 = cr25 ;; } +// { .mfb; mov r1 = cr26 ;; } // reserved +// { .mfb; mov r1 = cr27 ;; } // reserved +// { .mfb; mov r1 = cr28 ;; } // reserved +// { .mfb; mov r1 = cr29 ;; } // reserved +// { .mfb; mov r1 = cr30 ;; } // reserved +// { .mfb; mov r1 = cr31 ;; } // reserved +// { .mfb; mov r1 = cr32 ;; } // reserved +// { .mfb; mov r1 = cr33 ;; } // reserved +// { .mfb; mov r1 = cr34 ;; } // reserved +// { .mfb; mov r1 = cr35 ;; } // reserved +// { .mfb; mov r1 = cr36 ;; } // reserved +// { .mfb; mov r1 = cr37 ;; } // reserved +// { .mfb; mov r1 = cr38 ;; } // reserved +// { .mfb; mov r1 = cr39 ;; } // reserved +// { .mfb; mov r1 = cr40 ;; } // reserved +// { .mfb; mov r1 = cr41 ;; } // reserved +// { .mfb; mov r1 = cr42 ;; } // reserved +// { .mfb; mov r1 = cr43 ;; } // reserved +// { .mfb; mov r1 = cr44 ;; } // reserved +// { .mfb; mov r1 = cr45 ;; } // reserved +// { .mfb; mov r1 = cr46 ;; } // reserved +// { .mfb; mov r1 = cr47 ;; } // reserved +// { .mfb; mov r1 = cr48 ;; } // reserved +// { .mfb; mov r1 = cr49 ;; } // reserved +// { .mfb; mov r1 = cr50 ;; } // reserved +// { .mfb; mov r1 = cr51 ;; } // reserved +// { .mfb; mov r1 = cr52 ;; } // reserved +// { .mfb; mov r1 = cr53 ;; } // reserved +// { .mfb; mov r1 = cr54 ;; } // reserved +// { .mfb; mov r1 = cr55 ;; } // reserved +// { .mfb; mov r1 = cr56 ;; } // reserved +// { .mfb; mov r1 = cr57 ;; } // reserved +// { .mfb; mov r1 = cr58 ;; } // reserved +// { .mfb; mov r1 = cr59 ;; } // reserved +// { .mfb; mov r1 = cr60 ;; } // reserved +// { .mfb; mov r1 = cr61 ;; } // reserved +// { .mfb; mov r1 = cr62 ;; } // reserved +// { .mfb; mov r1 = cr63 ;; } // reserved + { .mfb; mov r1 = cr64 ;; } + { .mfb; mov r1 = cr65 ;; } + { .mfb; mov r1 = cr66 ;; } + { .mfb; mov r1 = cr67 ;; } + { .mfb; mov r1 = cr68 ;; } + { .mfb; mov r1 = cr69 ;; } + { .mfb; mov r1 = cr70 ;; } + { .mfb; mov r1 = cr71 ;; } + { .mfb; mov r1 = cr72 ;; } + { .mfb; mov r1 = cr73 ;; } + { .mfb; mov r1 = cr74 ;; } +// { .mfb; mov r1 = cr75 ;; } // reserved +// { .mfb; mov r1 = cr76 ;; } // reserved +// { .mfb; mov r1 = cr77 ;; } // reserved +// { .mfb; mov r1 = cr78 ;; } // reserved +// { .mfb; mov r1 = cr79 ;; } // reserved + { .mfb; mov r1 = cr80 ;; } + { .mfb; mov r1 = cr81 ;; } +// { .mfb; mov r1 = cr82 ;; } // reserved +// { .mfb; mov r1 = cr83 ;; } // reserved +// { .mfb; mov r1 = cr84 ;; } // reserved +// { .mfb; mov r1 = cr85 ;; } // reserved +// { .mfb; mov r1 = cr86 ;; } // reserved +// { .mfb; mov r1 = cr87 ;; } // reserved +// { .mfb; mov r1 = cr88 ;; } // reserved +// { .mfb; mov r1 = cr89 ;; } // reserved +// { .mfb; mov r1 = cr90 ;; } // reserved +// { .mfb; mov r1 = cr91 ;; } // reserved +// { .mfb; mov r1 = cr92 ;; } // reserved +// { .mfb; mov r1 = cr93 ;; } // reserved +// { .mfb; mov r1 = cr94 ;; } // reserved +// { .mfb; mov r1 = cr95 ;; } // reserved +// { .mfb; mov r1 = cr96 ;; } // reserved +// { .mfb; mov r1 = cr97 ;; } // reserved +// { .mfb; mov r1 = cr98 ;; } // reserved +// { .mfb; mov r1 = cr99 ;; } // reserved +// { .mfb; mov r1 = cr100 ;; } // reserved +// { .mfb; mov r1 = cr101 ;; } // reserved +// { .mfb; mov r1 = cr102 ;; } // reserved +// { .mfb; mov r1 = cr103 ;; } // reserved +// { .mfb; mov r1 = cr104 ;; } // reserved +// { .mfb; mov r1 = cr105 ;; } // reserved +// { .mfb; mov r1 = cr106 ;; } // reserved +// { .mfb; mov r1 = cr107 ;; } // reserved +// { .mfb; mov r1 = cr108 ;; } // reserved +// { .mfb; mov r1 = cr109 ;; } // reserved +// { .mfb; mov r1 = cr110 ;; } // reserved +// { .mfb; mov r1 = cr111 ;; } // reserved +// { .mfb; mov r1 = cr112 ;; } // reserved +// { .mfb; mov r1 = cr113 ;; } // reserved +// { .mfb; mov r1 = cr114 ;; } // reserved +// { .mfb; mov r1 = cr115 ;; } // reserved +// { .mfb; mov r1 = cr116 ;; } // reserved +// { .mfb; mov r1 = cr117 ;; } // reserved +// { .mfb; mov r1 = cr118 ;; } // reserved +// { .mfb; mov r1 = cr119 ;; } // reserved +// { .mfb; mov r1 = cr120 ;; } // reserved +// { .mfb; mov r1 = cr121 ;; } // reserved +// { .mfb; mov r1 = cr122 ;; } // reserved +// { .mfb; mov r1 = cr123 ;; } // reserved +// { .mfb; mov r1 = cr124 ;; } // reserved +// { .mfb; mov r1 = cr125 ;; } // reserved +// { .mfb; mov r1 = cr126 ;; } // reserved +// { .mfb; mov r1 = cr127 ;; } // reserved + +// Control registers by name + { .mfb; mov r1 = cr.dcr ;; } + { .mfb; mov r1 = cr.itm ;; } + { .mfb; mov r1 = cr.iva ;; } + { .mfb; mov r1 = cr.pta ;; } + { .mfb; mov r1 = cr.ipsr ;; } + { .mfb; mov r1 = cr.isr ;; } + { .mfb; mov r1 = cr.iip ;; } + { .mfb; mov r1 = cr.iipa ;; } + { .mfb; mov r1 = cr.ifs ;; } + { .mfb; mov r1 = cr.iim ;; } + { .mfb; mov r1 = cr.iha ;; } + { .mfb; mov r1 = cr.lid ;; } + { .mfb; mov r1 = cr.ivr ;; } + { .mfb; mov r1 = cr.tpr ;; } + { .mfb; mov r1 = cr.eoi ;; } + { .mfb; mov r1 = cr.irr0 ;; } + { .mfb; mov r1 = cr.irr1 ;; } + { .mfb; mov r1 = cr.irr2 ;; } + { .mfb; mov r1 = cr.irr3 ;; } + { .mfb; mov r1 = cr.itv ;; } + { .mfb; mov r1 = cr.pmv ;; } + { .mfb; mov r1 = cr.lrr0 ;; } + { .mfb; mov r1 = cr.lrr1 ;; } + { .mfb; mov r1 = cr.cmcv ;; } + +// Other registers + { .mfb; mov r1 = psr ;; } +// { .mfb; mov r1 = psr.l ;; } + { .mfb; mov r1 = psr.um ;; } + { .mmi; mov r1 = ip ;; } + +// Indirect register files + { .mmi + mov r1 = pmc[r3] + mov r2 = pmc[r4] + nop.i 0;; } + { .mmi + mov r1 = pmd[r3] + mov r2 = pmd[r4] + nop.i 0;; } + { .mmi + mov r1 = pkr[r3] + mov r2 = pkr[r4] + nop.i 0;; } + { .mmi + mov r1 = rr[r3] + mov r2 = rr[r4] + nop.i 0;; } + { .mmi + mov r1 = ibr[r3] + mov r2 = ibr[r4] + nop.i 0;; } + { .mmi + mov r1 = dbr[r3] + mov r2 = dbr[r4] + nop.i 0;; } + { .mmi + mov r1 = CPUID[r3] + mov r2 = CPUID[r4] + nop.i 0;; } + { .mmi + mov r1 = cpuid[r3] + mov r2 = cpuid[r4] + nop.i 0;; } diff --git a/gas/testsuite/gas/vtable/vtable.exp b/gas/testsuite/gas/vtable/vtable.exp index 0d3e1bc..992f800 100644 --- a/gas/testsuite/gas/vtable/vtable.exp +++ b/gas/testsuite/gas/vtable/vtable.exp @@ -20,6 +20,10 @@ if { ([istarget "*-*-elf*"] && ![istarget *-*-linux*aout*] && ![istarget *-*-linux*oldld*] } then { + if {[istarget "ia64-*"]} then { + return + } + # not supported by D30V if {[istarget "d30v-*-*"]} { return |