diff options
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 39 | ||||
| -rw-r--r-- | gas/config/tc-mips.c | 673 | ||||
| -rw-r--r-- | gas/doc/as.texinfo | 15 | ||||
| -rw-r--r-- | gas/doc/c-mips.texi | 18 | ||||
| -rw-r--r-- | gas/po/gas.pot | 285 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/mips.exp | 1 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/mips32.d | 49 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/mips32.s | 63 |
8 files changed, 631 insertions, 512 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 9c8a3df..8de2b35 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -13,6 +13,45 @@ operand specifiers. Change warning generated by 'B' operand specifier to reflect its new multi-purpose usage. + * config/tc-mips.c (mips_set_options): Use ISA_UNKNOWN rather than + -1, and update comment. + (file_mips_isa): Likewise. + (mips_cpu): Use CPU_UNKNOWN rather than -1, and update comment. + (ISA_HAS_COPROC_DELAYS, ISA_HAS_64BIT_REGS, gpr_interlocks): Use + ISA_* constants rather than hard-coded numbers. + (mips_cpu_info): New structure. + (mips_cpu_info_table): New table describing CPU and ISA names + and numbers. + (mips_cpu_info_from_name, mips_cpu_info_from_isa, + mips_cpu_info_from_cpu): New functions. + (mips_isa_to_str): New function to get string for ISA name. + (mips_cpu_to_str): Convert to use mips_cpu_info_from_cpu, and + return const char *. + (md_begin): Redo CPU and ISA selection logic, using + mips_cpu_info_from_*. Convert to use ISA_* constants rather + than hard-coded numbers. + (append_insn, mips_emit_delays, macro, macro2): Convert to use + ISA_* constants rather than hard-coded numbers. + (mips_ip): Convert to use mips_isa_to_str to get ISA name. + (md_longopts): Delete OPTION_NO_MIPS32. + (md_parse_option): Convert to use ISA_* constants rather than + hard-coded numbers. Make OPTIONS_MIPS32 case treat MIPS32 + as an ISA. Delete OPTION_NO_MIPS32 case. Convert OPTION_MCPU + to use strcasecmp to recognize "default" and to use + mips_cpu_info_from_name to get CPU numbers from argument. + (md_show_usage): Move -mips32 so it's with the rest of the ISA + flags. Change 4Kc, 4Kp and 4Km CPU entries to just be + mips32-4k. + (s_mipsset): Accept ISA value 32. + * doc/as.texinfo: Clean up MIPS options summary slightly, + remove -no-mips32. Add note about -mips4 and -mips32 + specifying those ISA levels. Delete -mips32 and -no-mips32 + cpu flag descriptions. + * doc/c-mips.texi: Add -mips32 to list of ISA switches. Clean + up the supported CPU switch list, and replace 4Kc, 4Km, and + 4Kp entries with a single mips32-4k entry. Note that you can + use ".set mips32". + 2000-12-01 Joel Sherrill <joel@OARcorp.com> * configure.in (arm-*-rtems*, a29k-*rtems*, h8300-*-rtems*): diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 568d261..fb8c5e6 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -187,10 +187,13 @@ struct mips_set_options }; /* This is the struct we use to hold the current set of options. Note - that we must set the isa and mips16 fields to -1 to indicate that - they have not been initialized. */ + that we must set the isa field to ISA_UNKNOWN and the mips16 field to + -1 to indicate that they have not been initialized. */ -static struct mips_set_options mips_opts = { -1, -1, 0, 0, 0, 0, 0, 0 }; +static struct mips_set_options mips_opts = +{ + ISA_UNKNOWN, -1, 0, 0, 0, 0, 0, 0 +}; /* These variables are filled in with the masks of registers used. The object format code reads them and puts them in the appropriate @@ -199,10 +202,10 @@ unsigned long mips_gprmask; unsigned long mips_cprmask[4]; /* MIPS ISA we are using for this output file. */ -static int file_mips_isa; +static int file_mips_isa = ISA_UNKNOWN; -/* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ -static int mips_cpu = -1; +/* The CPU type we are using for this output file. */ +static int mips_cpu = CPU_UNKNOWN; /* The argument of the -mabi= flag. */ static char* mips_abi_string = 0; @@ -226,15 +229,15 @@ static int mips_gp32 = 0; also assume that ISAs which don't have delays for these insns, don't have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */ #define ISA_HAS_COPROC_DELAYS(ISA) ( \ - (ISA) == 1 \ - || (ISA) == 2 \ - || (ISA) == 3 \ + (ISA) == ISA_MIPS1 \ + || (ISA) == ISA_MIPS2 \ + || (ISA) == ISA_MIPS3 \ ) /* Return true if ISA supports 64 bit gp register instructions. */ #define ISA_HAS_64BIT_REGS(ISA) ( \ - (ISA) == 3 \ - || (ISA) == 4 \ + (ISA) == ISA_MIPS3 \ + || (ISA) == ISA_MIPS4 \ ) /* Whether the processor uses hardware interlocks to protect @@ -270,7 +273,7 @@ static int mips_gp32 = 0; /* Whether the processor uses hardware interlocks to protect reads from the GPRs, and thus does not require nops to be inserted. */ #define gpr_interlocks \ - (mips_opts.isa != 1 \ + (mips_opts.isa != ISA_MIPS1 \ || mips_cpu == CPU_R3900) /* As with other "interlocks" this is used by hardware that has FP @@ -706,9 +709,24 @@ static void s_mips_stab PARAMS ((int)); static void s_mips_weakext PARAMS ((int)); static void s_file PARAMS ((int)); static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); -static char *mips_cpu_to_str PARAMS ((int)); - +static const char *mips_isa_to_str PARAMS ((int)); +static const char *mips_cpu_to_str PARAMS ((int)); static int validate_mips_insn PARAMS ((const struct mips_opcode *)); + +/* Table and functions used to map between CPU/ISA names, and + ISA levels, and CPU numbers. */ + +struct mips_cpu_info +{ + const char *name; /* CPU or ISA name. */ + int is_isa; /* Is this an ISA? (If 0, a CPU.) */ + int isa; /* ISA level. */ + int cpu; /* CPU number (default CPU if ISA). */ +}; + +static const struct mips_cpu_info *mips_cpu_info_from_name PARAMS ((const char *)); +static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int)); +static const struct mips_cpu_info *mips_cpu_info_from_cpu PARAMS ((int)); /* Pseudo-op table. @@ -852,33 +870,34 @@ static boolean mips16_small, mips16_ext; static segT pdr_seg; #endif -static char * +static const char * +mips_isa_to_str (isa) + int isa; +{ + const struct mips_cpu_info *ci; + static char s[20]; + + ci = mips_cpu_info_from_isa (isa); + if (ci != NULL) + return (ci->name); + + sprintf (s, "ISA#%d", isa); + return s; +} + +static const char * mips_cpu_to_str (cpu) int cpu; { + const struct mips_cpu_info *ci; static char s[16]; - switch (cpu) - { - case CPU_R2000: return "R2000"; - case CPU_R3000: return "R3000"; - case CPU_R3900: return "R3900"; - case CPU_R4000: return "R4000"; - case CPU_R4010: return "R4010"; - case CPU_VR4100: return "VR4100"; - case CPU_R4111: return "R4111"; - case CPU_R4300: return "R4300"; - case CPU_R4400: return "R4400"; - case CPU_R4600: return "R4600"; - case CPU_R4650: return "R4650"; - case CPU_R5000: return "R5000"; - case CPU_R6000: return "R6000"; - case CPU_R8000: return "R8000"; - case CPU_R10000: return "R10000"; - case CPU_4K: return "4K"; - default: - sprintf (s, "%d", cpu); - return s; - } + + ci = mips_cpu_info_from_cpu (cpu); + if (ci != NULL) + return (ci->name); + + sprintf (s, "CPU#%d", cpu); + return s; } /* This function is called once, at assembler startup time. It should @@ -887,13 +906,14 @@ mips_cpu_to_str (cpu) void md_begin () { - boolean ok = false; register const char *retval = NULL; int i = 0; const char *cpu; char *a = NULL; int broken = 0; int mips_isa_from_cpu; + int target_cpu_had_mips16 = 0; + const struct mips_cpu_info *ci; /* GP relative stuff not working for PE */ if (strncmp (TARGET_OS, "pe", 2) == 0 @@ -913,130 +933,52 @@ md_begin () cpu = a; } - if (mips_cpu < 0) + if (strncmp (cpu, "mips16", sizeof "mips16" - 1) == 0) { - /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is - just the generic 'mips', in which case set mips_cpu based - on the given ISA, if any. */ - - if (strcmp (cpu, "mips") == 0) - { - if (mips_opts.isa < 0) - mips_cpu = CPU_R3000; - - else if (mips_opts.isa == 2) - mips_cpu = CPU_R6000; - - else if (mips_opts.isa == 3) - mips_cpu = CPU_R4000; - - else if (mips_opts.isa == 4) - mips_cpu = CPU_R8000; - - else - mips_cpu = CPU_R3000; - } - - else if (strcmp (cpu, "r3900") == 0 - || strcmp (cpu, "mipstx39") == 0 - ) - mips_cpu = CPU_R3900; - - else if (strcmp (cpu, "r6000") == 0 - || strcmp (cpu, "mips2") == 0) - mips_cpu = CPU_R6000; - - else if (strcmp (cpu, "mips64") == 0 - || strcmp (cpu, "r4000") == 0 - || strcmp (cpu, "mips3") == 0) - mips_cpu = CPU_R4000; - - else if (strcmp (cpu, "r4400") == 0) - mips_cpu = CPU_R4400; - - else if (strcmp (cpu, "mips64orion") == 0 - || strcmp (cpu, "r4600") == 0) - mips_cpu = CPU_R4600; - - else if (strcmp (cpu, "r4650") == 0) - mips_cpu = CPU_R4650; - - else if (strcmp (cpu, "mips64vr4300") == 0) - mips_cpu = CPU_R4300; - - else if (strcmp (cpu, "mips64vr4111") == 0) - mips_cpu = CPU_R4111; - - else if (strcmp (cpu, "mips64vr4100") == 0) - mips_cpu = CPU_VR4100; - - else if (strcmp (cpu, "r4010") == 0) - mips_cpu = CPU_R4010; - - else if (strcmp (cpu, "4Kc") == 0 - || strcmp (cpu, "4Kp") == 0 - || strcmp (cpu, "4Km") == 0) - mips_cpu = CPU_4K; - - else if (strcmp (cpu, "r5000") == 0 - || strcmp (cpu, "mips64vr5000") == 0) - mips_cpu = CPU_R5000; - - else if (strcmp (cpu, "r8000") == 0 - || strcmp (cpu, "mips4") == 0) - mips_cpu = CPU_R8000; - - else if (strcmp (cpu, "r10000") == 0) - mips_cpu = CPU_R10000; - - else if (strcmp (cpu, "mips16") == 0) - mips_cpu = 0; /* FIXME */ - - else - mips_cpu = CPU_R3000; + target_cpu_had_mips16 = 1; + cpu += sizeof "mips16" - 1; } - if (mips_cpu == CPU_R3000 - || mips_cpu == CPU_R3900) - mips_isa_from_cpu = 1; - - else if (mips_cpu == CPU_R6000 - || mips_cpu == CPU_R4010) - mips_isa_from_cpu = 2; - - else if (mips_cpu == CPU_R4000 - || mips_cpu == CPU_VR4100 - || mips_cpu == CPU_R4111 - || mips_cpu == CPU_R4400 - || mips_cpu == CPU_R4300 - || mips_cpu == CPU_R4600 - || mips_cpu == CPU_R4650) - mips_isa_from_cpu = 3; - - else if (mips_cpu == CPU_R5000 - || mips_cpu == CPU_R8000 - || mips_cpu == CPU_R10000) - mips_isa_from_cpu = 4; - - else - mips_isa_from_cpu = -1; + if (mips_opts.mips16 < 0) + mips_opts.mips16 = target_cpu_had_mips16; - if (mips_opts.isa == -1) + /* At this point, mips_cpu will either be CPU_UNKNOWN if no CPU was + specified on the command line, or some other value if one was. + Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on + the command line, or will be set otherwise if one was. */ + if (mips_cpu != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) { - if (mips_isa_from_cpu != -1) - mips_opts.isa = mips_isa_from_cpu; - else - mips_opts.isa = 1; + /* We have it all. There's nothing to do. */ } - - if (mips_opts.mips16 < 0) + else if (mips_cpu != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN) { - if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) - mips_opts.mips16 = 1; - else - mips_opts.mips16 = 0; + /* We have CPU, we need ISA. */ + ci = mips_cpu_info_from_cpu (mips_cpu); + assert (ci != NULL); + mips_opts.isa = ci->isa; + } + else if (mips_cpu == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) + { + /* We have ISA, we need default CPU. */ + ci = mips_cpu_info_from_isa (mips_opts.isa); + assert (ci != NULL); + mips_cpu = ci->cpu; + } + else + { + /* We need to set both ISA and CPU from target cpu. */ + ci = mips_cpu_info_from_name (cpu); + if (ci == NULL) + ci = mips_cpu_info_from_cpu (CPU_R3000); + assert (ci != NULL); + mips_opts.isa = ci->isa; + mips_cpu = ci->cpu; } + ci = mips_cpu_info_from_cpu (mips_cpu); + assert (ci != NULL); + mips_isa_from_cpu = ci->isa; + /* End of TARGET_CPU processing, get rid of malloced memory if necessary. */ cpu = NULL; @@ -1046,7 +988,7 @@ md_begin () a = NULL; } - if (mips_opts.isa == 1 && mips_trap) + if (mips_opts.isa == ISA_MIPS1 && mips_trap) as_bad (_("trap exception not supported at ISA 1")); /* Set the EABI kind based on the ISA before the user gets @@ -1057,37 +999,14 @@ md_begin () && 0 == strcmp (mips_abi_string,"eabi")) mips_eabi64 = 1; - if (mips_cpu != 0 && mips_cpu != -1) - { - ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_cpu); - - /* If they asked for mips1 or mips2 and a cpu that is - mips3 or greater, then mark the object file 32BITMODE. */ - if (mips_isa_from_cpu != -1 - && ! ISA_HAS_64BIT_REGS (mips_opts.isa) - && ISA_HAS_64BIT_REGS (mips_isa_from_cpu)) - mips_32bitmode = 1; - } - else - { - switch (mips_opts.isa) - { - case 1: - ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, CPU_R3000); - break; - case 2: - ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, CPU_R6000); - break; - case 3: - ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, CPU_R4000); - break; - case 4: - ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, CPU_R8000); - break; - } - } + /* If they asked for mips1 or mips2 and a cpu that is + mips3 or greater, then mark the object file 32BITMODE. */ + if (mips_isa_from_cpu != ISA_UNKNOWN + && ! ISA_HAS_64BIT_REGS (mips_opts.isa) + && ISA_HAS_64BIT_REGS (mips_isa_from_cpu)) + mips_32bitmode = 1; - if (! ok) + if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_cpu)) as_warn (_("Could not set architecture and machine")); file_mips_isa = mips_opts.isa; @@ -1549,7 +1468,7 @@ append_insn (place, ip, address_expr, reloc_type, unmatched_hi) && ISA_HAS_COPROC_DELAYS (mips_opts.isa) && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) && ! cop_interlocks) - || (mips_opts.isa == 1 + || (mips_opts.isa == ISA_MIPS1 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) { /* A generic coprocessor delay. The previous instruction @@ -2083,7 +2002,7 @@ append_insn (place, ip, address_expr, reloc_type, unmatched_hi) && ! gpr_interlocks && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) || (! mips_opts.mips16 - && mips_opts.isa == 1 + && mips_opts.isa == ISA_MIPS1 /* Itbl support may require additional care here. */ && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) /* We can not swap with a branch instruction. */ @@ -2419,7 +2338,7 @@ mips_emit_delays (insns) && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY)) || (! mips_opts.mips16 - && mips_opts.isa == 1 + && mips_opts.isa == ISA_MIPS1 && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY))) { @@ -5421,7 +5340,7 @@ macro (ip) s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); if (strcmp (s, ".lit8") == 0) { - if (mips_opts.isa != 1) + if (mips_opts.isa != ISA_MIPS1) { macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); @@ -5446,7 +5365,7 @@ macro (ip) macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); } - if (mips_opts.isa != 1) + if (mips_opts.isa != ISA_MIPS1) { macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); @@ -5473,7 +5392,7 @@ macro (ip) to adjust when loading from memory. */ r = BFD_RELOC_LO16; dob: - assert (mips_opts.isa == 1); + assert (mips_opts.isa == ISA_MIPS1); macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", target_big_endian ? treg + 1 : treg, (int) r, breg); @@ -5512,7 +5431,7 @@ macro (ip) } /* Itbl support may require additional care here. */ coproc = 1; - if (mips_opts.isa != 1) + if (mips_opts.isa != ISA_MIPS1) { s = "ldc1"; goto ld; @@ -5529,7 +5448,7 @@ macro (ip) return; } - if (mips_opts.isa != 1) + if (mips_opts.isa != ISA_MIPS1) { s = "sdc1"; goto st; @@ -6157,7 +6076,7 @@ macro2 (ip) as_bad (_("opcode not supported on this processor")); return; } - assert (mips_opts.isa == 1); + assert (mips_opts.isa == ISA_MIPS1); /* Even on a big endian machine $fn comes before $fn+1. We have to adjust when storing to memory. */ macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", @@ -6466,7 +6385,7 @@ macro2 (ip) case M_TRUNCWS: case M_TRUNCWD: - assert (mips_opts.isa == 1); + assert (mips_opts.isa == ISA_MIPS1); sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ @@ -7146,8 +7065,9 @@ mips_ip (str, ip) { static char buf[100]; sprintf (buf, - _("opcode not supported on this processor: %s (MIPS%d)"), - mips_cpu_to_str (mips_cpu), mips_opts.isa); + _("opcode not supported on this processor: %s (%s)"), + mips_cpu_to_str (mips_cpu), + mips_isa_to_str (mips_opts.isa)); insn_error = buf; return; @@ -8964,9 +8884,6 @@ struct option md_longopts[] = {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, #define OPTION_MIPS32 (OPTION_MD_BASE + 28) {"mips32", no_argument, NULL, OPTION_MIPS32}, -#define OPTION_NO_MIPS32 (OPTION_MD_BASE + 29) - {"no-mips32", no_argument, NULL, OPTION_NO_MIPS32}, - #ifdef OBJ_ELF #define OPTION_ELF_BASE (OPTION_MD_BASE + 35) #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) @@ -9037,154 +8954,39 @@ md_parse_option (c, arg) break; case OPTION_MIPS1: - mips_opts.isa = 1; + mips_opts.isa = ISA_MIPS1; break; case OPTION_MIPS2: - mips_opts.isa = 2; + mips_opts.isa = ISA_MIPS2; break; case OPTION_MIPS3: - mips_opts.isa = 3; + mips_opts.isa = ISA_MIPS3; break; case OPTION_MIPS4: - mips_opts.isa = 4; + mips_opts.isa = ISA_MIPS4; + break; + + case OPTION_MIPS32: + mips_opts.isa = ISA_MIPS32; break; case OPTION_MCPU: { - char *p; - - /* Identify the processor type */ - p = arg; - if (strcmp (p, "default") == 0 - || strcmp (p, "DEFAULT") == 0) - mips_cpu = -1; + /* Identify the processor type. */ + if (strcasecmp (arg, "default") == 0) + mips_cpu = CPU_UNKNOWN; else { - int sv = 0; - - /* We need to cope with the various "vr" prefixes for the 4300 - processor. */ - if (*p == 'v' || *p == 'V') - { - sv = 1; - p++; - } - - if (*p == 'r' || *p == 'R') - p++; - - mips_cpu = -1; - switch (*p) - { - case '1': - if (strcmp (p, "10000") == 0 - || strcmp (p, "10k") == 0 - || strcmp (p, "10K") == 0) - mips_cpu = CPU_R10000; - break; - - case '2': - if (strcmp (p, "2000") == 0 - || strcmp (p, "2k") == 0 - || strcmp (p, "2K") == 0) - mips_cpu = CPU_R2000; - break; - - case '3': - if (strcmp (p, "3000") == 0 - || strcmp (p, "3k") == 0 - || strcmp (p, "3K") == 0) - mips_cpu = CPU_R3000; - else if (strcmp (p, "3900") == 0) - mips_cpu = CPU_R3900; - break; - - case '4': - if (strcmp (p, "4000") == 0 - || strcmp (p, "4k") == 0 - || strcmp (p, "4K") == 0) - mips_cpu = CPU_R4000; - else if (strcmp (p, "4100") == 0) - mips_cpu = CPU_VR4100; - else if (strcmp (p, "4111") == 0) - mips_cpu = CPU_R4111; - else if (strcmp (p, "4300") == 0) - mips_cpu = CPU_R4300; - else if (strcmp (p, "4400") == 0) - mips_cpu = CPU_R4400; - else if (strcmp (p, "4600") == 0) - mips_cpu = CPU_R4600; - else if (strcmp (p, "4650") == 0) - mips_cpu = CPU_R4650; - else if (strcmp (p, "4010") == 0) - mips_cpu = CPU_R4010; - else if (strcmp (p, "4Kc") == 0 - || strcmp (p, "4Kp") == 0 - || strcmp (p, "4Km") == 0) - mips_cpu = CPU_MIPS32; - break; - - case '5': - if (strcmp (p, "5000") == 0 - || strcmp (p, "5k") == 0 - || strcmp (p, "5K") == 0) - mips_cpu = CPU_R5000; - break; - - case '6': - if (strcmp (p, "6000") == 0 - || strcmp (p, "6k") == 0 - || strcmp (p, "6K") == 0) - mips_cpu = CPU_R6000; - break; - - case '8': - if (strcmp (p, "8000") == 0 - || strcmp (p, "8k") == 0 - || strcmp (p, "8K") == 0) - mips_cpu = CPU_R8000; - break; - - case 'o': - if (strcmp (p, "orion") == 0) - mips_cpu = CPU_R4600; - break; - - case 'm': - case 'M': - switch (atoi (p + 1)) - { - case 5200: - case 5230: - case 5231: - case 5261: - case 5721: - case 7000: - mips_cpu = CPU_R5000; - break; - default: - break; - } - } - - if (sv - && (mips_cpu != CPU_R4300 - && mips_cpu != CPU_VR4100 - && mips_cpu != CPU_R4111 - && mips_cpu != CPU_R5000)) - { - as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg); - return 0; - } + const struct mips_cpu_info *ci; - if (mips_cpu == -1) - { - as_bad (_("invalid architecture -mcpu=%s"), arg); - return 0; - } + ci = mips_cpu_info_from_name (arg); + if (ci == NULL || ci->is_isa) + as_bad (_("invalid architecture -mcpu=%s"), arg); + else + mips_cpu = ci->cpu; } } break; @@ -9210,13 +9012,6 @@ md_parse_option (c, arg) case OPTION_NO_M4100: break; - case OPTION_MIPS32: - mips_cpu = CPU_MIPS32; - break; - - case OPTION_NO_MIPS32: - break; - case OPTION_M3900: mips_cpu = CPU_R3900; break; @@ -9411,6 +9206,7 @@ MIPS options:\n\ -mips2 generate MIPS ISA II instructions\n\ -mips3 generate MIPS ISA III instructions\n\ -mips4 generate MIPS ISA IV instructions\n\ +-mips32 generate MIPS32 ISA instructions\n\ -mcpu=CPU generate code for CPU, where CPU is one of:\n")); first = 1; @@ -9430,9 +9226,7 @@ MIPS options:\n\ show (stream, "6000", &column, &first); show (stream, "8000", &column, &first); show (stream, "10000", &column, &first); - show (stream, "4Kc", &column, &first); - show (stream, "4Kp", &column, &first); - show (stream, "4Km", &column, &first); + show (stream, "mips32-4k", &column, &first); fputc ('\n', stream); fprintf (stream, _("\ @@ -9448,9 +9242,6 @@ MIPS options:\n\ show (stream, "4650", &column, &first); fputc ('\n', stream); - fprintf (stream, _("\ --mips32 generate MIPS32 instructions\n")); - fprintf(stream, _("\ -mips16 generate mips16 instructions\n\ -no-mips16 do not generate mips16 instructions\n")); @@ -10441,12 +10232,18 @@ s_mipsset (x) /* Permit the user to change the ISA on the fly. Needless to say, misuse can cause serious problems. */ isa = atoi (name + 4); - if (isa == 0) - mips_opts.isa = file_mips_isa; - else if (isa < 1 || isa > 4) - as_bad (_("unknown ISA level")); - else - mips_opts.isa = isa; + switch (isa) + { + case 0: mips_opts.isa = file_mips_isa; break; + case 1: mips_opts.isa = ISA_MIPS1; break; + case 2: mips_opts.isa = ISA_MIPS2; break; + case 3: mips_opts.isa = ISA_MIPS3; break; + case 4: mips_opts.isa = ISA_MIPS4; break; + case 32: mips_opts.isa = ISA_MIPS32; break; + default: + as_bad (_("unknown ISA level")); + break; + } } else if (strcmp (name, "autoextend") == 0) mips_opts.noautoextend = 0; @@ -12092,3 +11889,179 @@ s_loc (x) symbolP->sy_segment = now_seg; } #endif + +/* CPU name/ISA/number mapping table. + + Entries are grouped by type. The first matching CPU or ISA entry + gets chosen by CPU or ISA, so it should be the 'canonical' name + for that type. Entries after that within the type are sorted + alphabetically. + + Case is ignored in comparison, so put the canonical entry in the + appropriate case but everything else in lower case to ease eye pain. */ +static const struct mips_cpu_info mips_cpu_info_table[] = +{ + /* MIPS1 ISA */ + { "MIPS1", 1, ISA_MIPS1, CPU_R3000, }, + { "mips", 1, ISA_MIPS1, CPU_R3000, }, + + /* MIPS2 ISA */ + { "MIPS2", 1, ISA_MIPS2, CPU_R6000, }, + + /* MIPS3 ISA */ + { "MIPS3", 1, ISA_MIPS3, CPU_R4000, }, + + /* MIPS4 ISA */ + { "MIPS4", 1, ISA_MIPS4, CPU_R8000, }, + + /* MIPS32 ISA */ + { "MIPS32", 1, ISA_MIPS32, CPU_MIPS32, }, + { "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32, }, + + /* XXX for now, MIPS64 -> MIPS3 because of history */ + { "MIPS64", 1, ISA_MIPS3, CPU_R4000 }, /* XXX! */ + + /* R2000 CPU */ + { "R2000", 0, ISA_MIPS1, CPU_R2000, }, + { "2000", 0, ISA_MIPS1, CPU_R2000, }, + { "2k", 0, ISA_MIPS1, CPU_R2000, }, + { "r2k", 0, ISA_MIPS1, CPU_R2000, }, + + /* R3000 CPU */ + { "R3000", 0, ISA_MIPS1, CPU_R3000, }, + { "3000", 0, ISA_MIPS1, CPU_R3000, }, + { "3k", 0, ISA_MIPS1, CPU_R3000, }, + { "r3k", 0, ISA_MIPS1, CPU_R3000, }, + + /* TX3900 CPU */ + { "R3900", 0, ISA_MIPS1, CPU_R3900, }, + { "3900", 0, ISA_MIPS1, CPU_R3900, }, + { "mipstx39", 0, ISA_MIPS1, CPU_R3900, }, + + /* R4000 CPU */ + { "R4000", 0, ISA_MIPS3, CPU_R4000, }, + { "4000", 0, ISA_MIPS3, CPU_R4000, }, + { "4k", 0, ISA_MIPS3, CPU_R4000, }, /* beware */ + { "r4k", 0, ISA_MIPS3, CPU_R4000, }, + + /* R4010 CPU */ + { "R4010", 0, ISA_MIPS2, CPU_R4010, }, + { "4010", 0, ISA_MIPS2, CPU_R4010, }, + + /* R4400 CPU */ + { "R4400", 0, ISA_MIPS3, CPU_R4400, }, + { "4400", 0, ISA_MIPS3, CPU_R4400, }, + + /* R4600 CPU */ + { "R4600", 0, ISA_MIPS3, CPU_R4600, }, + { "4600", 0, ISA_MIPS3, CPU_R4600, }, + { "mips64orion", 0, ISA_MIPS3, CPU_R4600, }, + { "orion", 0, ISA_MIPS3, CPU_R4600, }, + + /* R4650 CPU */ + { "R4650", 0, ISA_MIPS3, CPU_R4650, }, + { "4650", 0, ISA_MIPS3, CPU_R4650, }, + + /* R6000 CPU */ + { "R6000", 0, ISA_MIPS2, CPU_R6000, }, + { "6000", 0, ISA_MIPS2, CPU_R6000, }, + { "6k", 0, ISA_MIPS2, CPU_R6000, }, + { "r6k", 0, ISA_MIPS2, CPU_R6000, }, + + /* R8000 CPU */ + { "R8000", 0, ISA_MIPS4, CPU_R8000, }, + { "8000", 0, ISA_MIPS4, CPU_R8000, }, + { "8k", 0, ISA_MIPS4, CPU_R8000, }, + { "r8k", 0, ISA_MIPS4, CPU_R8000, }, + + /* R10000 CPU */ + { "R10000", 0, ISA_MIPS4, CPU_R10000, }, + { "10000", 0, ISA_MIPS4, CPU_R10000, }, + { "10k", 0, ISA_MIPS4, CPU_R10000, }, + { "r10k", 0, ISA_MIPS4, CPU_R10000, }, + + /* VR4100 CPU */ + { "VR4100", 0, ISA_MIPS3, CPU_VR4100, }, + { "4100", 0, ISA_MIPS3, CPU_VR4100, }, + { "mips64vr4100", 0, ISA_MIPS3, CPU_VR4100, }, + { "r4100", 0, ISA_MIPS3, CPU_VR4100, }, + + /* VR4111 CPU */ + { "VR4111", 0, ISA_MIPS3, CPU_R4111, }, + { "4111", 0, ISA_MIPS3, CPU_R4111, }, + { "mips64vr4111", 0, ISA_MIPS3, CPU_R4111, }, + { "r4111", 0, ISA_MIPS3, CPU_R4111, }, + + /* VR4300 CPU */ + { "VR4300", 0, ISA_MIPS3, CPU_R4300, }, + { "4300", 0, ISA_MIPS3, CPU_R4300, }, + { "mips64vr4300", 0, ISA_MIPS3, CPU_R4300, }, + { "r4300", 0, ISA_MIPS3, CPU_R4300, }, + + /* VR5000 CPU */ + { "VR5000", 0, ISA_MIPS4, CPU_R5000, }, + { "5000", 0, ISA_MIPS4, CPU_R5000, }, + { "5k", 0, ISA_MIPS4, CPU_R5000, }, + { "mips64vr5000", 0, ISA_MIPS4, CPU_R5000, }, + { "r5000", 0, ISA_MIPS4, CPU_R5000, }, + { "r5200", 0, ISA_MIPS4, CPU_R5000, }, + { "r5230", 0, ISA_MIPS4, CPU_R5000, }, + { "r5231", 0, ISA_MIPS4, CPU_R5000, }, + { "r5261", 0, ISA_MIPS4, CPU_R5000, }, + { "r5721", 0, ISA_MIPS4, CPU_R5000, }, + { "r5k", 0, ISA_MIPS4, CPU_R5000, }, + { "r7000", 0, ISA_MIPS4, CPU_R5000, }, + + /* MIPS32 4K CPU */ + { "MIPS32-4K", 0, ISA_MIPS32, CPU_MIPS32_4K, }, + { "4kc", 0, ISA_MIPS32, CPU_MIPS32_4K, }, + { "4km", 0, ISA_MIPS32, CPU_MIPS32_4K, }, + { "4kp", 0, ISA_MIPS32, CPU_MIPS32_4K, }, + { "mips32-4kc", 0, ISA_MIPS32, CPU_MIPS32_4K, }, + { "mips32-4km", 0, ISA_MIPS32, CPU_MIPS32_4K, }, + { "mips32-4kp", 0, ISA_MIPS32, CPU_MIPS32_4K, }, + + /* End marker. */ + { NULL, 0, 0, 0, }, +}; + +static const struct mips_cpu_info * +mips_cpu_info_from_name (name) + const char *name; +{ + int i; + + for (i = 0; mips_cpu_info_table[i].name != NULL; i++) + if (strcasecmp(name, mips_cpu_info_table[i].name) == 0) + return (&mips_cpu_info_table[i]); + + return (NULL); +} + +static const struct mips_cpu_info * +mips_cpu_info_from_isa (isa) + int isa; +{ + int i; + + for (i = 0; mips_cpu_info_table[i].name != NULL; i++) + if (mips_cpu_info_table[i].is_isa + && isa == mips_cpu_info_table[i].isa) + return (&mips_cpu_info_table[i]); + + return (NULL); +} + +static const struct mips_cpu_info * +mips_cpu_info_from_cpu (cpu) + int cpu; +{ + int i; + + for (i = 0; mips_cpu_info_table[i].name != NULL; i++) + if (!mips_cpu_info_table[i].is_isa + && cpu == mips_cpu_info_table[i].cpu) + return (&mips_cpu_info_table[i]); + + return (NULL); +} diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo index a45a561..a59ae1d 100644 --- a/gas/doc/as.texinfo +++ b/gas/doc/as.texinfo @@ -276,7 +276,8 @@ Here is a brief summary of how to invoke @code{@value{AS}}. For details, @end ifset @ifset MIPS [ -nocpp ] [ -EL ] [ -EB ] [ -G @var{num} ] [ -mcpu=@var{CPU} ] - [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -m4650 ] [ -no-m4650 ] [ -mips32 ] [ -no-mips32 ] + [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -mips4 ] [ -mips32 ] + [ -m4650 ] [ -no-m4650 ] [ --trap ] [ --break ] [ --emulation=@var{name} ] @end ifset @@ -669,10 +670,12 @@ Generate ``little endian'' format output. @item -mips1 @itemx -mips2 @itemx -mips3 +@itemx -mips4 +@itemx -mips32 Generate code for a particular MIPS Instruction Set Architecture level. @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors, -@samp{-mips2} to the @sc{r6000} processor, and @samp{-mips3} to the @sc{r4000} -processor. +@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the @sc{r4000} +processor, @samp{-mips32} to a generic @sc{MIPS32} processor. @item -m4650 @itemx -no-m4650 @@ -681,12 +684,6 @@ the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} instructions around accesses to the @samp{HI} and @samp{LO} registers. @samp{-no-m4650} turns off this option. -@item -mips32 -@itemx -no-mips32 -Generate code for the @sc{MIPS32} architecture. This tells the assembler to -accept ISA level 2 instructions and MIPS32 extensions including some @sc{r4000} -instructions. - @item -mcpu=@var{CPU} Generate code for a particular MIPS cpu. This has little effect on the assembler, but it is passed by @code{@value{GCC}}. diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi index 137dfe9..e56156e 100644 --- a/gas/doc/c-mips.texi +++ b/gas/doc/c-mips.texi @@ -60,12 +60,14 @@ to select big-endian output, and @samp{-EL} for little-endian. @itemx -mips2 @itemx -mips3 @itemx -mips4 +@itemx -mips32 Generate code for a particular MIPS Instruction Set Architecture level. @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors, @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the -@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and -@sc{r10000} processors. You can also switch instruction sets during the -assembly; see @ref{MIPS ISA,, Directives to override the ISA level}. +@sc{r4000} processor, @samp{-mips4} to the @sc{r8000} and +@sc{r10000} processors, and @samp{-mips32} to a generic @sc(MIPS32) +processor. You can also switch instruction sets during the +assembly; see @ref{MIPS ISA, Directives to override the ISA level}. @item -mgp32 Assume that 32-bit general purpose registers are available. This @@ -140,10 +142,8 @@ rm5721, 6000, rm7000, 8000, -10000 -4Kc -4Km -4Kp +10000, +mips32-4k @end quotation @@ -239,8 +239,8 @@ assembly language programmers! @kindex @code{.set mips@var{n}} @sc{gnu} @code{@value{AS}} supports an additional directive to change the @sc{mips} Instruction Set Architecture level on the fly: @code{.set -mips@var{n}}. @var{n} should be a number from 0 to 4. A value from 1 -to 4 makes the assembler accept instructions for the corresponding +mips@var{n}}. @var{n} should be a number from 0 to 4, or 32. The values 1 +to 4 and 32 make the assembler accept instructions for the corresponding @sc{isa} level, from that point on in the assembly. @code{.set mips@var{n}} affects not only which instructions are permitted, but also how certain macros are expanded. @code{.set mips0} restores the diff --git a/gas/po/gas.pot b/gas/po/gas.pot index 24f3cc4..a7f0c5a 100644 --- a/gas/po/gas.pot +++ b/gas/po/gas.pot @@ -6,7 +6,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" -"POT-Creation-Date: 2000-12-01 10:13-0800\n" +"POT-Creation-Date: 2000-12-01 13:21-0800\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n" "Language-Team: LANGUAGE <LL@li.org>\n" @@ -979,8 +979,8 @@ msgid "Unknown segment type" msgstr "" #. Probably a memory allocation problem? Give up now. -#: config/tc-a29k.c:330 config/tc-hppa.c:1412 config/tc-mips.c:1107 -#: config/tc-mips.c:1149 config/tc-sparc.c:846 +#: config/tc-a29k.c:330 config/tc-hppa.c:1412 config/tc-mips.c:1026 +#: config/tc-mips.c:1068 config/tc-sparc.c:846 msgid "Broken assembler. No assembly attempted." msgstr "" @@ -1104,7 +1104,7 @@ msgstr "" msgid "type %d reloc done?\n" msgstr "" -#: config/tc-alpha.c:1379 config/tc-alpha.c:1386 config/tc-mips.c:7422 +#: config/tc-alpha.c:1379 config/tc-alpha.c:1386 config/tc-mips.c:7351 msgid "Used $at without \".set noat\"" msgstr "" @@ -1460,7 +1460,7 @@ msgid "invalid symbol to rename to" msgstr "" #: config/tc-arc.c:1009 config/tc-avr.c:372 config/tc-d10v.c:291 -#: config/tc-d30v.c:366 config/tc-mips.c:8850 config/tc-mn10200.c:375 +#: config/tc-d30v.c:366 config/tc-mips.c:8783 config/tc-mn10200.c:375 #: config/tc-pj.c:356 config/tc-ppc.c:4511 config/tc-sh.c:2058 #: config/tc-v850.c:1291 msgid "bad call to md_atof" @@ -1477,8 +1477,8 @@ msgstr "" #: config/tc-arc.c:1325 config/tc-arm.c:4570 config/tc-avr.c:852 #: config/tc-cris.c:2733 config/tc-d10v.c:1538 config/tc-d30v.c:1865 -#: config/tc-mips.c:3293 config/tc-mips.c:4225 config/tc-mips.c:5010 -#: config/tc-mips.c:5556 config/tc-ppc.c:4847 config/tc-v850.c:2385 +#: config/tc-mips.c:3225 config/tc-mips.c:4157 config/tc-mips.c:4942 +#: config/tc-mips.c:5488 config/tc-ppc.c:4847 config/tc-v850.c:2385 msgid "expression too complex" msgstr "" @@ -1519,7 +1519,7 @@ msgstr "" msgid "Invalid syntax for .req directive." msgstr "" -#: config/tc-arm.c:1506 config/tc-mips.c:10088 read.c:2047 +#: config/tc-arm.c:1506 config/tc-mips.c:9892 read.c:2047 #, c-format msgid "Alignment too large: %d. assumed." msgstr "" @@ -1978,7 +1978,7 @@ msgstr "" msgid "out of range branch" msgstr "" -#: config/tc-arm.c:7096 config/tc-arm.c:7112 config/tc-mips.c:9915 +#: config/tc-arm.c:7096 config/tc-arm.c:7112 config/tc-mips.c:9719 msgid "Branch out of range" msgstr "" @@ -2061,7 +2061,7 @@ msgstr "" msgid "Cannot represent %s relocation in this object file format" msgstr "" -#: config/tc-arm.c:7515 config/tc-mips.c:11428 config/tc-sh.c:3177 +#: config/tc-arm.c:7515 config/tc-mips.c:11238 config/tc-sh.c:3177 #, c-format msgid "Can not represent %s relocation in this object file format" msgstr "" @@ -2830,7 +2830,7 @@ msgstr "" msgid "invalid operands" msgstr "" -#: config/tc-h8300.c:1250 config/tc-h8500.c:1104 config/tc-mips.c:8046 +#: config/tc-h8300.c:1250 config/tc-h8500.c:1104 config/tc-mips.c:7979 #: config/tc-sh.c:1877 config/tc-w65.c:740 config/tc-z8k.c:1205 msgid "unknown opcode" msgstr "" @@ -3694,7 +3694,7 @@ msgstr "" msgid "Unknown temporary pseudo register" msgstr "" -#: config/tc-i860.c:181 config/tc-mips.c:1104 +#: config/tc-i860.c:181 config/tc-mips.c:1023 #, c-format msgid "internal error: can't hash `%s': %s\n" msgstr "" @@ -4051,7 +4051,7 @@ msgid "" " -xdebug\t\t debug dependency violation checker\n" msgstr "" -#: config/tc-ia64.c:6147 config/tc-mips.c:1091 +#: config/tc-ia64.c:6147 config/tc-mips.c:1010 msgid "Could not set architecture and machine" msgstr "" @@ -4578,7 +4578,7 @@ msgstr "" msgid "Can not do %d byte pic relocation" msgstr "" -#: config/tc-m68k.c:919 config/tc-mips.c:11409 +#: config/tc-m68k.c:919 config/tc-mips.c:11219 #, c-format msgid "Cannot make %s relocation PC relative" msgstr "" @@ -5221,327 +5221,327 @@ msgstr "" msgid "Cannot represent relocation type %s" msgstr "" -#: config/tc-mips.c:636 +#: config/tc-mips.c:639 #, c-format msgid "internal Error, line %d, %s" msgstr "" -#: config/tc-mips.c:638 +#: config/tc-mips.c:641 msgid "MIPS internal Error" msgstr "" -#: config/tc-mips.c:903 +#: config/tc-mips.c:923 msgid "-G not supported in this configuration." msgstr "" -#: config/tc-mips.c:1050 +#: config/tc-mips.c:992 msgid "trap exception not supported at ISA 1" msgstr "" -#: config/tc-mips.c:1130 +#: config/tc-mips.c:1049 #, c-format msgid "internal: can't hash `%s': %s" msgstr "" -#: config/tc-mips.c:1138 +#: config/tc-mips.c:1057 #, c-format msgid "internal error: bad mips16 opcode: %s %s\n" msgstr "" -#: config/tc-mips.c:1306 +#: config/tc-mips.c:1225 #, c-format msgid "returned from mips_ip(%s) insn_opcode = 0x%x\n" msgstr "" -#: config/tc-mips.c:1860 config/tc-mips.c:11541 +#: config/tc-mips.c:1779 config/tc-mips.c:11351 msgid "extended instruction in delay slot" msgstr "" -#: config/tc-mips.c:1882 config/tc-mips.c:1889 +#: config/tc-mips.c:1801 config/tc-mips.c:1808 #, c-format msgid "jump to misaligned address (0x%lx)" msgstr "" -#: config/tc-mips.c:2538 config/tc-mips.c:2879 +#: config/tc-mips.c:2457 config/tc-mips.c:2811 msgid "Macro instruction expanded into multiple instructions" msgstr "" -#: config/tc-mips.c:2932 +#: config/tc-mips.c:2864 msgid "unsupported large constant" msgstr "" -#: config/tc-mips.c:2934 +#: config/tc-mips.c:2866 #, c-format msgid "Instruction %s requires absolute expression" msgstr "" -#: config/tc-mips.c:3080 +#: config/tc-mips.c:3012 msgid "Number larger than 32 bits" msgstr "" -#: config/tc-mips.c:3101 +#: config/tc-mips.c:3033 msgid "Number larger than 64 bits" msgstr "" -#: config/tc-mips.c:3367 config/tc-mips.c:3439 config/tc-mips.c:5118 -#: config/tc-mips.c:5169 config/tc-mips.c:5705 config/tc-mips.c:5768 +#: config/tc-mips.c:3299 config/tc-mips.c:3371 config/tc-mips.c:5050 +#: config/tc-mips.c:5101 config/tc-mips.c:5637 config/tc-mips.c:5700 msgid "PIC code offset overflow (max 16 signed bits)" msgstr "" -#: config/tc-mips.c:3678 +#: config/tc-mips.c:3610 #, c-format msgid "Branch %s is always false (nop)" msgstr "" -#: config/tc-mips.c:3683 +#: config/tc-mips.c:3615 #, c-format msgid "Branch likely %s is always false" msgstr "" -#: config/tc-mips.c:3690 config/tc-mips.c:3764 config/tc-mips.c:3867 -#: config/tc-mips.c:3922 config/tc-mips.c:6805 config/tc-mips.c:6814 -#: config/tc-mips.c:6822 config/tc-mips.c:6931 +#: config/tc-mips.c:3622 config/tc-mips.c:3696 config/tc-mips.c:3799 +#: config/tc-mips.c:3854 config/tc-mips.c:6737 config/tc-mips.c:6746 +#: config/tc-mips.c:6754 config/tc-mips.c:6863 msgid "Unsupported large constant" msgstr "" #. result is always true -#: config/tc-mips.c:3726 +#: config/tc-mips.c:3658 #, c-format msgid "Branch %s is always true" msgstr "" -#: config/tc-mips.c:3998 config/tc-mips.c:4105 +#: config/tc-mips.c:3930 config/tc-mips.c:4037 msgid "Divide by zero." msgstr "" -#: config/tc-mips.c:4689 +#: config/tc-mips.c:4621 msgid "MIPS PIC call to register other than $25" msgstr "" -#: config/tc-mips.c:4694 config/tc-mips.c:4806 +#: config/tc-mips.c:4626 config/tc-mips.c:4738 msgid "No .cprestore pseudo-op used in PIC code" msgstr "" -#: config/tc-mips.c:4879 config/tc-mips.c:4968 config/tc-mips.c:5456 -#: config/tc-mips.c:5497 config/tc-mips.c:5515 config/tc-mips.c:6144 +#: config/tc-mips.c:4811 config/tc-mips.c:4900 config/tc-mips.c:5388 +#: config/tc-mips.c:5429 config/tc-mips.c:5447 config/tc-mips.c:6076 msgid "opcode not supported on this processor" msgstr "" -#: config/tc-mips.c:5975 config/tc-mips.c:6699 +#: config/tc-mips.c:5907 config/tc-mips.c:6631 msgid "Macro used $at after \".set noat\"" msgstr "" -#: config/tc-mips.c:6115 config/tc-mips.c:6133 +#: config/tc-mips.c:6047 config/tc-mips.c:6065 msgid "rotate count too large" msgstr "" -#: config/tc-mips.c:6184 +#: config/tc-mips.c:6116 #, c-format msgid "Instruction %s: result is always false" msgstr "" -#: config/tc-mips.c:6353 +#: config/tc-mips.c:6285 #, c-format msgid "Instruction %s: result is always true" msgstr "" -#: config/tc-mips.c:6492 config/tc-mips.c:6519 config/tc-mips.c:6591 -#: config/tc-mips.c:6616 +#: config/tc-mips.c:6424 config/tc-mips.c:6451 config/tc-mips.c:6523 +#: config/tc-mips.c:6548 msgid "operand overflow" msgstr "" #. FIXME: Check if this is one of the itbl macros, since they #. are added dynamically. -#: config/tc-mips.c:6695 +#: config/tc-mips.c:6627 #, c-format msgid "Macro %s not implemented yet" msgstr "" -#: config/tc-mips.c:6965 +#: config/tc-mips.c:6897 #, c-format msgid "internal: bad mips opcode (mask error): %s %s" msgstr "" -#: config/tc-mips.c:7019 +#: config/tc-mips.c:6953 #, c-format msgid "internal: bad mips opcode (unknown operand type `%c'): %s %s" msgstr "" -#: config/tc-mips.c:7026 +#: config/tc-mips.c:6960 #, c-format msgid "internal: bad mips opcode (bits 0x%lx undefined): %s %s" msgstr "" -#: config/tc-mips.c:7134 +#: config/tc-mips.c:7068 #, c-format -msgid "opcode not supported on this processor: %s (MIPS%d)" +msgid "opcode not supported on this processor: %s (%s)" msgstr "" -#: config/tc-mips.c:7204 +#: config/tc-mips.c:7139 #, c-format msgid "Improper shift amount (%ld)" msgstr "" -#: config/tc-mips.c:7230 config/tc-mips.c:8386 config/tc-mips.c:8501 +#: config/tc-mips.c:7165 config/tc-mips.c:8319 config/tc-mips.c:8434 #, c-format msgid "Invalid value for `%s' (%lu)" msgstr "" -#: config/tc-mips.c:7248 config/tc-mips.c:7278 +#: config/tc-mips.c:7183 #, c-format msgid "Illegal break code (%ld)" msgstr "" -#: config/tc-mips.c:7262 +#: config/tc-mips.c:7197 #, c-format msgid "Illegal lower break code (%ld)" msgstr "" -#: config/tc-mips.c:7293 +#: config/tc-mips.c:7210 #, c-format -msgid "Illegal syscall code (%ld)" +msgid "Illegal 20-bit code (%ld)" msgstr "" -#: config/tc-mips.c:7305 +#: config/tc-mips.c:7222 #, c-format msgid "Coproccesor code > 25 bits (%ld)" msgstr "" -#: config/tc-mips.c:7319 +#: config/tc-mips.c:7235 +#, c-format +msgid "Illegal 19-bit code (%ld)" +msgstr "" + +#: config/tc-mips.c:7247 #, c-format msgid "Invalidate performance regster (%ld)" msgstr "" -#: config/tc-mips.c:7355 +#: config/tc-mips.c:7284 #, c-format msgid "Invalid register number (%d)" msgstr "" -#: config/tc-mips.c:7515 +#: config/tc-mips.c:7448 #, c-format msgid "Invalid float register number (%d)" msgstr "" -#: config/tc-mips.c:7525 +#: config/tc-mips.c:7458 #, c-format msgid "Float register should be even, was %d" msgstr "" -#: config/tc-mips.c:7576 +#: config/tc-mips.c:7509 msgid "absolute expression required" msgstr "" -#: config/tc-mips.c:7637 +#: config/tc-mips.c:7570 #, c-format msgid "Bad floating point constant: %s" msgstr "" -#: config/tc-mips.c:7759 +#: config/tc-mips.c:7692 msgid "Can't use floating point insn in this section" msgstr "" -#: config/tc-mips.c:7813 +#: config/tc-mips.c:7746 msgid "16 bit expression not in range 0..65535" msgstr "" -#: config/tc-mips.c:7850 +#: config/tc-mips.c:7783 msgid "16 bit expression not in range -32768..32767" msgstr "" -#: config/tc-mips.c:7921 +#: config/tc-mips.c:7854 msgid "lui expression not in range 0..65535" msgstr "" -#: config/tc-mips.c:7945 +#: config/tc-mips.c:7878 #, c-format msgid "invalid condition code register $fcc%d" msgstr "" -#: config/tc-mips.c:7970 +#: config/tc-mips.c:7903 msgid "invalid coprocessor sub-selection value (0-7)" msgstr "" -#: config/tc-mips.c:7975 +#: config/tc-mips.c:7908 #, c-format msgid "bad char = '%c'\n" msgstr "" -#: config/tc-mips.c:7988 config/tc-mips.c:8526 +#: config/tc-mips.c:7921 config/tc-mips.c:8459 msgid "illegal operands" msgstr "" -#: config/tc-mips.c:8055 +#: config/tc-mips.c:7988 msgid "unrecognized opcode" msgstr "" -#: config/tc-mips.c:8164 +#: config/tc-mips.c:8097 #, c-format msgid "invalid register number (%d)" msgstr "" -#: config/tc-mips.c:8245 +#: config/tc-mips.c:8178 msgid "used $at without \".set noat\"" msgstr "" -#: config/tc-mips.c:8420 +#: config/tc-mips.c:8353 msgid "can't parse register list" msgstr "" -#: config/tc-mips.c:8454 config/tc-mips.c:8484 +#: config/tc-mips.c:8387 config/tc-mips.c:8417 msgid "invalid register list" msgstr "" -#: config/tc-mips.c:8651 +#: config/tc-mips.c:8584 msgid "extended operand requested but not required" msgstr "" -#: config/tc-mips.c:8653 +#: config/tc-mips.c:8586 msgid "invalid unextended operand value" msgstr "" -#: config/tc-mips.c:8681 +#: config/tc-mips.c:8614 msgid "operand value out of range for instruction" msgstr "" -#: config/tc-mips.c:9166 -#, c-format -msgid "ignoring invalid leading 'v' in -mcpu=%s switch" -msgstr "" - -#: config/tc-mips.c:9172 +#: config/tc-mips.c:8987 #, c-format msgid "invalid architecture -mcpu=%s" msgstr "" -#: config/tc-mips.c:9228 +#: config/tc-mips.c:9036 msgid "-G may not be used with embedded PIC code" msgstr "" -#: config/tc-mips.c:9240 +#: config/tc-mips.c:9048 msgid "-call_shared is supported only for ELF format" msgstr "" -#: config/tc-mips.c:9246 config/tc-mips.c:10330 config/tc-mips.c:10498 +#: config/tc-mips.c:9054 config/tc-mips.c:10134 config/tc-mips.c:10308 msgid "-G may not be used with SVR4 PIC code" msgstr "" -#: config/tc-mips.c:9255 +#: config/tc-mips.c:9063 msgid "-non_shared is supported only for ELF format" msgstr "" -#: config/tc-mips.c:9271 +#: config/tc-mips.c:9079 msgid "-G is not supported for this configuration" msgstr "" -#: config/tc-mips.c:9276 +#: config/tc-mips.c:9084 msgid "-G may not be used with SVR4 or embedded PIC code" msgstr "" -#: config/tc-mips.c:9300 +#: config/tc-mips.c:9108 msgid "No compiled in support for 64 bit object file format" msgstr "" -#: config/tc-mips.c:9388 +#: config/tc-mips.c:9196 msgid "" "MIPS options:\n" "-membedded-pic\t\tgenerate embedded position independent code\n" @@ -5552,33 +5552,30 @@ msgid "" "\t\t\timplicitly with the gp register [default 8]\n" msgstr "" -#: config/tc-mips.c:9396 +#: config/tc-mips.c:9204 msgid "" "-mips1\t\t\tgenerate MIPS ISA I instructions\n" "-mips2\t\t\tgenerate MIPS ISA II instructions\n" "-mips3\t\t\tgenerate MIPS ISA III instructions\n" "-mips4\t\t\tgenerate MIPS ISA IV instructions\n" +"-mips32 generate MIPS32 ISA instructions\n" "-mcpu=CPU\t\tgenerate code for CPU, where CPU is one of:\n" msgstr "" -#: config/tc-mips.c:9425 +#: config/tc-mips.c:9232 msgid "" "-mCPU\t\t\tequivalent to -mcpu=CPU.\n" "-no-mCPU\t\tdon't generate code specific to CPU.\n" "\t\t\tFor -mCPU and -no-mCPU, CPU must be one of:\n" msgstr "" -#: config/tc-mips.c:9438 -msgid "-mips32 generate MIPS32 instructions\n" -msgstr "" - -#: config/tc-mips.c:9441 +#: config/tc-mips.c:9245 msgid "" "-mips16\t\t\tgenerate mips16 instructions\n" "-no-mips16\t\tdo not generate mips16 instructions\n" msgstr "" -#: config/tc-mips.c:9444 +#: config/tc-mips.c:9248 msgid "" "-O0\t\t\tremove unneeded NOPs, do not swap branches\n" "-O\t\t\tremove unneeded NOPs and swap branches\n" @@ -5587,7 +5584,7 @@ msgid "" "--break, --no-trap\tbreak exception on div by 0 and mult overflow\n" msgstr "" -#: config/tc-mips.c:9451 +#: config/tc-mips.c:9255 msgid "" "-KPIC, -call_shared\tgenerate SVR4 position independent code\n" "-non_shared\t\tdo not generate position independent code\n" @@ -5596,170 +5593,170 @@ msgid "" "-64\t\t\tcreate 64 bit object file\n" msgstr "" -#: config/tc-mips.c:9508 +#: config/tc-mips.c:9312 #, c-format msgid "Unsupported reloc size %d" msgstr "" -#: config/tc-mips.c:9611 +#: config/tc-mips.c:9415 msgid "Unmatched %%hi reloc" msgstr "" -#: config/tc-mips.c:9735 +#: config/tc-mips.c:9539 msgid "Invalid PC relative reloc" msgstr "" -#: config/tc-mips.c:9845 config/tc-sparc.c:3101 config/tc-sparc.c:3108 +#: config/tc-mips.c:9649 config/tc-sparc.c:3101 config/tc-sparc.c:3108 #: config/tc-sparc.c:3115 config/tc-sparc.c:3122 config/tc-sparc.c:3129 #: config/tc-sparc.c:3138 config/tc-sparc.c:3149 config/tc-sparc.c:3175 #: config/tc-sparc.c:3203 write.c:984 write.c:1048 msgid "relocation overflow" msgstr "" -#: config/tc-mips.c:9861 +#: config/tc-mips.c:9665 #, c-format msgid "Branch to odd address (%lx)" msgstr "" -#: config/tc-mips.c:10025 +#: config/tc-mips.c:9829 #, c-format msgid "%08lx UNDEFINED\n" msgstr "" -#: config/tc-mips.c:10091 +#: config/tc-mips.c:9895 msgid "Alignment negative: 0 assumed." msgstr "" -#: config/tc-mips.c:10179 +#: config/tc-mips.c:9983 msgid "No read only data section in this object file format" msgstr "" -#: config/tc-mips.c:10202 +#: config/tc-mips.c:10006 msgid "Global pointers not supported; recompile -G 0" msgstr "" -#: config/tc-mips.c:10288 +#: config/tc-mips.c:10092 #, c-format msgid "%s: no such section" msgstr "" -#: config/tc-mips.c:10325 +#: config/tc-mips.c:10129 #, c-format msgid ".option pic%d not supported" msgstr "" -#: config/tc-mips.c:10336 +#: config/tc-mips.c:10140 #, c-format msgid "Unrecognized option \"%s\"" msgstr "" -#: config/tc-mips.c:10399 +#: config/tc-mips.c:10203 msgid "`noreorder' must be set before `nomacro'" msgstr "" -#: config/tc-mips.c:10434 +#: config/tc-mips.c:10244 msgid "unknown ISA level" msgstr "" -#: config/tc-mips.c:10457 +#: config/tc-mips.c:10267 msgid ".set pop with no .set push" msgstr "" -#: config/tc-mips.c:10481 +#: config/tc-mips.c:10291 #, c-format msgid "Tried to set unrecognized symbol: %s\n" msgstr "" -#: config/tc-mips.c:10531 +#: config/tc-mips.c:10341 msgid ".cpload not in noreorder section" msgstr "" -#: config/tc-mips.c:10613 +#: config/tc-mips.c:10423 msgid "Unsupported use of .gpword" msgstr "" -#: config/tc-mips.c:10750 +#: config/tc-mips.c:10560 msgid "expected `$'" msgstr "" -#: config/tc-mips.c:10758 +#: config/tc-mips.c:10568 msgid "Bad register number" msgstr "" -#: config/tc-mips.c:10774 +#: config/tc-mips.c:10584 msgid "Unrecognized register name" msgstr "" -#: config/tc-mips.c:10973 +#: config/tc-mips.c:10783 msgid "unsupported PC relative reference to different section" msgstr "" -#: config/tc-mips.c:11082 +#: config/tc-mips.c:10892 msgid "unsupported relocation" msgstr "" -#: config/tc-mips.c:11187 +#: config/tc-mips.c:10997 msgid "AT used after \".set noat\" or macro used after \".set nomacro\"" msgstr "" -#: config/tc-mips.c:11250 +#: config/tc-mips.c:11060 msgid "Double check fx_r_type in tc-mips.c:tc_gen_reloc" msgstr "" -#: config/tc-mips.c:11762 +#: config/tc-mips.c:11572 msgid "missing `.end' at end of assembly" msgstr "" -#: config/tc-mips.c:11777 +#: config/tc-mips.c:11587 msgid "Expected simple number." msgstr "" -#: config/tc-mips.c:11803 +#: config/tc-mips.c:11613 #, c-format msgid " *input_line_pointer == '%c' 0x%02x\n" msgstr "" -#: config/tc-mips.c:11805 +#: config/tc-mips.c:11615 msgid "Invalid number" msgstr "" -#: config/tc-mips.c:11859 +#: config/tc-mips.c:11669 msgid ".end not in text section" msgstr "" -#: config/tc-mips.c:11863 +#: config/tc-mips.c:11673 msgid ".end directive without a preceding .ent directive." msgstr "" -#: config/tc-mips.c:11872 +#: config/tc-mips.c:11682 msgid ".end symbol does not match .ent symbol." msgstr "" -#: config/tc-mips.c:11875 +#: config/tc-mips.c:11685 msgid ".end directive missing or unknown symbol" msgstr "" -#: config/tc-mips.c:11950 +#: config/tc-mips.c:11760 msgid ".ent or .aent not in text section." msgstr "" -#: config/tc-mips.c:11953 +#: config/tc-mips.c:11763 msgid "missing `.end'" msgstr "" -#: config/tc-mips.c:11986 ecoff.c:3205 +#: config/tc-mips.c:11796 ecoff.c:3205 msgid ".frame outside of .ent" msgstr "" -#: config/tc-mips.c:11997 ecoff.c:3216 +#: config/tc-mips.c:11807 ecoff.c:3216 msgid "Bad .frame directive" msgstr "" -#: config/tc-mips.c:12027 +#: config/tc-mips.c:11837 msgid ".mask/.fmask outside of .ent" msgstr "" -#: config/tc-mips.c:12034 +#: config/tc-mips.c:11844 msgid "Bad .mask/.fmask directive" msgstr "" diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index 363c8f5..a7deff8 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -88,6 +88,7 @@ if [istarget mips*-*-*] then { run_dump_test "mips4100" run_dump_test "lineno" run_dump_test "sync" + run_dump_test "mips32" # Make sure that -mcpu=FOO and -mFOO are equivalent. Assemble a file # containing 4650-specific instructions with -m4650 and -mcpu=4650, diff --git a/gas/testsuite/gas/mips/mips32.d b/gas/testsuite/gas/mips/mips32.d new file mode 100644 index 0000000..5573e9d --- /dev/null +++ b/gas/testsuite/gas/mips/mips32.d @@ -0,0 +1,49 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS MIPS32 instructions +#as: -mips32 + +# Check MIPS32 instruction assembly + +.*: +file format elf.*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 70410821 clo \$at,\$v0 +0+0004 <[^>]*> 70831820 clz \$v1,\$a0 +0+0008 <[^>]*> 70a60000 mad \$a1,\$a2 +0+000c <[^>]*> 70e80001 madu \$a3,\$t0 +0+0010 <[^>]*> 712a0004 msub \$t1,\$t2 +0+0014 <[^>]*> 716c0005 msubu \$t3,\$t4 +0+0018 <[^>]*> 71cf6802 mul \$t5,\$t6,\$t7 +0+001c <[^>]*> ce040000 pref 0x4,0\(\$s0\) +0+0020 <[^>]*> ce247fff pref 0x4,32767\(\$s1\) +0+0024 <[^>]*> ce448000 pref 0x4,-32768\(\$s2\) +0+0028 <[^>]*> 00000040 ssnop +0+002c <[^>]*> 4900fff4 bc2f 0+0000 <text_label> +0+0030 <[^>]*> 00000000 nop +0+0034 <[^>]*> 4902fff2 bc2fl 0+0000 <text_label> +0+0038 <[^>]*> 00000000 nop +0+003c <[^>]*> 4901fff0 bc2t 0+0000 <text_label> +0+0040 <[^>]*> 00000000 nop +0+0044 <[^>]*> 4903ffee bc2tl 0+0000 <text_label> +0+0048 <[^>]*> 00000000 nop +0+004c <[^>]*> 48411000 cfc2 \$at,\$2 +0+0050 <[^>]*> 4b234567 c2 0x1234567 +0+0054 <[^>]*> 48c21800 ctc2 \$v0,\$3 +0+0058 <[^>]*> 48032000 mfc2 \$v1,\$4 +0+005c <[^>]*> 48042800 mfc2 \$a0,\$5 +0+0060 <[^>]*> 48053007 mfc2 \$a1,\$6,7 +0+0064 <[^>]*> 48863800 mtc2 \$a2,\$7 +0+0068 <[^>]*> 48874000 mtc2 \$a3,\$8 +0+006c <[^>]*> 48884807 mtc2 \$t0,\$9,7 +0+0070 <[^>]*> bc250000 cache 0x5,0\(\$at\) +0+0074 <[^>]*> bc457fff cache 0x5,32767\(\$v0\) +0+0078 <[^>]*> bc658000 cache 0x5,-32768\(\$v1\) +0+007c <[^>]*> 42000018 eret +0+0080 <[^>]*> 42000008 tlbp +0+0084 <[^>]*> 42000001 tlbr +0+0088 <[^>]*> 42000002 tlbwi +0+008c <[^>]*> 42000006 tlbwr +0+0090 <[^>]*> 42000020 wait +0+0094 <[^>]*> 42000020 wait +0+0098 <[^>]*> 4359e260 wait 0x56789 +0+009c <[^>]*> 00000000 nop diff --git a/gas/testsuite/gas/mips/mips32.s b/gas/testsuite/gas/mips/mips32.s new file mode 100644 index 0000000..240909a --- /dev/null +++ b/gas/testsuite/gas/mips/mips32.s @@ -0,0 +1,63 @@ +# source file to test assembly of mips32 instructions + + .set noreorder + .set noat + + .globl text_label .text +text_label: + + # unprivileged CPU instructions + + clo $1, $2 + clz $3, $4 + madd $5, $6 # disassembles as mad ... + maddu $7, $8 # disassembles as madu ... + msub $9, $10 + msubu $11, $12 + mul $13, $14, $15 + pref 4, ($16) + pref 4, 32767($17) + pref 4, -32768($18) + ssnop + + + # unprivileged coprocessor instructions. + # these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes. + + bc2f text_label + nop + bc2fl text_label + nop + bc2t text_label + nop + bc2tl text_label + nop + # XXX other BCzCond encodings not currently expressable + cfc2 $1, $2 + cop2 0x1234567 # disassembles as c2 ... + ctc2 $2, $3 + mfc2 $3, $4 + mfc2 $4, $5, 0 # disassembles without sel + mfc2 $5, $6, 7 + mtc2 $6, $7 + mtc2 $7, $8, 0 # disassembles without sel + mtc2 $8, $9, 7 + + + # privileged instructions + + cache 5, ($1) + cache 5, 32767($2) + cache 5, -32768($3) + eret + tlbp + tlbr + tlbwi + tlbwr + wait + wait 0 # disassembles without code + wait 0x56789 + + # padding to a cache line boundary so it's more likely to + # pass everywhere + nop |