diff options
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/config/tc-m32c.c | 26 | ||||
| -rw-r--r-- | gas/doc/c-m32c.texi | 68 |
3 files changed, 100 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 9ffaff5..8a6d0c0 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2005-07-25 DJ Delorie <dj@redhat.com> + + * config/tc-m32c.c (md_cgen_lookup_reloc): Add 8 bit operands. + Support %mod() modifiers from opcodes. + * doc/c-m32c.texi (M32C-Modifiers): New section. + 2005-07-25 Jan Hubicka <jh@suse.cz> H.J. Lu <hongjiu.lu@intel.com> diff --git a/gas/config/tc-m32c.c b/gas/config/tc-m32c.c index 1a9ca40..9ccc9a7 100644 --- a/gas/config/tc-m32c.c +++ b/gas/config/tc-m32c.c @@ -738,6 +738,27 @@ md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED, int offset; } op_reloc_table[] = { + /* Absolute relocs for 8-bit fields. */ + { M32C_OPERAND_IMM_8_QI, BFD_RELOC_8, 1 }, + { M32C_OPERAND_IMM_16_QI, BFD_RELOC_8, 2 }, + { M32C_OPERAND_IMM_24_QI, BFD_RELOC_8, 3 }, + { M32C_OPERAND_IMM_32_QI, BFD_RELOC_8, 4 }, + { M32C_OPERAND_IMM_40_QI, BFD_RELOC_8, 5 }, + { M32C_OPERAND_IMM_48_QI, BFD_RELOC_8, 6 }, + { M32C_OPERAND_IMM_56_QI, BFD_RELOC_8, 7 }, + { M32C_OPERAND_DSP_8_S8, BFD_RELOC_8, 1 }, + { M32C_OPERAND_DSP_16_S8, BFD_RELOC_8, 2 }, + { M32C_OPERAND_DSP_24_S8, BFD_RELOC_8, 3 }, + { M32C_OPERAND_DSP_32_S8, BFD_RELOC_8, 4 }, + { M32C_OPERAND_DSP_40_S8, BFD_RELOC_8, 5 }, + { M32C_OPERAND_DSP_48_S8, BFD_RELOC_8, 6 }, + { M32C_OPERAND_DSP_8_U8, BFD_RELOC_8, 1 }, + { M32C_OPERAND_DSP_16_U8, BFD_RELOC_8, 2 }, + { M32C_OPERAND_DSP_24_U8, BFD_RELOC_8, 3 }, + { M32C_OPERAND_DSP_32_U8, BFD_RELOC_8, 4 }, + { M32C_OPERAND_DSP_40_U8, BFD_RELOC_8, 5 }, + { M32C_OPERAND_DSP_48_U8, BFD_RELOC_8, 6 }, + /* Absolute relocs for 16-bit fields. */ { M32C_OPERAND_IMM_16_HI, BFD_RELOC_16, 2 }, { M32C_OPERAND_IMM_24_HI, BFD_RELOC_16, 3 }, @@ -777,6 +798,11 @@ md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED, { fixP->fx_where += or->offset; fixP->fx_size -= or->offset; + + if (fixP->fx_cgen.opinfo + && fixP->fx_cgen.opinfo != BFD_RELOC_NONE) + return fixP->fx_cgen.opinfo; + return or->reloc; } } diff --git a/gas/doc/c-m32c.texi b/gas/doc/c-m32c.texi index 83cda7d..a49fe20 100644 --- a/gas/doc/c-m32c.texi +++ b/gas/doc/c-m32c.texi @@ -21,6 +21,7 @@ change the default to the M32C microprocessor. @menu * M32C-Opts:: M32C Options +* M32C-Modifiers:: Symbolic Operand Modifiers @end menu @node M32C-Opts @@ -46,3 +47,70 @@ Assemble M32C instructions. Assemble M16C instructions (default). @end table + +@node M32C-Modifiers +@section Symbolic Operand Modifiers + +@cindex M32C modifiers +@cindex syntax, M32C + +The assembler supports several modifiers when using symbol addresses +in M32C instruction operands. The general syntax is the following: + +@smallexample +%modifier(symbol) +@end smallexample + +@table @code +@cindex symbol modifiers + +@item %dsp8 +@itemx %dsp16 + +These modifiers override the assembler's assumptions about how big a +symbol's address is. Normally, when it sees an operand like +@samp{sym[a0]} it assumes @samp{sym} may require the widest +displacement field (16 bits for @samp{-m16c}, 24 bits for +@samp{-m32c}). These modifiers tell it to assume the address will fit +in an 8 or 16 bit (respectively) unsigned displacement. Note that, of +course, if it doesn't actually fit you will get linker errors. Example: + +@smallexample +mov.w %dsp8(sym)[a0],r1 +mov.b #0,%dsp8(sym)[a0] +@end smallexample + +@item %hi8 + +This modifier allows you to load bits 16 through 23 of a 24 bit +address into an 8 bit register. This is useful with, for example, the +M16C @samp{smovf} instruction, which expects a 20 bit address in +@samp{r1h} and @samp{a0}. Example: + +@smallexample +mov.b #%hi8(sym),r1h +mov.w #%lo16(sym),a0 +smovf.b +@end smallexample + +@item %lo16 + +Likewise, this modifier allows you to load bits 0 through 15 of a 24 +bit address into a 16 bit register. + +@item %hi16 + +This modifier allows you to load bits 16 through 31 of a 32 bit +address into a 16 bit register. While the M32C family only has 24 +bits of address space, it does support addresses in pairs of 16 bit +registers (like @samp{a1a0} for the @samp{lde} instruction). This +modifier is for loading the upper half in such cases. Example: + +@smallexample +mov.w #%hi16(sym),a1 +mov.w #%lo16(sym),a0 +@dots{} +lde.w [a1a0],r1 +@end smallexample + +@end table |