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-rw-r--r--gas/ChangeLog16
-rw-r--r--gas/config/tc-arm.c78
-rw-r--r--gas/doc/c-arm.texi8
-rw-r--r--gas/testsuite/ChangeLog6
-rw-r--r--gas/testsuite/gas/arm/tls.d48
-rw-r--r--gas/testsuite/gas/arm/tls.s42
6 files changed, 169 insertions, 29 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 9d3d46e..63d2301 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,19 @@
+2011-01-10 Nathan Sidwell <nathan@codesourcery.com>
+ Glauber de Oliveira Costa <glommer@gmail.com>
+
+ * doc/c-arm.texi: Document TLSDESC and TLSCALL relocations, and
+ .tlsdescseq directive.
+ * config/tc-arm.c (arm_typed_reg_parse): Check for potential reloc
+ following a symbol.
+ (s_arm_tls_descseq): New directive.
+ (md_pseudo_table): Add it.
+ (encode_branch): Allow TLS_CALL relocs too.
+ (do_t_blx, do_t_branch23): Use encode_branch.
+ (reloc_names): Add tlsdesc and tlscall.
+ (md_apply_fix): Process tls desc relocations.
+ (tc_gen_reloc): Likewise.
+ (arm_fix_adjustable): Likewise.
+
2011-01-07 Quentin Neill <quentin.neill@amd.com>
* config/tc-i386.c (cpu_arch): Add CPU_BMI_FLAGS.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index f4ebdc4..ae389f5 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -1472,6 +1472,10 @@ arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
if (reg == FAIL)
return FAIL;
+ /* Do not allow regname(... to parse as a register. */
+ if (*str == '(')
+ return FAIL;
+
/* Do not allow a scalar (reg+index) to parse as a register. */
if ((atype.defined & NTA_HASINDEX) != 0)
{
@@ -4273,6 +4277,30 @@ s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
}
#endif /* OBJ_ELF */
+/* Emit a tls fix for the symbol. */
+
+static void
+s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
+{
+ char *p;
+ expressionS exp;
+#ifdef md_flush_pending_output
+ md_flush_pending_output ();
+#endif
+
+#ifdef md_cons_align
+ md_cons_align (4);
+#endif
+
+ /* Since we're just labelling the code, there's no need to define a
+ mapping symbol. */
+ expression (&exp);
+ p = obstack_next_free (&frchain_now->frch_obstack);
+ fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
+ thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
+ : BFD_RELOC_ARM_TLS_DESCSEQ);
+}
+
static void s_arm_arch (int);
static void s_arm_object_arch (int);
static void s_arm_cpu (int);
@@ -4352,6 +4380,7 @@ const pseudo_typeS md_pseudo_table[] =
{ "setfp", s_arm_unwind_setfp, 0 },
{ "unwind_raw", s_arm_unwind_raw, 0 },
{ "eabi_attribute", s_arm_eabi_attribute, 0 },
+ { "tlsdescseq", s_arm_tls_descseq, 0 },
#else
{ "word", cons, 4},
@@ -7281,9 +7310,12 @@ encode_branch (int default_reloc)
{
if (inst.operands[0].hasreloc)
{
- constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
- _("the only suffix valid here is '(plt)'"));
- inst.reloc.type = BFD_RELOC_ARM_PLT32;
+ constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
+ && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
+ _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
+ inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
+ ? BFD_RELOC_ARM_PLT32
+ : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
}
else
inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
@@ -9655,8 +9687,7 @@ do_t_blx (void)
{
/* No register. This must be BLX(1). */
inst.instruction = 0xf000e800;
- inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
- inst.reloc.pc_rel = 1;
+ encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
}
}
@@ -9734,8 +9765,15 @@ static void
do_t_branch23 (void)
{
set_it_insn_type_last ();
- inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
- inst.reloc.pc_rel = 1;
+ encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
+
+ /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
+ this file. We used to simply ignore the PLT reloc type here --
+ the branch encoding is now needed to deal with TLSCALL relocs.
+ So if we see a PLT reloc now, put it back to how it used to be to
+ keep the preexisting behaviour. */
+ if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
+ inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
#if defined(OBJ_COFF)
/* If the destination of the branch is a defined symbol which does not have
@@ -16517,7 +16555,13 @@ static struct reloc_entry reloc_names[] =
{ "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
{ "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
{ "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
- { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL}
+ { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
+ { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
+ { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
+ { "tlscall", BFD_RELOC_ARM_TLS_CALL},
+ { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
+ { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
+ { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
};
#endif
@@ -20835,6 +20879,14 @@ md_apply_fix (fixS * fixP,
break;
#ifdef OBJ_ELF
+ case BFD_RELOC_ARM_TLS_CALL:
+ case BFD_RELOC_ARM_THM_TLS_CALL:
+ case BFD_RELOC_ARM_TLS_DESCSEQ:
+ case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
+ S_SET_THREAD_LOCAL (fixP->fx_addsy);
+ break;
+
+ case BFD_RELOC_ARM_TLS_GOTDESC:
case BFD_RELOC_ARM_TLS_GD32:
case BFD_RELOC_ARM_TLS_LE32:
case BFD_RELOC_ARM_TLS_IE32:
@@ -21436,6 +21488,10 @@ tc_gen_reloc (asection *section, fixS *fixp)
return NULL;
#ifdef OBJ_ELF
+ case BFD_RELOC_ARM_TLS_CALL:
+ case BFD_RELOC_ARM_THM_TLS_CALL:
+ case BFD_RELOC_ARM_TLS_DESCSEQ:
+ case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
case BFD_RELOC_ARM_GOT32:
case BFD_RELOC_ARM_GOTOFF:
case BFD_RELOC_ARM_GOT_PREL:
@@ -21481,6 +21537,7 @@ tc_gen_reloc (asection *section, fixS *fixp)
code = fixp->fx_r_type;
break;
+ case BFD_RELOC_ARM_TLS_GOTDESC:
case BFD_RELOC_ARM_TLS_GD32:
case BFD_RELOC_ARM_TLS_IE32:
case BFD_RELOC_ARM_TLS_LDM32:
@@ -21742,6 +21799,11 @@ arm_fix_adjustable (fixS * fixP)
|| fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
|| fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
|| fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
+ || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
+ || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
+ || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
+ || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
+ || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
|| fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
return FALSE;
diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index d3cccf4..e14cc2e 100644
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -478,6 +478,8 @@ The following relocations are supported:
@code{TLSGD},
@code{TLSLDM},
@code{TLSLDO},
+@code{TLSDESC},
+@code{TLSCALL},
@code{GOTTPOFF},
@code{GOT_PREL}
and
@@ -864,6 +866,12 @@ defined). This directive also has the added property in that it marks
the aliased symbol as being a thumb function entry point, in the same
way that the @code{.thumb_func} directive does.
+@cindex @code{.tlsdescseq} directive, ARM
+@item .tlsdescseq @var{tls-variable}
+This directive is used to annotate parts of an inlined TLS descriptor
+trampoline. Normally the trampoline is provided by the linker, and
+this directive is not needed.
+
@c UUUUUUUUUUUUUUUUUUUUUUUUUU
@cindex @code{.unreq} directive, ARM
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 67eee86..d28da8d 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2011-01-10 Nathan Sidwell <nathan@codesourcery.com>
+ Glauber de Oliveira Costa <glommer@gmail.com>
+
+ * gas/arm/tls.s: Add tlsdesc tests.
+ * gas/arm/tls.d: Adjust.
+
2011-01-07 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/ilp32/x86-64-arch-2.d: Add bmi flag and BMI instruction
diff --git a/gas/testsuite/gas/arm/tls.d b/gas/testsuite/gas/arm/tls.d
index 6401f29..727f8e4 100644
--- a/gas/testsuite/gas/arm/tls.d
+++ b/gas/testsuite/gas/arm/tls.d
@@ -11,15 +11,39 @@
Disassembly of section .text:
-00+0 <main>:
- 0: e1a00000 nop ; \(mov r0, r0\)
- 4: e1a00000 nop ; \(mov r0, r0\)
- 8: e1a0f00e mov pc, lr
- c: 00000000 .word 0x00000000
- c: R_ARM_TLS_GD32 a
- 10: 00000004 .word 0x00000004
- 10: R_ARM_TLS_LDM32 b
- 14: 00000008 .word 0x00000008
- 14: R_ARM_TLS_IE32 c
- 18: 00000000 .word 0x00000000
- 18: R_ARM_TLS_LE32 d
+0+00 <arm_fn>:
+ 0: e1a00000 nop ; .*
+ 0: R_ARM_TLS_DESCSEQ af
+ 4: e59f0014 ldr r0, \[pc, #20\] ; 20 .*
+ 8: fa000000 blx 8 <ae\+.*>
+ 8: R_ARM_TLS_CALL ae
+ c: e1a00000 nop ; .*
+0+10 <.arm_pool>:
+ 10: 00000008 .word 0x00000008
+ 10: R_ARM_TLS_GD32 aa
+ 14: 0000000c .word 0x0000000c
+ 14: R_ARM_TLS_LDM32 ab
+ 18: 00000010 .word 0x00000010
+ 18: R_ARM_TLS_IE32 ac
+ 1c: 00000000 .word 0x00000000
+ 1c: R_ARM_TLS_LE32 ad
+ 20: 00000018 .word 0x00000018
+ 20: R_ARM_TLS_GOTDESC ae
+0+24 <thumb_fn>:
+ 24: 46c0 nop ; .*
+ 26: 46c0 nop ; .*
+ 26: R_ARM_THM_TLS_DESCSEQ tf
+ 28: 4805 ldr r0, \[pc, #20\] ; \(40 .*\)
+ 2a: f000 e800 blx 4 <te\+0x4>
+ 2a: R_ARM_THM_TLS_CALL te
+ 2e: 46c0 nop ; .*
+ 30: 00000002 .word 0x00000002
+ 30: R_ARM_TLS_GD32 ta
+ 34: 00000006 .word 0x00000006
+ 34: R_ARM_TLS_LDM32 tb
+ 38: 0000000a .word 0x0000000a
+ 38: R_ARM_TLS_IE32 tc
+ 3c: 00000000 .word 0x00000000
+ 3c: R_ARM_TLS_LE32 td
+ 40: 00000017 .word 0x00000017
+ 40: R_ARM_TLS_GOTDESC te
diff --git a/gas/testsuite/gas/arm/tls.s b/gas/testsuite/gas/arm/tls.s
index 48722a4..96a25f5 100644
--- a/gas/testsuite/gas/arm/tls.s
+++ b/gas/testsuite/gas/arm/tls.s
@@ -1,14 +1,38 @@
.text
- .globl main
- .type main, %function
-main:
+ .arm
+ .globl arm_fn
+ .type arm_fn, %function
+arm_fn:
+1:
+.tlsdescseq af
nop
-.L2:
+ ldr r0, 1f
+2: blx ae(tlscall)
nop
- mov pc, lr
+.arm_pool:
+ .word aa(tlsgd) + (. - 1b - 8)
+ .word ab(tlsldm) + (. - 1b- 8)
+ .word ac(gottpoff) + (. - 1b - 8)
+ .word ad(tpoff)
+1: .word ae(tlsdesc) + (. - 2b)
+
+ .thumb
+ .globl thumb_fn
+ .type thumb_fn, %function
+thumb_fn:
+ nop
+1:
+.tlsdescseq tf
+ nop
+ ldr r0, 1f
+2: blx te(tlscall)
+ nop
+
+ .p2align 2
.Lpool:
- .word a(tlsgd) + (. - .L2 - 8)
- .word b(tlsldm) + (. - .L2 - 8)
- .word c(gottpoff) + (. - .L2 - 8)
- .word d(tpoff)
+ .word ta(tlsgd) + (. - 1b - 8)
+ .word tb(tlsldm) + (. - 1b - 8)
+ .word tc(gottpoff) + (. - 1b - 8)
+ .word td(tpoff)
+1: .word te(tlsdesc) + (. - 2b + 1)
generated by cgit v1.1 at 2025-03-01 22:00:40 +0000