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-rw-r--r--gas/ChangeLog6
-rw-r--r--gas/config/bfin-parse.y12
-rw-r--r--gas/testsuite/ChangeLog5
-rw-r--r--gas/testsuite/gas/bfin/expected_errors.l3
-rw-r--r--gas/testsuite/gas/bfin/expected_errors.s4
5 files changed, 26 insertions, 4 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index e283ac5..4c4a03c 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2011-03-24 Mike Frysinger <vapier@gentoo.org>
+
+ * config/bfin-parse.y (check_macfuncs): Clarify error message when
+ P is mismatched. Check destination regno are off by one when P is
+ set, or are equal when P is not set.
+
2011-03-23 Mike Frysinger <vapier@gentoo.org>
* config/bfin-parse.y (SEARCH): Return yyerror when dest reg $2 is
diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y
index fcc2ee8..f20d20b 100644
--- a/gas/config/bfin-parse.y
+++ b/gas/config/bfin-parse.y
@@ -336,11 +336,15 @@ check_macfuncs (Macfunc *aa, Opt_mode *opa,
aa->s1.regno |= (ab->s1.regno & CODE_MASK);
}
- if (aa->w == ab->w && aa->P != ab->P)
+ if (aa->w == ab->w && aa->P != ab->P)
+ return yyerror ("Destination Dreg sizes (full or half) must match");
+
+ if (aa->w && ab->w)
{
- return yyerror ("macfuncs must differ");
- if (aa->w && (aa->dst.regno - ab->dst.regno != 1))
- return yyerror ("Destination Dregs must differ by one");
+ if (aa->P && (aa->dst.regno - ab->dst.regno) != 1)
+ return yyerror ("Destination Dregs (full) must differ by one");
+ if (!aa->P && aa->dst.regno != ab->dst.regno)
+ return yyerror ("Destination Dregs (half) must match");
}
/* Make sure mod flags get ORed, too. */
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 3207362..328d9e8 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2011-03-24 Mike Frysinger <vapier@gentoo.org>
+
+ * gas/bfin/expected_errors.s: Add invalid dsp mult insn tests.
+ * gas/bfin/expected_errors.l: Add new error messages.
+
2011-03-23 Mike Frysinger <vapier@gentoo.org>
* gas/bfin/expected_errors.s: Add invalid SEARCH/BITMUX insns.
diff --git a/gas/testsuite/gas/bfin/expected_errors.l b/gas/testsuite/gas/bfin/expected_errors.l
index 09bfd7f..316ff20 100644
--- a/gas/testsuite/gas/bfin/expected_errors.l
+++ b/gas/testsuite/gas/bfin/expected_errors.l
@@ -92,3 +92,6 @@
.*:115: Error: Dreg expected for destination operand. Input text was \).
.*:117: Error: Illegal dest register combination. Input text was \).
.*:118: Error: Illegal source register combination. Input text was \).
+.*:120: Error: Destination Dregs \(full\) must differ by one.
+.*:121: Error: Destination Dregs \(half\) must match.
+.*:122: Error: Destination Dreg sizes \(full or half\) must match.
diff --git a/gas/testsuite/gas/bfin/expected_errors.s b/gas/testsuite/gas/bfin/expected_errors.s
index 0cea5ff..736613f 100644
--- a/gas/testsuite/gas/bfin/expected_errors.s
+++ b/gas/testsuite/gas/bfin/expected_errors.s
@@ -116,3 +116,7 @@
(R3, R3) = SEARCH R0 (GE);
BITMUX (R4, R4, A0) (ASR);
+
+ R0 = A0, R3 = A1;
+ R0.L = A0, R1.H = A1;
+ R0 = A0, R1.H = A1;