aboutsummaryrefslogtreecommitdiff
path: root/gas
diff options
context:
space:
mode:
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog16
-rw-r--r--gas/config/tc-mips.c134
-rwxr-xr-xgas/configure3
-rw-r--r--gas/configure.in7
-rw-r--r--gas/testsuite/ChangeLog8
-rw-r--r--gas/testsuite/gas/mips/mips.exp71
-rw-r--r--gas/testsuite/gas/mips/r5900-full.d349
-rw-r--r--gas/testsuite/gas/mips/r5900-full.s421
-rw-r--r--gas/testsuite/gas/mips/r5900.d93
-rw-r--r--gas/testsuite/gas/mips/r5900.s135
10 files changed, 1190 insertions, 47 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index a8e3b6a..c78139c 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,19 @@
+2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
+
+ * config/tc-mips.c: Add support for MIPS r5900.
+ Add M_LQ_AB and M_SQ_AB to support large values for instructions
+ lq and sq.
+ (can_swap_branch_p, get_append_method): Detect some conditional
+ short loops to fix a bug on the r5900 by NOP in the branch delay
+ slot.
+ (M_MUL): Support 3 operands in multu on r5900.
+ (M_TRUNCWS): Support trunc.w.s on r5900 in MIPS ISA I.
+ (s_mipsset): Force 32 bit floating point on r5900.
+ (mips_ip): Check parameter range of instructions mfps and mtps on
+ r5900.
+ * configure.in: Detect CPU type when target string contains r5900
+ (e.g. mips64r5900el-linux-gnu).
+
2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
* as.c (parse_args): Update copyright year to 2013.
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 0372b7a..2d8639c 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -1,6 +1,6 @@
/* tc-mips.c -- assemble code for a MIPS chip.
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
- 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
+ 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
Free Software Foundation, Inc.
Contributed by the OSF and Ralph Campbell.
Written by Keith Knowles and Ralph Campbell, working independently.
@@ -171,6 +171,10 @@ struct mips_cl_insn
/* True if this instruction is complete. */
unsigned int complete_p : 1;
+
+ /* True if this instruction is cleared from history by unconditional
+ branch. */
+ unsigned int cleared_p : 1;
};
/* The ABI to use. */
@@ -518,6 +522,7 @@ static int mips_32bitmode = 0;
|| mips_opts.isa == ISA_MIPS64 \
|| mips_opts.isa == ISA_MIPS64R2 \
|| mips_opts.arch == CPU_R4010 \
+ || mips_opts.arch == CPU_R5900 \
|| mips_opts.arch == CPU_R10000 \
|| mips_opts.arch == CPU_R12000 \
|| mips_opts.arch == CPU_R14000 \
@@ -535,6 +540,7 @@ static int mips_32bitmode = 0;
#define gpr_interlocks \
(mips_opts.isa != ISA_MIPS1 \
|| mips_opts.arch == CPU_R3900 \
+ || mips_opts.arch == CPU_R5900 \
|| mips_opts.micromips \
)
@@ -1679,6 +1685,7 @@ create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
insn->noreorder_p = (mips_opts.noreorder > 0);
insn->mips16_absolute_jump_p = 0;
insn->complete_p = 0;
+ insn->cleared_p = 0;
}
/* Record the current MIPS16/microMIPS mode in now_seg. */
@@ -3735,10 +3742,13 @@ fix_loongson2f (struct mips_cl_insn * ip)
/* IP is a branch that has a delay slot, and we need to fill it
automatically. Return true if we can do that by swapping IP
- with the previous instruction. */
+ with the previous instruction.
+ ADDRESS_EXPR is an operand of the instruction to be used with
+ RELOC_TYPE. */
static bfd_boolean
-can_swap_branch_p (struct mips_cl_insn *ip)
+can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
+ bfd_reloc_code_real_type *reloc_type)
{
unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
@@ -3857,13 +3867,64 @@ can_swap_branch_p (struct mips_cl_insn *ip)
&& insn_length (history) != 4)
return FALSE;
+ /* On R5900 short loops need to be fixed by inserting a nop in
+ the branch delay slots.
+ A short loop can be terminated too early. */
+ if (mips_opts.arch == CPU_R5900
+ /* Check if instruction has a parameter, ignore "j $31". */
+ && (address_expr != NULL)
+ /* Parameter must be 16 bit. */
+ && (*reloc_type == BFD_RELOC_16_PCREL_S2)
+ /* Branch to same segment. */
+ && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
+ /* Branch to same code fragment. */
+ && (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
+ /* Can only calculate branch offset if value is known. */
+ && symbol_constant_p(address_expr->X_add_symbol)
+ /* Check if branch is really conditional. */
+ && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
+ || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
+ || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
+ {
+ int distance;
+ /* Check if loop is shorter than 6 instructions including
+ branch and delay slot. */
+ distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
+ if (distance <= 20)
+ {
+ int i;
+ int rv;
+
+ rv = FALSE;
+ /* When the loop includes branches or jumps,
+ it is not a short loop. */
+ for (i = 0; i < (distance / 4); i++)
+ {
+ if ((history[i].cleared_p)
+ || delayed_branch_p(&history[i]))
+ {
+ rv = TRUE;
+ break;
+ }
+ }
+ if (rv == FALSE)
+ {
+ /* Insert nop after branch to fix short loop. */
+ return FALSE;
+ }
+ }
+ }
+
return TRUE;
}
-/* Decide how we should add IP to the instruction stream. */
+/* Decide how we should add IP to the instruction stream.
+ ADDRESS_EXPR is an operand of the instruction to be used with
+ RELOC_TYPE. */
static enum append_method
-get_append_method (struct mips_cl_insn *ip)
+get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
+ bfd_reloc_code_real_type *reloc_type)
{
unsigned long pinfo;
@@ -3879,7 +3940,8 @@ get_append_method (struct mips_cl_insn *ip)
/* Otherwise, it's our responsibility to fill branch delay slots. */
if (delayed_branch_p (ip))
{
- if (!branch_likely_p (ip) && can_swap_branch_p (ip))
+ if (!branch_likely_p (ip)
+ && can_swap_branch_p (ip, address_expr, reloc_type))
return APPEND_SWAP;
pinfo = ip->insn_mo->pinfo;
@@ -4260,7 +4322,7 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
}
}
- method = get_append_method (ip);
+ method = get_append_method (ip, address_expr, reloc_type);
branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
#ifdef OBJ_ELF
@@ -4578,8 +4640,17 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
/* If we have just completed an unconditional branch, clear the history. */
if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
|| (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
+ {
+ unsigned int i;
+
mips_no_prev_insn ();
+ for (i = 0; i < ARRAY_SIZE (history); i++)
+ {
+ history[i].cleared_p = 1;
+ }
+ }
+
/* We need to emit a label at the end of branch-likely macros. */
if (emit_branch_likely_macro)
{
@@ -4591,7 +4662,8 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
mips_clear_insn_labels ();
}
-/* Forget that there was any previous instruction or label. */
+/* Forget that there was any previous instruction or label.
+ When BRANCH is true, the branch history is also flushed. */
static void
mips_no_prev_insn (void)
@@ -8858,7 +8930,8 @@ macro (struct mips_cl_insn *ip)
s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
if (strcmp (s, ".lit8") == 0)
{
- if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
+ if ((mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
+ && (mips_opts.arch != CPU_R5900))
{
macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
BFD_RELOC_MIPS_LITERAL, mips_gp_register);
@@ -8881,7 +8954,8 @@ macro (struct mips_cl_insn *ip)
macro_build_lui (&offset_expr, AT);
}
- if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
+ if ((mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
+ && (mips_opts.arch != CPU_R5900))
{
macro_build (&offset_expr, "ldc1", "T,o(b)",
treg, BFD_RELOC_LO16, AT);
@@ -8898,7 +8972,8 @@ macro (struct mips_cl_insn *ip)
r = BFD_RELOC_LO16;
dob:
gas_assert (!mips_opts.micromips);
- gas_assert (mips_opts.isa == ISA_MIPS1);
+ gas_assert ((mips_opts.isa == ISA_MIPS1)
+ || (mips_opts.arch == CPU_R5900));
macro_build (&offset_expr, "lwc1", "T,o(b)",
target_big_endian ? treg + 1 : treg, r, breg);
/* FIXME: A possible overflow which I don't know how to deal
@@ -8936,7 +9011,7 @@ macro (struct mips_cl_insn *ip)
/* Itbl support may require additional care here. */
coproc = 1;
fmt = "T,o(b)";
- if (mips_opts.isa != ISA_MIPS1)
+ if ((mips_opts.isa != ISA_MIPS1) && (mips_opts.arch != CPU_R5900))
{
s = "ldc1";
goto ld_st;
@@ -8949,7 +9024,7 @@ macro (struct mips_cl_insn *ip)
/* Itbl support may require additional care here. */
coproc = 1;
fmt = "T,o(b)";
- if (mips_opts.isa != ISA_MIPS1)
+ if ((mips_opts.isa != ISA_MIPS1) && (mips_opts.arch != CPU_R5900))
{
s = "sdc1";
goto ld_st;
@@ -8957,6 +9032,16 @@ macro (struct mips_cl_insn *ip)
s = "swc1";
goto ldd_std;
+ case M_LQ_AB:
+ fmt = "t,o(b)";
+ s = "lq";
+ goto ld;
+
+ case M_SQ_AB:
+ fmt = "t,o(b)";
+ s = "sq";
+ goto ld_st;
+
case M_LD_AB:
fmt = "t,o(b)";
if (HAVE_64BIT_GPRS)
@@ -9269,8 +9354,15 @@ macro (struct mips_cl_insn *ip)
case M_DMUL:
dbl = 1;
case M_MUL:
+ if (mips_opts.arch == CPU_R5900)
+ {
+ macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg);
+ }
+ else
+ {
macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
macro_build (NULL, "mflo", MFHL_FMT, dreg);
+ }
break;
case M_DMUL_I:
@@ -9833,7 +9925,7 @@ macro (struct mips_cl_insn *ip)
case M_TRUNCWS:
case M_TRUNCWD:
gas_assert (!mips_opts.micromips);
- gas_assert (mips_opts.isa == ISA_MIPS1);
+ gas_assert ((mips_opts.isa == ISA_MIPS1) || (mips_opts.arch == CPU_R5900));
used_at = 1;
sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
@@ -10638,7 +10730,7 @@ mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
/* Let a macro pass, we'll catch it later when it is expanded. */
return 1;
- if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
+ if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900))
{
/* Allow odd registers for single-precision ops. */
switch (insn->pinfo & (FP_S | FP_D))
@@ -11789,6 +11881,10 @@ mips_ip (char *str, struct mips_cl_insn *ip)
if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
as_warn (_("Invalid performance register (%lu)"),
(unsigned long) imm_expr.X_add_number);
+ if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900
+ && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps")))
+ as_warn (_("Invalid performance register (%lu)"),
+ (unsigned long) imm_expr.X_add_number);
INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
@@ -16380,7 +16476,14 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
case ISA_MIPS64:
case ISA_MIPS64R2:
mips_opts.gp32 = 0;
+ if (mips_opts.arch == CPU_R5900)
+ {
+ mips_opts.fp32 = 1;
+ }
+ else
+ {
mips_opts.fp32 = 0;
+ }
break;
default:
as_bad (_("unknown ISA level %s"), name + 4);
@@ -19082,6 +19185,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
{ "r4600", 0, ISA_MIPS3, CPU_R4600 },
{ "orion", 0, ISA_MIPS3, CPU_R4600 },
{ "r4650", 0, ISA_MIPS3, CPU_R4650 },
+ { "r5900", 0, ISA_MIPS3, CPU_R5900 },
/* ST Microelectronics Loongson 2E and 2F cores */
{ "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
{ "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
diff --git a/gas/configure b/gas/configure
index cd9e5a4..382f8d3 100755
--- a/gas/configure
+++ b/gas/configure
@@ -12060,6 +12060,9 @@ _ACEOF
mips64* | mipsisa64* | mipsisa32*)
mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..//' -e 's/el$//'`
;;
+ mips*)
+ mips_cpu=`echo $target_cpu | sed -e 's/^mips//' -e 's/el$//'`
+ ;;
*)
as_fn_error "$target_cpu isn't a supported MIPS CPU name" "$LINENO" 5
;;
diff --git a/gas/configure.in b/gas/configure.in
index a795d0d..88cbff8c 100644
--- a/gas/configure.in
+++ b/gas/configure.in
@@ -3,7 +3,7 @@ dnl
dnl And be careful when changing it! If you must add tests with square
dnl brackets, be sure changequote invocations surround it.
dnl
-dnl Copyright 2012 Free Software Foundation
+dnl Copyright 2012, 2013 Free Software Foundation
dnl
dnl This file is free software; you can redistribute it and/or modify
dnl it under the terms of the GNU General Public License as published by
@@ -247,6 +247,11 @@ changequote(,)dnl
mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..//' -e 's/el$//'`
changequote([,])dnl
;;
+ mips*)
+changequote(,)dnl
+ mips_cpu=`echo $target_cpu | sed -e 's/^mips//' -e 's/el$//'`
+changequote([,])dnl
+ ;;
*)
AC_MSG_ERROR($target_cpu isn't a supported MIPS CPU name)
;;
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 3cc89a6..0cb2856 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
+
+ * gas/mips/r5900-full.s: New test.
+ * gas/mips/r5900-full.d: Expected disassembly.
+ * gas/mips/r5900.s: New test.
+ * gas/mips/r5900.d: Expected disassembly.
+ * gas/mips/mips.exp: Run new tests.
+
2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/int-insns.d: Update.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 87637a7..8de1cad 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1,4 +1,4 @@
-# Copyright 2012
+# Copyright 2012, 2013
# Free Software Foundation, Inc.
# This program is free software; you can redistribute it and/or modify
@@ -88,6 +88,9 @@
# The architecture provides 32- or 64-bit General Purpose
# Registers.
#
+# singlefloat
+# The CPU is 64 bit, but only supports 32 bit FPU.
+#
# as_flags: The assembler flags used when assembling tests for this
# architecture.
#
@@ -460,6 +463,9 @@ mips_arch_create octeon2 64 octeonp {} \
{ }
mips_arch_create xlr 64 mips64 {} \
{ -march=xlr -mtune=xlr } { -mmips:xlr }
+mips_arch_create r5900 64 mips3 { gpr_ilocks singlefloat } \
+ { -march=r5900 -mtune=r5900 } { -mmips:5900 } \
+ { mipsr5900el-*-* mips64r5900el-*-* }
#
# And now begin the actual tests! VxWorks uses RELA rather than REL
@@ -563,13 +569,13 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "24k-triple-stores-3" \
[mips_arch_list_matching mips2]
run_dump_test_arches "24k-triple-stores-4" \
- [mips_arch_list_matching mips2]
+ [mips_arch_list_matching mips2 !singlefloat]
run_dump_test_arches "24k-triple-stores-5" \
[mips_arch_list_matching mips1]
run_dump_test_arches "24k-triple-stores-6" \
- [mips_arch_list_matching mips2]
+ [mips_arch_list_matching mips2 !singlefloat]
run_dump_test_arches "24k-triple-stores-7" \
- [mips_arch_list_matching mips2]
+ [mips_arch_list_matching mips2 !singlefloat]
run_dump_test_arches "24k-triple-stores-8" \
[mips_arch_list_matching mips1]
run_dump_test_arches "24k-triple-stores-9" \
@@ -618,18 +624,18 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "sd" [mips_arch_list_matching mips1]
run_dump_test_arches "sd-forward" \
[mips_arch_list_matching mips1]
- run_dump_test_arches "l_d" [mips_arch_list_matching mips1]
+ run_dump_test_arches "l_d" [mips_arch_list_matching mips1 !singlefloat]
run_dump_test_arches "l_d-forward" \
- [mips_arch_list_matching mips1]
- run_dump_test_arches "s_d" [mips_arch_list_matching mips1]
+ [mips_arch_list_matching mips1 !singlefloat]
+ run_dump_test_arches "s_d" [mips_arch_list_matching mips1 !singlefloat]
run_dump_test_arches "s_d-forward" \
- [mips_arch_list_matching mips1]
- run_dump_test_arches "ldc1" [mips_arch_list_matching mips2]
+ [mips_arch_list_matching mips1 !singlefloat]
+ run_dump_test_arches "ldc1" [mips_arch_list_matching mips2 !singlefloat]
run_dump_test_arches "ldc1-forward" \
- [mips_arch_list_matching mips2]
- run_dump_test_arches "sdc1" [mips_arch_list_matching mips2]
+ [mips_arch_list_matching mips2 !singlefloat]
+ run_dump_test_arches "sdc1" [mips_arch_list_matching mips2 !singlefloat]
run_dump_test_arches "sdc1-forward" \
- [mips_arch_list_matching mips2]
+ [mips_arch_list_matching mips2 !singlefloat]
if $has_newabi {
run_dump_test_arches "ld-n32" \
[mips_arch_list_matching mips3]
@@ -640,21 +646,21 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "sd-forward-n32" \
[mips_arch_list_matching mips3]
run_dump_test_arches "l_d-n32" \
- [mips_arch_list_matching mips3]
+ [mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "l_d-forward-n32" \
- [mips_arch_list_matching mips3]
+ [mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "s_d-n32" \
- [mips_arch_list_matching mips3]
+ [mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "s_d-forward-n32" \
- [mips_arch_list_matching mips3]
+ [mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "ldc1-n32" \
- [mips_arch_list_matching mips3]
+ [mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "ldc1-forward-n32" \
- [mips_arch_list_matching mips3]
+ [mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "sdc1-n32" \
- [mips_arch_list_matching mips3]
+ [mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "sdc1-forward-n32" \
- [mips_arch_list_matching mips3]
+ [mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "ld-n64" \
[mips_arch_list_matching mips3]
run_dump_test_arches "ld-forward-n64" \
@@ -664,21 +670,21 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "sd-forward-n64" \
[mips_arch_list_matching mips3]
run_dump_test_arches "l_d-n64" \
- [mips_arch_list_matching mips3]
+ [mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "l_d-forward-n64" \
- [mips_arch_list_matching mips3]
+ [mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "s_d-n64" \
- [mips_arch_list_matching mips3]
+ [mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "s_d-forward-n64" \
- [mips_arch_list_matching mips3]
+ [mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "ldc1-n64" \
- [mips_arch_list_matching mips3]
+ [mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "ldc1-forward-n64" \
- [mips_arch_list_matching mips3]
+ [mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "sdc1-n64" \
- [mips_arch_list_matching mips3]
+ [mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "sdc1-forward-n64" \
- [mips_arch_list_matching mips3]
+ [mips_arch_list_matching mips3 !singlefloat]
}
}
if $elf { run_dump_test "ld-svr4pic" }
@@ -876,7 +882,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "mips-abi32-pic2"
run_dump_test "elf${el}-rel"
- run_dump_test_arches "elf${el}-rel2" [mips_arch_list_matching gpr64]
+ run_dump_test_arches "elf${el}-rel2" [mips_arch_list_matching gpr64 !singlefloat]
run_dump_test "e32${el}-rel2"
run_dump_test "elf${el}-rel3"
run_dump_test_arches "elf-rel4" [mips_arch_list_matching gpr64]
@@ -1096,10 +1102,10 @@ if { [istarget mips*-*-vxworks*] } {
run_list_test_arches "mips-hard-float-flag" \
"-32 -msoft-float -mhard-float" \
- [mips_arch_list_matching mips1]
+ [mips_arch_list_matching mips1 !singlefloat]
run_list_test_arches "mips-double-float-flag" \
"-32 -msingle-float -mdouble-float" \
- [mips_arch_list_matching mips1]
+ [mips_arch_list_matching mips1 !singlefloat]
run_dump_test "mips16-vis-1"
run_dump_test "call-nonpic-1"
@@ -1148,4 +1154,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "lui" [mips_arch_list_matching mips1]
run_list_test_arches "lui-1" "-32" [mips_arch_list_matching mips1]
run_list_test_arches "lui-2" "-32" [mips_arch_list_matching mips1]
+
+ run_dump_test "r5900"
+ run_dump_test "r5900-full"
}
diff --git a/gas/testsuite/gas/mips/r5900-full.d b/gas/testsuite/gas/mips/r5900-full.d
new file mode 100644
index 0000000..b3cc442
--- /dev/null
+++ b/gas/testsuite/gas/mips/r5900-full.d
@@ -0,0 +1,349 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric -mmips:5900
+#name: Full MIPS R5900
+#as: -march=r5900 -mtune=r5900
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 001f0020 add \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 01430820 add \$1,\$10,\$3
+[0-9a-f]+ <[^>]*> 03e0f820 add \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 201f0000 addi \$31,\$0,0
+[0-9a-f]+ <[^>]*> 21410003 addi \$1,\$10,3
+[0-9a-f]+ <[^>]*> 23e0ffff addi \$0,\$31,-1
+[0-9a-f]+ <[^>]*> 241f0000 li \$31,0
+[0-9a-f]+ <[^>]*> 25410003 addiu \$1,\$10,3
+[0-9a-f]+ <[^>]*> 241fffff li \$31,-1
+[0-9a-f]+ <[^>]*> 001f0024 and \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 01430824 and \$1,\$10,\$3
+[0-9a-f]+ <[^>]*> 03e0f824 and \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 301f0000 andi \$31,\$0,0x0
+[0-9a-f]+ <[^>]*> 31410003 andi \$1,\$10,0x3
+[0-9a-f]+ <[^>]*> 33e0ffff andi \$0,\$31,0xffff
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 461f0018 adda\.s \$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f818 adda\.s \$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f0034 c\.lt\.s \$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f834 c\.lt\.s \$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f0036 c\.le\.s \$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f836 c\.le\.s \$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f0032 c\.eq\.s \$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f832 c\.eq\.s \$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f0030 c\.f\.s \$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f830 c\.f\.s \$f31,\$f0
+[0-9a-f]+ <[^>]*> 4600f824 trunc\.w\.s \$f0,\$f31
+[0-9a-f]+ <[^>]*> 460007e4 trunc\.w\.s \$f31,\$f0
+[0-9a-f]+ <[^>]*> 42000039 di
+[0-9a-f]+ <[^>]*> 42000038 ei
+[0-9a-f]+ <[^>]*> 703f001a div1 \$0,\$1,\$31
+[0-9a-f]+ <[^>]*> 73e1001a div1 \$0,\$31,\$1
+[0-9a-f]+ <[^>]*> 703f001b divu1 \$0,\$1,\$31
+[0-9a-f]+ <[^>]*> 73e1001b divu1 \$0,\$31,\$1
+[0-9a-f]+ <[^>]*> 7c000000 sq \$0,0\(\$0\)
+[0-9a-f]+ <[^>]*> 7c217fff sq \$1,32767\(\$1\)
+[0-9a-f]+ <[^>]*> 7d088000 sq \$8,-32768\(\$8\)
+[0-9a-f]+ <[^>]*> 7fffffff sq \$31,-1\(\$31\)
+[0-9a-f]+ <[^>]*> 78000000 lq \$0,0\(\$0\)
+[0-9a-f]+ <[^>]*> 78217fff lq \$1,32767\(\$1\)
+[0-9a-f]+ <[^>]*> 79088000 lq \$8,-32768\(\$8\)
+[0-9a-f]+ <[^>]*> 7bffffff lq \$31,-1\(\$31\)
+[0-9a-f]+ <[^>]*> cc000000 pref 0x0,0\(\$0\)
+[0-9a-f]+ <[^>]*> cc217fff pref 0x1,32767\(\$1\)
+[0-9a-f]+ <[^>]*> cd088000 pref 0x8,-32768\(\$8\)
+[0-9a-f]+ <[^>]*> cfffffff pref 0x1f,-1\(\$31\)
+[0-9a-f]+ <[^>]*> 4600f81c madd\.s \$f0,\$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f07dc madd\.s \$f31,\$f0,\$f31
+[0-9a-f]+ <[^>]*> 701f0021 maddu1 \$0,\$31
+[0-9a-f]+ <[^>]*> 73e00021 maddu1 \$31,\$0
+[0-9a-f]+ <[^>]*> 701f0021 maddu1 \$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f821 maddu1 \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0020 madd1 \$0,\$31
+[0-9a-f]+ <[^>]*> 73e00020 madd1 \$31,\$0
+[0-9a-f]+ <[^>]*> 701f0020 madd1 \$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f820 madd1 \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 461f001e madda\.s \$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f81e madda\.s \$f31,\$f0
+[0-9a-f]+ <[^>]*> 4600f828 max\.s \$f0,\$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f07e8 max\.s \$f31,\$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f829 min\.s \$f0,\$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f07e9 min\.s \$f31,\$f0,\$f31
+[0-9a-f]+ <[^>]*> 401fc801 mfpc \$31,0
+[0-9a-f]+ <[^>]*> 4000c803 mfpc \$0,1
+[0-9a-f]+ <[^>]*> 4000c800 mfps \$0,0
+[0-9a-f]+ <[^>]*> 401fc800 mfps \$31,0
+[0-9a-f]+ <[^>]*> 409fc801 mtpc \$31,0
+[0-9a-f]+ <[^>]*> 4080c803 mtpc \$0,1
+[0-9a-f]+ <[^>]*> 4080c800 mtps \$0,0
+[0-9a-f]+ <[^>]*> 409fc800 mtps \$31,0
+[0-9a-f]+ <[^>]*> 4000c000 mfbpc \$0
+[0-9a-f]+ <[^>]*> 401fc000 mfbpc \$31
+[0-9a-f]+ <[^>]*> 4080c000 mtbpc \$0
+[0-9a-f]+ <[^>]*> 409fc000 mtbpc \$31
+[0-9a-f]+ <[^>]*> 4000c004 mfdab \$0
+[0-9a-f]+ <[^>]*> 401fc004 mfdab \$31
+[0-9a-f]+ <[^>]*> 4080c004 mtdab \$0
+[0-9a-f]+ <[^>]*> 409fc004 mtdab \$31
+[0-9a-f]+ <[^>]*> 4000c005 mfdabm \$0
+[0-9a-f]+ <[^>]*> 401fc005 mfdabm \$31
+[0-9a-f]+ <[^>]*> 4080c005 mtdabm \$0
+[0-9a-f]+ <[^>]*> 409fc005 mtdabm \$31
+[0-9a-f]+ <[^>]*> 4000c006 mfdvb \$0
+[0-9a-f]+ <[^>]*> 401fc006 mfdvb \$31
+[0-9a-f]+ <[^>]*> 4080c006 mtdvb \$0
+[0-9a-f]+ <[^>]*> 409fc006 mtdvb \$31
+[0-9a-f]+ <[^>]*> 4000c007 mfdvbm \$0
+[0-9a-f]+ <[^>]*> 401fc007 mfdvbm \$31
+[0-9a-f]+ <[^>]*> 4080c007 mtdvbm \$0
+[0-9a-f]+ <[^>]*> 409fc007 mtdvbm \$31
+[0-9a-f]+ <[^>]*> 4000c002 mfiab \$0
+[0-9a-f]+ <[^>]*> 401fc002 mfiab \$31
+[0-9a-f]+ <[^>]*> 4080c002 mtiab \$0
+[0-9a-f]+ <[^>]*> 409fc002 mtiab \$31
+[0-9a-f]+ <[^>]*> 4000c003 mfiabm \$0
+[0-9a-f]+ <[^>]*> 401fc003 mfiabm \$31
+[0-9a-f]+ <[^>]*> 4080c003 mtiabm \$0
+[0-9a-f]+ <[^>]*> 409fc003 mtiabm \$31
+[0-9a-f]+ <[^>]*> 70000010 mfhi1 \$0
+[0-9a-f]+ <[^>]*> 7000f810 mfhi1 \$31
+[0-9a-f]+ <[^>]*> 70000011 mthi1 \$0
+[0-9a-f]+ <[^>]*> 73e00011 mthi1 \$31
+[0-9a-f]+ <[^>]*> 70000012 mflo1 \$0
+[0-9a-f]+ <[^>]*> 7000f812 mflo1 \$31
+[0-9a-f]+ <[^>]*> 70000013 mtlo1 \$0
+[0-9a-f]+ <[^>]*> 73e00013 mtlo1 \$31
+[0-9a-f]+ <[^>]*> 00000028 mfsa \$0
+[0-9a-f]+ <[^>]*> 0000f828 mfsa \$31
+[0-9a-f]+ <[^>]*> 00000029 mtsa \$0
+[0-9a-f]+ <[^>]*> 03e00029 mtsa \$31
+[0-9a-f]+ <[^>]*> 0418ffff mtsab \$0,-1
+[0-9a-f]+ <[^>]*> 05188000 mtsab \$8,-32768
+[0-9a-f]+ <[^>]*> 05187fff mtsab \$8,32767
+[0-9a-f]+ <[^>]*> 07f80000 mtsab \$31,0
+[0-9a-f]+ <[^>]*> 0419ffff mtsah \$0,-1
+[0-9a-f]+ <[^>]*> 05198000 mtsah \$8,-32768
+[0-9a-f]+ <[^>]*> 05197fff mtsah \$8,32767
+[0-9a-f]+ <[^>]*> 07f90000 mtsah \$31,0
+[0-9a-f]+ <[^>]*> 001f000b movn \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 03e0f80b movn \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 001f000a movz \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 03e0f80a movz \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 4600f81d msub\.s \$f0,\$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f07dd msub\.s \$f31,\$f0,\$f31
+[0-9a-f]+ <[^>]*> 461f001f msuba\.s \$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f81f msuba\.s \$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f001a mula\.s \$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f81a mula\.s \$f31,\$f0
+[0-9a-f]+ <[^>]*> 701f0018 mult1 \$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f818 mult1 \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0018 mult1 \$0,\$31
+[0-9a-f]+ <[^>]*> 73e00018 mult1 \$31,\$0
+[0-9a-f]+ <[^>]*> 701f0019 multu1 \$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f819 multu1 \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0019 multu1 \$0,\$31
+[0-9a-f]+ <[^>]*> 73e00019 multu1 \$31,\$0
+[0-9a-f]+ <[^>]*> 701f06e8 qfsrv \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fee8 qfsrv \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 4600f816 rsqrt\.s \$f0,\$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f07d6 rsqrt\.s \$f31,\$f0,\$f31
+[0-9a-f]+ <[^>]*> 461f0019 suba\.s \$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f819 suba\.s \$f31,\$f0
+[0-9a-f]+ <[^>]*> 701f0168 pabsh \$0,\$31
+[0-9a-f]+ <[^>]*> 7000f968 pabsh \$31,\$0
+[0-9a-f]+ <[^>]*> 701f0068 pabsw \$0,\$31
+[0-9a-f]+ <[^>]*> 7000f868 pabsw \$31,\$0
+[0-9a-f]+ <[^>]*> 701f0208 paddb \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fa08 paddb \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0108 paddh \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f908 paddh \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0608 paddsb \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fe08 paddsb \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0508 paddsh \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fd08 paddsh \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0408 paddsw \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fc08 paddsw \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0628 paddub \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fe28 paddub \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0528 padduh \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fd28 padduh \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0428 padduw \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fc28 padduw \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0008 paddw \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f808 paddw \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0128 padsbh \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f928 padsbh \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0489 pand \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fc89 pand \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f02a8 pceqb \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0faa8 pceqb \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f01a8 pceqh \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f9a8 pceqh \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f00a8 pceqw \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fa88 pcgtb \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f00a8 pceqw \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f8a8 pceqw \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0288 pcgtb \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fa88 pcgtb \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0188 pcgth \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f988 pcgth \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0088 pcgtw \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f888 pcgtw \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f06e9 pcpyh \$0,\$31
+[0-9a-f]+ <[^>]*> 7000fee9 pcpyh \$31,\$0
+[0-9a-f]+ <[^>]*> 701f0389 pcpyld \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fb89 pcpyld \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f03a9 pcpyud \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fba9 pcpyud \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0749 pdivbw \$0,\$31
+[0-9a-f]+ <[^>]*> 73e00749 pdivbw \$31,\$0
+[0-9a-f]+ <[^>]*> 701f0369 pdivuw \$0,\$31
+[0-9a-f]+ <[^>]*> 73e00369 pdivuw \$31,\$0
+[0-9a-f]+ <[^>]*> 701f0349 pdivw \$0,\$31
+[0-9a-f]+ <[^>]*> 73e00349 pdivw \$31,\$0
+[0-9a-f]+ <[^>]*> 701f06a9 pexch \$0,\$31
+[0-9a-f]+ <[^>]*> 7000fea9 pexch \$31,\$0
+[0-9a-f]+ <[^>]*> 701f07a9 pexcw \$0,\$31
+[0-9a-f]+ <[^>]*> 7000ffa9 pexcw \$31,\$0
+[0-9a-f]+ <[^>]*> 701f0689 pexeh \$0,\$31
+[0-9a-f]+ <[^>]*> 7000fe89 pexeh \$31,\$0
+[0-9a-f]+ <[^>]*> 701f0789 pexew \$0,\$31
+[0-9a-f]+ <[^>]*> 7000ff89 pexew \$31,\$0
+[0-9a-f]+ <[^>]*> 701f0788 pext5 \$0,\$31
+[0-9a-f]+ <[^>]*> 7000ff88 pext5 \$31,\$0
+[0-9a-f]+ <[^>]*> 701f0688 pextlb \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fe88 pextlb \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0588 pextlh \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fd88 pextlh \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0488 pextlw \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fc88 pextlw \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f06a8 pextub \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fea8 pextub \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f05a8 pextuh \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fda8 pextuh \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f04a8 pextuw \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fca8 pextuw \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0449 phmadh \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fc49 phmadh \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0549 phmsbh \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fd49 phmsbh \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f02a9 pinteh \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0faa9 pinteh \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0289 pinth \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fa89 pinth \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 73e00004 plzcw \$0,\$31
+[0-9a-f]+ <[^>]*> 7000f804 plzcw \$31,\$0
+[0-9a-f]+ <[^>]*> 701f0409 pmaddh \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fc09 pmaddh \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0029 pmadduw \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f829 pmadduw \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0009 pmaddw \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f809 pmaddw \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f01c8 pmaxh \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f9c8 pmaxh \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f00c8 pmaxw \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f8c8 pmaxw \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 70000209 pmfhi \$0
+[0-9a-f]+ <[^>]*> 7000fa09 pmfhi \$31
+[0-9a-f]+ <[^>]*> 700000f0 pmfhl\.lh \$0
+[0-9a-f]+ <[^>]*> 7000f8f0 pmfhl\.lh \$31
+[0-9a-f]+ <[^>]*> 70000030 pmfhl\.lw \$0
+[0-9a-f]+ <[^>]*> 7000f830 pmfhl\.lw \$31
+[0-9a-f]+ <[^>]*> 70000130 pmfhl\.sh \$0
+[0-9a-f]+ <[^>]*> 7000f930 pmfhl\.sh \$31
+[0-9a-f]+ <[^>]*> 700000b0 pmfhl\.slw \$0
+[0-9a-f]+ <[^>]*> 7000f8b0 pmfhl\.slw \$31
+[0-9a-f]+ <[^>]*> 70000070 pmfhl\.uw \$0
+[0-9a-f]+ <[^>]*> 7000f870 pmfhl\.uw \$31
+[0-9a-f]+ <[^>]*> 70000249 pmflo \$0
+[0-9a-f]+ <[^>]*> 7000fa49 pmflo \$31
+[0-9a-f]+ <[^>]*> 701f01e8 pminh \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f9e8 pminh \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f00e8 pminw \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f8e8 pminw \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0509 pmsubh \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fd09 pmsubh \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0109 pmsubw \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f909 pmsubw \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 70000229 pmthi \$0
+[0-9a-f]+ <[^>]*> 73e00229 pmthi \$31
+[0-9a-f]+ <[^>]*> 70000031 pmthl\.lw \$0
+[0-9a-f]+ <[^>]*> 73e00031 pmthl\.lw \$31
+[0-9a-f]+ <[^>]*> 70000269 pmtlo \$0
+[0-9a-f]+ <[^>]*> 73e00269 pmtlo \$31
+[0-9a-f]+ <[^>]*> 701f0709 pmulth \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0ff09 pmulth \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0329 pmultuw \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fb29 pmultuw \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0309 pmultw \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fb09 pmultw \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0309 pmultw \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fb09 pmultw \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f04e9 pnor \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fce9 pnor \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f04a9 por \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fca9 por \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f07c8 ppac5 \$0,\$31
+[0-9a-f]+ <[^>]*> 7000ffc8 ppac5 \$31,\$0
+[0-9a-f]+ <[^>]*> 701f06c8 ppacb \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fec8 ppacb \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f05c8 ppach \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fdc8 ppach \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f04c8 ppacw \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fcc8 ppacw \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f06c9 prevh \$0,\$31
+[0-9a-f]+ <[^>]*> 7000fec9 prevh \$31,\$0
+[0-9a-f]+ <[^>]*> 701f07c9 prot3w \$0,\$31
+[0-9a-f]+ <[^>]*> 7000ffc9 prot3w \$31,\$0
+[0-9a-f]+ <[^>]*> 7000f834 psllh \$31,\$0,0x0
+[0-9a-f]+ <[^>]*> 701f07f4 psllh \$0,\$31,0x1f
+[0-9a-f]+ <[^>]*> 701f0089 psllvw \$0,\$31,\$0
+[0-9a-f]+ <[^>]*> 73e0f889 psllvw \$31,\$0,\$31
+[0-9a-f]+ <[^>]*> 7000f83c psllw \$31,\$0,0x0
+[0-9a-f]+ <[^>]*> 701f07fc psllw \$0,\$31,0x1f
+[0-9a-f]+ <[^>]*> 7000f837 psrah \$31,\$0,0x0
+[0-9a-f]+ <[^>]*> 701f07f7 psrah \$0,\$31,0x1f
+[0-9a-f]+ <[^>]*> 701f00e9 psravw \$0,\$31,\$0
+[0-9a-f]+ <[^>]*> 73e0f8e9 psravw \$31,\$0,\$31
+[0-9a-f]+ <[^>]*> 7000f83f psraw \$31,\$0,0x0
+[0-9a-f]+ <[^>]*> 701f07ff psraw \$0,\$31,0x1f
+[0-9a-f]+ <[^>]*> 7000f836 psrlh \$31,\$0,0x0
+[0-9a-f]+ <[^>]*> 701f07f6 psrlh \$0,\$31,0x1f
+[0-9a-f]+ <[^>]*> 701f00c9 psrlvw \$0,\$31,\$0
+[0-9a-f]+ <[^>]*> 73e0f8c9 psrlvw \$31,\$0,\$31
+[0-9a-f]+ <[^>]*> 7000f83e psrlw \$31,\$0,0x0
+[0-9a-f]+ <[^>]*> 701f07fe psrlw \$0,\$31,0x1f
+[0-9a-f]+ <[^>]*> 701f0248 psubb \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fa48 psubb \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0148 psubh \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f948 psubh \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0648 psubsb \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fe48 psubsb \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0548 psubsh \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fd48 psubsh \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0448 psubsw \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fc48 psubsw \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0668 psubub \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fe68 psubub \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0568 psubuh \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fd68 psubuh \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0468 psubuw \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fc68 psubuw \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0048 psubw \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f848 psubw \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f04c9 pxor \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fcc9 pxor \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 001f0018 mult \$0,\$31
+[0-9a-f]+ <[^>]*> 03e0f818 mult \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 001f0019 multu \$0,\$31
+[0-9a-f]+ <[^>]*> 03e0f819 multu \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 001f0019 multu \$0,\$31
+[0-9a-f]+ <[^>]*> 03e0f819 multu \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0000 madd \$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f800 madd \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0000 madd \$0,\$31
+[0-9a-f]+ <[^>]*> 73e00000 madd \$31,\$0
+[0-9a-f]+ <[^>]*> 701f0001 maddu \$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f801 maddu \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0001 maddu \$0,\$31
+[0-9a-f]+ <[^>]*> 73e00001 maddu \$31,\$0
+[0-9a-f]+ <[^>]*> 0000000f sync
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/r5900-full.s b/gas/testsuite/gas/mips/r5900-full.s
new file mode 100644
index 0000000..c0dc20a
--- /dev/null
+++ b/gas/testsuite/gas/mips/r5900-full.s
@@ -0,0 +1,421 @@
+ .text
+
+stuff:
+ .ent stuff
+ .set push
+ .set noreorder
+ .set noat
+
+ add $0, $0, $31
+ add $1, $10, $3
+ add $31, $31, $0
+
+ addi $31, $0, 0
+ addi $1, $10, 3
+ addi $0, $31, -1
+
+ addiu $31, $0, 0
+ addiu $1, $10, 3
+ addiu $31, $0, 0xFFFF
+
+ and $0, $0, $31
+ and $1, $10, $3
+ and $31, $31, $0
+
+ andi $31, $0, 0
+ andi $1, $10, 3
+ andi $0, $31, 0xFFFF
+
+ nop
+
+ # Test R5900 specific instructions:
+ adda.s $f0, $f31
+ adda.s $f31, $f0
+
+ # The c.lt.s instruction of R5900 has the same opcode as c.olt.s of MIPS I.
+ c.lt.s $f0, $f31
+ c.lt.s $f31, $f0
+
+ # The c.le.s instruction of R5900 has the same opcode as c.ole.s of MIPS I.
+ c.le.s $f0, $f31
+ c.le.s $f31, $f0
+
+ c.eq.s $f0, $f31
+ c.eq.s $f31, $f0
+
+ c.f.s $f0, $f31
+ c.f.s $f31, $f0
+
+ # The cvt.w.s instruction of the R5900 does the same as trunc.w.s in MIPS I.
+ # The cvt.w.s instruction of MIPS I doesn't exist in the R5900 CPU.
+ # For compatibilty the instruction trunc.w.s uses the opcode of cvt.w.s.
+ # cvt.w.s should not be used on R5900.
+ trunc.w.s $f0, $f31
+ trunc.w.s $f31, $f0
+
+ # Test ei/di, but not the R5900 has a bug. ei/di should not be used.
+ di
+ ei
+
+ # Like div but result is written to lo1 and hi1 registers (pipeline 1).
+ div1 $0, $1, $31
+ div1 $0, $31, $1
+ divu1 $0, $1, $31
+ divu1 $0, $31, $1
+
+ # 128 bit store instruction.
+ sq $0, 0($0)
+ sq $1, 0x7fff($1)
+ sq $8, -0x8000($8)
+ sq $31, -1($31)
+
+ # 128 bit load instruction.
+ lq $0, 0($0)
+ lq $1, 0x7fff($1)
+ lq $8, -0x8000($8)
+ lq $31, -1($31)
+
+ # Prefetch cache
+ pref 0, 0($0)
+ pref 1, 0x7fff($1)
+ pref 8, -0x8000($8)
+ pref 31, -1($31)
+
+ # Floating point multiply-ADD
+ madd.s $f0, $f31, $f0
+ madd.s $f31, $f0, $f31
+
+ # Like maddu, but pipeline 1
+ maddu1 $0, $31
+ maddu1 $31, $0
+ maddu1 $0, $0, $31
+ maddu1 $31, $31, $0
+
+ # Like madd, but pipeline 1
+ madd1 $0, $31
+ madd1 $31, $0
+ madd1 $0, $0, $31
+ madd1 $31, $31, $0
+
+ # Floating point multiply-ADD
+ madda.s $f0, $f31
+ madda.s $f31, $f0
+
+ # Floating point maximum
+ max.s $f0, $f31, $f0
+ max.s $f31, $f0, $f31
+
+ # Floating point minimum
+ min.s $f0, $f31, $f0
+ min.s $f31, $f0, $f31
+
+ # Preformance counter registers
+ mfpc $31, 0
+ mfpc $0, 1
+ mfps $0, 0
+ mfps $31, 0
+ mtpc $31, 0
+ mtpc $0, 1
+ mtps $0, 0
+ mtps $31, 0
+
+ # Brekpoint register
+ mfbpc $0
+ mfbpc $31
+ mtbpc $0
+ mtbpc $31
+ mfdab $0
+ mfdab $31
+ mtdab $0
+ mtdab $31
+ mfdabm $0
+ mfdabm $31
+ mtdabm $0
+ mtdabm $31
+ mfdvb $0
+ mfdvb $31
+ mtdvb $0
+ mtdvb $31
+ mfdvbm $0
+ mfdvbm $31
+ mtdvbm $0
+ mtdvbm $31
+ mfiab $0
+ mfiab $31
+ mtiab $0
+ mtiab $31
+ mfiabm $0
+ mfiabm $31
+ mtiabm $0
+ mtiabm $31
+
+ # Pipeline1
+ mfhi1 $0
+ mfhi1 $31
+ mthi1 $0
+ mthi1 $31
+ mflo1 $0
+ mflo1 $31
+ mtlo1 $0
+ mtlo1 $31
+
+ # Shift amount register
+ mfsa $0
+ mfsa $31
+ mtsa $0
+ mtsa $31
+ mtsab $0, -1
+ mtsab $8, 0x8000
+ mtsab $8, 0x7FFF
+ mtsab $31, 0
+ mtsah $0, -1
+ mtsah $8, 0x8000
+ mtsah $8, 0x7FFF
+ mtsah $31, 0
+
+ movn $0, $0, $31
+ movn $31, $31, $0
+ movz $0, $0, $31
+ movz $31, $31, $0
+
+ # Floating multiply and subtract
+ msub.s $f0, $f31, $f0
+ msub.s $f31, $f0, $f31
+
+ # Floating multiply and subtract from accumulator
+ msuba.s $f0, $f31
+ msuba.s $f31, $f0
+
+ # Floating point multiply to accumulator
+ mula.s $f0, $f31
+ mula.s $f31, $f0
+
+ # Like mult but pipeline 1
+ mult1 $0, $0, $31
+ mult1 $31, $31, $0
+ mult1 $0, $31
+ mult1 $31, $0
+
+ # Like multu but pipeline 1
+ multu1 $0, $0, $31
+ multu1 $31, $31, $0
+ multu1 $0, $31
+ multu1 $31, $0
+
+ # Quadword funnel shift right variable
+ qfsrv $0, $0, $31
+ qfsrv $31, $31, $0
+
+ # Floating point reciprocal squre root
+ rsqrt.s $f0, $f31, $f0
+ rsqrt.s $f31, $f0, $f31
+
+ # FLoating point subtract to accumulator
+ suba.s $f0, $f31
+ suba.s $f31, $f0
+
+ # Parallel instructions operating on 128 bit registers:
+ pabsh $0, $31
+ pabsh $31, $0
+ pabsw $0, $31
+ pabsw $31, $0
+ paddb $0, $0, $31
+ paddb $31, $31, $0
+ paddh $0, $0, $31
+ paddh $31, $31, $0
+ paddsb $0, $0, $31
+ paddsb $31, $31, $0
+ paddsh $0, $0, $31
+ paddsh $31, $31, $0
+ paddsw $0, $0, $31
+ paddsw $31, $31, $0
+ paddub $0, $0, $31
+ paddub $31, $31, $0
+ padduh $0, $0, $31
+ padduh $31, $31, $0
+ padduw $0, $0, $31
+ padduw $31, $31, $0
+ paddw $0, $0, $31
+ paddw $31, $31, $0
+ padsbh $0, $0, $31
+ padsbh $31, $31, $0
+ pand $0, $0, $31
+ pand $31, $31, $0
+ pceqb $0, $0, $31
+ pceqb $31, $31, $0
+ pceqh $0, $0, $31
+ pceqh $31, $31, $0
+ pceqw $0, $0, $31
+ pcgtb $31, $31, $0
+ pceqw $0, $0, $31
+ pceqw $31, $31, $0
+ pcgtb $0, $0, $31
+ pcgtb $31, $31, $0
+ pcgth $0, $0, $31
+ pcgth $31, $31, $0
+ pcgtw $0, $0, $31
+ pcgtw $31, $31, $0
+ pcpyh $0, $31
+ pcpyh $31, $0
+ pcpyld $0, $0, $31
+ pcpyld $31, $31, $0
+ pcpyud $0, $0, $31
+ pcpyud $31, $31, $0
+ pdivbw $0, $31
+ pdivbw $31, $0
+ pdivuw $0, $31
+ pdivuw $31, $0
+ pdivw $0, $31
+ pdivw $31, $0
+ pexch $0, $31
+ pexch $31, $0
+ pexcw $0, $31
+ pexcw $31, $0
+ pexeh $0, $31
+ pexeh $31, $0
+ pexew $0, $31
+ pexew $31, $0
+ pext5 $0, $31
+ pext5 $31, $0
+ pextlb $0, $0, $31
+ pextlb $31, $31, $0
+ pextlh $0, $0, $31
+ pextlh $31, $31, $0
+ pextlw $0, $0, $31
+ pextlw $31, $31, $0
+ pextub $0, $0, $31
+ pextub $31, $31, $0
+ pextuh $0, $0, $31
+ pextuh $31, $31, $0
+ pextuw $0, $0, $31
+ pextuw $31, $31, $0
+ phmadh $0, $0, $31
+ phmadh $31, $31, $0
+ phmsbh $0, $0, $31
+ phmsbh $31, $31, $0
+ pinteh $0, $0, $31
+ pinteh $31, $31, $0
+ pinth $0, $0, $31
+ pinth $31, $31, $0
+ plzcw $0, $31
+ plzcw $31, $0
+ pmaddh $0, $0, $31
+ pmaddh $31, $31, $0
+ pmadduw $0, $0, $31
+ pmadduw $31, $31, $0
+ pmaddw $0, $0, $31
+ pmaddw $31, $31, $0
+ pmaxh $0, $0, $31
+ pmaxh $31, $31, $0
+ pmaxw $0, $0, $31
+ pmaxw $31, $31, $0
+ pmfhi $0
+ pmfhi $31
+ pmfhl.lh $0
+ pmfhl.lh $31
+ pmfhl.lw $0
+ pmfhl.lw $31
+ pmfhl.sh $0
+ pmfhl.sh $31
+ pmfhl.slw $0
+ pmfhl.slw $31
+ pmfhl.uw $0
+ pmfhl.uw $31
+ pmflo $0
+ pmflo $31
+ pminh $0, $0, $31
+ pminh $31, $31, $0
+ pminw $0, $0, $31
+ pminw $31, $31, $0
+ pmsubh $0, $0, $31
+ pmsubh $31, $31, $0
+ pmsubw $0, $0, $31
+ pmsubw $31, $31, $0
+ pmthi $0
+ pmthi $31
+ pmthl.lw $0
+ pmthl.lw $31
+ pmtlo $0
+ pmtlo $31
+ pmulth $0, $0, $31
+ pmulth $31, $31, $0
+ pmultuw $0, $0, $31
+ pmultuw $31, $31, $0
+ pmultw $0, $0, $31
+ pmultw $31, $31, $0
+ pmultw $0, $0, $31
+ pmultw $31, $31, $0
+ pnor $0, $0, $31
+ pnor $31, $31, $0
+ por $0, $0, $31
+ por $31, $31, $0
+ ppac5 $0, $31
+ ppac5 $31, $0
+ ppacb $0, $0, $31
+ ppacb $31, $31, $0
+ ppach $0, $0, $31
+ ppach $31, $31, $0
+ ppacw $0, $0, $31
+ ppacw $31, $31, $0
+ prevh $0, $31
+ prevh $31, $0
+ prot3w $0, $31
+ prot3w $31, $0
+ psllh $31, $0, 0
+ psllh $0, $31, 31
+ psllvw $0, $31, $0
+ psllvw $31, $0, $31
+ psllw $31, $0, 0
+ psllw $0, $31, 31
+ psrah $31, $0, 0
+ psrah $0, $31, 31
+ psravw $0, $31, $0
+ psravw $31, $0, $31
+ psraw $31, $0, 0
+ psraw $0, $31, 31
+ psrlh $31, $0, 0
+ psrlh $0, $31, 31
+ psrlvw $0, $31, $0
+ psrlvw $31, $0, $31
+ psrlw $31, $0, 0
+ psrlw $0, $31, 31
+ psubb $0, $0, $31
+ psubb $31, $31, $0
+ psubh $0, $0, $31
+ psubh $31, $31, $0
+ psubsb $0, $0, $31
+ psubsb $31, $31, $0
+ psubsh $0, $0, $31
+ psubsh $31, $31, $0
+ psubsw $0, $0, $31
+ psubsw $31, $31, $0
+ psubub $0, $0, $31
+ psubub $31, $31, $0
+ psubuh $0, $0, $31
+ psubuh $31, $31, $0
+ psubuw $0, $0, $31
+ psubuw $31, $31, $0
+ psubw $0, $0, $31
+ psubw $31, $31, $0
+ pxor $0, $0, $31
+ pxor $31, $31, $0
+
+ # G1 instructions
+ mult $0, $0, $31
+ mult $31, $31, $0
+ multu $0, $0, $31
+ multu $31, $31, $0
+ mul $0, $0, $31
+ mul $31, $31, $0
+ madd $0, $0, $31
+ madd $31, $31, $0
+ madd $0, $31
+ madd $31, $0
+ maddu $0, $0, $31
+ maddu $31, $31, $0
+ maddu $0, $31
+ maddu $31, $0
+ sync
+
+ .space 8
+ .end stuff
diff --git a/gas/testsuite/gas/mips/r5900.d b/gas/testsuite/gas/mips/r5900.d
new file mode 100644
index 0000000..7ef9a8a
--- /dev/null
+++ b/gas/testsuite/gas/mips/r5900.d
@@ -0,0 +1,93 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric -mmips:5900
+#name: MIPS R5900
+#as: -march=r5900 -mtune=r5900
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 001f0020 add \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 01430820 add \$1,\$10,\$3
+[0-9a-f]+ <[^>]*> 03e0f820 add \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 201f0000 addi \$31,\$0,0
+[0-9a-f]+ <[^>]*> 21410003 addi \$1,\$10,3
+[0-9a-f]+ <[^>]*> 23e0ffff addi \$0,\$31,-1
+[0-9a-f]+ <[^>]*> 241f0000 li \$31,0
+[0-9a-f]+ <[^>]*> 25410003 addiu \$1,\$10,3
+[0-9a-f]+ <[^>]*> 241fffff li \$31,-1
+[0-9a-f]+ <[^>]*> 001f0024 and \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 01430824 and \$1,\$10,\$3
+[0-9a-f]+ <[^>]*> 03e0f824 and \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 301f0000 andi \$31,\$0,0x0
+[0-9a-f]+ <[^>]*> 31410003 andi \$1,\$10,0x3
+[0-9a-f]+ <[^>]*> 33e0ffff andi \$0,\$31,0xffff
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 461f0034 c\.lt\.s \$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f834 c\.lt\.s \$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f0036 c\.le\.s \$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f836 c\.le\.s \$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f0032 c\.eq\.s \$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f832 c\.eq\.s \$f31,\$f0
+[0-9a-f]+ <[^>]*> 461f0030 c\.f\.s \$f0,\$f31
+[0-9a-f]+ <[^>]*> 4600f830 c\.f\.s \$f31,\$f0
+[0-9a-f]+ <[^>]*> 4600f824 trunc\.w\.s \$f0,\$f31
+[0-9a-f]+ <[^>]*> 460007e4 trunc\.w\.s \$f31,\$f0
+[0-9a-f]+ <[^>]*> 7c000000 sq \$0,0\(\$0\)
+[0-9a-f]+ <[^>]*> 7c217fff sq \$1,32767\(\$1\)
+[0-9a-f]+ <[^>]*> 7d088000 sq \$8,-32768\(\$8\)
+[0-9a-f]+ <[^>]*> 7fffffff sq \$31,-1\(\$31\)
+[0-9a-f]+ <[^>]*> 78000000 lq \$0,0\(\$0\)
+[0-9a-f]+ <[^>]*> 78217fff lq \$1,32767\(\$1\)
+[0-9a-f]+ <[^>]*> 79088000 lq \$8,-32768\(\$8\)
+[0-9a-f]+ <[^>]*> 7bffffff lq \$31,-1\(\$31\)
+[0-9a-f]+ <[^>]*> cc000000 pref 0x0,0\(\$0\)
+[0-9a-f]+ <[^>]*> cc217fff pref 0x1,32767\(\$1\)
+[0-9a-f]+ <[^>]*> cd088000 pref 0x8,-32768\(\$8\)
+[0-9a-f]+ <[^>]*> cfffffff pref 0x1f,-1\(\$31\)
+[0-9a-f]+ <[^>]*> 401fc801 mfpc \$31,0
+[0-9a-f]+ <[^>]*> 4000c803 mfpc \$0,1
+[0-9a-f]+ <[^>]*> 4000c800 mfps \$0,0
+[0-9a-f]+ <[^>]*> 401fc800 mfps \$31,0
+[0-9a-f]+ <[^>]*> 409fc801 mtpc \$31,0
+[0-9a-f]+ <[^>]*> 4080c803 mtpc \$0,1
+[0-9a-f]+ <[^>]*> 4080c800 mtps \$0,0
+[0-9a-f]+ <[^>]*> 409fc800 mtps \$31,0
+[0-9a-f]+ <[^>]*> 70000010 mfhi1 \$0
+[0-9a-f]+ <[^>]*> 7000f810 mfhi1 \$31
+[0-9a-f]+ <[^>]*> 70000011 mthi1 \$0
+[0-9a-f]+ <[^>]*> 73e00011 mthi1 \$31
+[0-9a-f]+ <[^>]*> 70000012 mflo1 \$0
+[0-9a-f]+ <[^>]*> 7000f812 mflo1 \$31
+[0-9a-f]+ <[^>]*> 70000013 mtlo1 \$0
+[0-9a-f]+ <[^>]*> 73e00013 mtlo1 \$31
+[0-9a-f]+ <[^>]*> 001f000b movn \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 03e0f80b movn \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 001f000a movz \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 03e0f80a movz \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0389 pcpyld \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fb89 pcpyld \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0588 pextlh \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fd88 pextlh \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0488 pextlw \$0,\$0,\$31
+[0-9a-f]+ <[^>]*> 73e0fc88 pextlw \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 001f0018 mult \$0,\$31
+[0-9a-f]+ <[^>]*> 03e0f818 mult \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 001f0019 multu \$0,\$31
+[0-9a-f]+ <[^>]*> 03e0f819 multu \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 001f0019 multu \$0,\$31
+[0-9a-f]+ <[^>]*> 03e0f819 multu \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0000 madd \$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f800 madd \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0000 madd \$0,\$31
+[0-9a-f]+ <[^>]*> 73e00000 madd \$31,\$0
+[0-9a-f]+ <[^>]*> 701f0001 maddu \$0,\$31
+[0-9a-f]+ <[^>]*> 73e0f801 maddu \$31,\$31,\$0
+[0-9a-f]+ <[^>]*> 701f0001 maddu \$0,\$31
+[0-9a-f]+ <[^>]*> 73e00001 maddu \$31,\$0
+[0-9a-f]+ <[^>]*> 0000000f sync
+[0-9a-f]+ <[^>]*> 2403012c li \$3,300
+[0-9a-f]+ <[^>]*> 2063ffff addi \$3,\$3,-1
+[0-9a-f]+ <[^>]*> 2084ffff addi \$4,\$4,-1
+[0-9a-f]+ <[^>]*> 1460fffd bnez \$3,[0-9a-f]+ <short_loop1>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 24040003 li \$4,3
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/r5900.s b/gas/testsuite/gas/mips/r5900.s
new file mode 100644
index 0000000..022c4ab
--- /dev/null
+++ b/gas/testsuite/gas/mips/r5900.s
@@ -0,0 +1,135 @@
+ .text
+
+stuff:
+ .ent stuff
+ .set push
+ .set noreorder
+ .set noat
+
+ add $0, $0, $31
+ add $1, $10, $3
+ add $31, $31, $0
+
+ addi $31, $0, 0
+ addi $1, $10, 3
+ addi $0, $31, -1
+
+ addiu $31, $0, 0
+ addiu $1, $10, 3
+ addiu $31, $0, 0xFFFF
+
+ and $0, $0, $31
+ and $1, $10, $3
+ and $31, $31, $0
+
+ andi $31, $0, 0
+ andi $1, $10, 3
+ andi $0, $31, 0xFFFF
+
+ nop
+
+ # The c.lt.s instruction of R5900 has the same opcode as c.olt.s of MIPS I.
+ c.lt.s $f0, $f31
+ c.lt.s $f31, $f0
+
+ # The c.le.s instruction of R5900 has the same opcode as c.ole.s of MIPS I.
+ c.le.s $f0, $f31
+ c.le.s $f31, $f0
+
+ c.eq.s $f0, $f31
+ c.eq.s $f31, $f0
+
+ c.f.s $f0, $f31
+ c.f.s $f31, $f0
+
+ # The cvt.w.s instruction of the R5900 does the same as trunc.w.s in MIPS I.
+ # The cvt.w.s instruction of MIPS I doesn't exist in the R5900 CPU.
+ # For compatibilty the instruction trunc.w.s uses the opcode of cvt.w.s.
+ # cvt.w.s should not be used on R5900.
+ trunc.w.s $f0, $f31
+ trunc.w.s $f31, $f0
+
+ # 128 bit store instruction.
+ sq $0, 0($0)
+ sq $1, 0x7fff($1)
+ sq $8, -0x8000($8)
+ sq $31, -1($31)
+
+ # 128 bit load instruction.
+ lq $0, 0($0)
+ lq $1, 0x7fff($1)
+ lq $8, -0x8000($8)
+ lq $31, -1($31)
+
+ # Prefetch cache
+ pref 0, 0($0)
+ pref 1, 0x7fff($1)
+ pref 8, -0x8000($8)
+ pref 31, -1($31)
+
+ # Preformance counter registers
+ mfpc $31, 0
+ mfpc $0, 1
+ mfps $0, 0
+ mfps $31, 0
+ mtpc $31, 0
+ mtpc $0, 1
+ mtps $0, 0
+ mtps $31, 0
+
+ # Pipeline1
+ mfhi1 $0
+ mfhi1 $31
+ mthi1 $0
+ mthi1 $31
+ mflo1 $0
+ mflo1 $31
+ mtlo1 $0
+ mtlo1 $31
+
+ movn $0, $0, $31
+ movn $31, $31, $0
+ movz $0, $0, $31
+ movz $31, $31, $0
+
+ # Parallel instructions operating on 128 bit registers:
+ pcpyld $0, $0, $31
+ pcpyld $31, $31, $0
+ pextlh $0, $0, $31
+ pextlh $31, $31, $0
+ pextlw $0, $0, $31
+ pextlw $31, $31, $0
+
+ # G1 instructions
+ mult $0, $0, $31
+ mult $31, $31, $0
+ multu $0, $0, $31
+ multu $31, $31, $0
+ mul $0, $0, $31
+ mul $31, $31, $0
+ madd $0, $0, $31
+ madd $31, $31, $0
+ madd $0, $31
+ madd $31, $0
+ maddu $0, $0, $31
+ maddu $31, $31, $0
+ maddu $0, $31
+ maddu $31, $0
+ sync
+
+ .set pop
+ .set push
+ .set reorder
+ # Short loop fix.
+ li $3, 300
+short_loop1:
+ addi $3, -1
+ addi $4, -1
+ # NOP should be inserted in branch delay.
+ bne $3, $0, short_loop1
+
+ li $4, 3
+ .set pop
+
+ .space 8
+ .end stuff
generated by cgit v1.1 at 2024-12-15 21:06:11 +0000