diff options
Diffstat (limited to 'gas')
75 files changed, 2432 insertions, 3109 deletions
diff --git a/gas/config/tc-bpf.c b/gas/config/tc-bpf.c index 3b86f9c..7a54fac 100644 --- a/gas/config/tc-bpf.c +++ b/gas/config/tc-bpf.c @@ -22,42 +22,42 @@ #include "as.h" #include "subsegs.h" #include "symcat.h" -#include "opcodes/bpf-desc.h" -#include "opcodes/bpf-opc.h" -#include "cgen.h" +#include "opcode/bpf.h" #include "elf/common.h" #include "elf/bpf.h" #include "dwarf2dbg.h" +#include "libiberty.h" #include <ctype.h> +/* Data structure representing a parsed BPF instruction. */ + +struct bpf_insn +{ + int size; /* Instruction size in bytes. */ + bpf_insn_word opcode; + uint8_t dst; + uint8_t src; + expressionS offset16; + expressionS imm32; + expressionS imm64; + expressionS disp16; + expressionS disp32; + + unsigned int has_dst : 1; + unsigned int has_src : 1; + unsigned int has_offset16 : 1; + unsigned int has_disp16 : 1; + unsigned int has_disp32 : 1; + unsigned int has_imm32 : 1; + unsigned int has_imm64 : 1; +}; + const char comment_chars[] = ";"; const char line_comment_chars[] = "#"; const char line_separator_chars[] = "`"; const char EXP_CHARS[] = "eE"; const char FLT_CHARS[] = "fFdD"; -static const char *invalid_expression; -static char pseudoc_lex[256]; -static const char symbol_chars[] = -"_ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789"; - -static const char arithm_op[] = "+-/<>%&|^"; - -static void init_pseudoc_lex (void); - -#define LEX_IS_SYMBOL_COMPONENT 1 -#define LEX_IS_WHITESPACE 2 -#define LEX_IS_NEWLINE 3 -#define LEX_IS_ARITHM_OP 4 -#define LEX_IS_STAR 6 -#define LEX_IS_CLSE_BR 7 -#define LEX_IS_OPEN_BR 8 -#define LEX_IS_EQUAL 9 -#define LEX_IS_EXCLA 10 - -#define ST_EOI 100 -#define MAX_TOKEN_SZ 100 - /* Like s_lcomm_internal in gas/read.c but the alignment string is allowed to be optional. */ @@ -110,18 +110,15 @@ const pseudo_typeS md_pseudo_table[] = -/* ISA handling. */ -static CGEN_BITSET *bpf_isa; - - - /* Command-line options processing. */ enum options { OPTION_LITTLE_ENDIAN = OPTION_MD_BASE, OPTION_BIG_ENDIAN, - OPTION_XBPF + OPTION_XBPF, + OPTION_DIALECT, + OPTION_ISA_SPEC, }; struct option md_longopts[] = @@ -129,6 +126,8 @@ struct option md_longopts[] = { "EL", no_argument, NULL, OPTION_LITTLE_ENDIAN }, { "EB", no_argument, NULL, OPTION_BIG_ENDIAN }, { "mxbpf", no_argument, NULL, OPTION_XBPF }, + { "mdialect", required_argument, NULL, OPTION_DIALECT}, + { "misa-spec", required_argument, NULL, OPTION_ISA_SPEC}, { NULL, no_argument, NULL, 0 }, }; @@ -136,18 +135,34 @@ size_t md_longopts_size = sizeof (md_longopts); const char * md_shortopts = ""; -extern int target_big_endian; +/* BPF supports little-endian and big-endian variants. The following + global records what endianness to use. It can be configured using + command-line options. It defaults to the host endianness + initialized in md_begin. */ -/* Whether target_big_endian has been set while parsing command-line - arguments. */ static int set_target_endian = 0; +extern int target_big_endian; + +/* The ISA specification can be one of BPF_V1, BPF_V2, BPF_V3, BPF_V4 + or BPF_XPBF. The ISA spec to use can be configured using + command-line options. It defaults to the latest BPF spec. */ + +static int isa_spec = BPF_V4; -static int target_xbpf = 0; +/* The assembler supports two different dialects: "normal" syntax and + "pseudoc" syntax. The dialect to use can be configured using + command-line options. */ -static int set_xbpf = 0; +enum target_asm_dialect +{ + DIALECT_NORMAL, + DIALECT_PSEUDOC +}; + +static int asm_dialect = DIALECT_NORMAL; int -md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED) +md_parse_option (int c, const char * arg) { switch (c) { @@ -156,12 +171,36 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED) target_big_endian = 1; break; case OPTION_LITTLE_ENDIAN: - set_target_endian = 1; + set_target_endian = 0; target_big_endian = 0; break; + case OPTION_DIALECT: + if (strcmp (arg, "normal") == 0) + asm_dialect = DIALECT_NORMAL; + else if (strcmp (arg, "pseudoc") == 0) + asm_dialect = DIALECT_PSEUDOC; + else + as_fatal (_("-mdialect=%s is not valid. Expected normal or pseudoc"), + arg); + break; + case OPTION_ISA_SPEC: + if (strcmp (arg, "v1") == 0) + isa_spec = BPF_V1; + else if (strcmp (arg, "v2") == 0) + isa_spec = BPF_V2; + else if (strcmp (arg, "v3") == 0) + isa_spec = BPF_V3; + else if (strcmp (arg, "v4") == 0) + isa_spec = BPF_V4; + else if (strcmp (arg, "xbpf") == 0) + isa_spec = BPF_XBPF; + else + as_fatal (_("-misa-spec=%s is not valid. Expected v1, v2, v3, v4 o xbpf"), + arg); + break; case OPTION_XBPF: - set_xbpf = 1; - target_xbpf = 1; + /* This is an alias for -misa-spec=xbpf. */ + isa_spec = BPF_XBPF; break; default: return 0; @@ -175,43 +214,22 @@ md_show_usage (FILE * stream) { fprintf (stream, _("\nBPF options:\n")); fprintf (stream, _("\ - --EL generate code for a little endian machine\n\ - --EB generate code for a big endian machine\n\ - -mxbpf generate xBPF instructions\n")); +BPF options:\n\ + -EL generate code for a little endian machine\n\ + -EB generate code for a big endian machine\n\ + -mdialect=DIALECT set the assembly dialect (normal, pseudoc)\n\ + -misa-spec set the BPF ISA spec (v1, v2, v3, v4, xbpf)\n\ + -mxbpf alias for -misa-spec=xbpf\n")); } - -static void -init_pseudoc_lex (void) -{ - const char *p; - - for (p = symbol_chars; *p; ++p) - pseudoc_lex[(unsigned char) *p] = LEX_IS_SYMBOL_COMPONENT; - - pseudoc_lex[' '] = LEX_IS_WHITESPACE; - pseudoc_lex['\t'] = LEX_IS_WHITESPACE; - pseudoc_lex['\r'] = LEX_IS_WHITESPACE; - pseudoc_lex['\n'] = LEX_IS_NEWLINE; - pseudoc_lex['*'] = LEX_IS_STAR; - pseudoc_lex[')'] = LEX_IS_CLSE_BR; - pseudoc_lex['('] = LEX_IS_OPEN_BR; - pseudoc_lex[']'] = LEX_IS_CLSE_BR; - pseudoc_lex['['] = LEX_IS_OPEN_BR; - - for (p = arithm_op; *p; ++p) - pseudoc_lex[(unsigned char) *p] = LEX_IS_ARITHM_OP; - - pseudoc_lex['='] = LEX_IS_EQUAL; - pseudoc_lex['!'] = LEX_IS_EXCLA; -} +/* This function is called once, at assembler startup time. This + should set up all the tables, etc that the MD part of the assembler + needs. */ void md_begin (void) { - /* Initialize the `cgen' interface. */ - /* If not specified in the command line, use the host endianness. */ if (!set_target_endian) @@ -223,50 +241,15 @@ md_begin (void) #endif } - /* If not specified in the command line, use eBPF rather - than xBPF. */ - if (!set_xbpf) - target_xbpf = 0; - - /* Set the ISA, which depends on the target endianness. */ - bpf_isa = cgen_bitset_create (ISA_MAX); - if (target_big_endian) - { - if (target_xbpf) - cgen_bitset_set (bpf_isa, ISA_XBPFBE); - else - cgen_bitset_set (bpf_isa, ISA_EBPFBE); - } - else - { - if (target_xbpf) - cgen_bitset_set (bpf_isa, ISA_XBPFLE); - else - cgen_bitset_set (bpf_isa, ISA_EBPFLE); - } - /* Ensure that lines can begin with '*' in BPF store pseudoc instruction. */ lex_type['*'] |= LEX_BEGIN_NAME; - /* Set the machine number and endian. */ - gas_cgen_cpu_desc = bpf_cgen_cpu_open (CGEN_CPU_OPEN_ENDIAN, - target_big_endian ? - CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE, - CGEN_CPU_OPEN_INSN_ENDIAN, - CGEN_ENDIAN_LITTLE, - CGEN_CPU_OPEN_ISAS, - bpf_isa, - CGEN_CPU_OPEN_END); - bpf_cgen_init_asm (gas_cgen_cpu_desc); - - /* This is a callback from cgen to gas to parse operands. */ - cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); - /* Set the machine type. */ bfd_default_set_arch_mach (stdoutput, bfd_arch_bpf, bfd_mach_bpf); - init_pseudoc_lex(); } +/* Round up a section size to the appropriate boundary. */ + valueT md_section_align (segT segment, valueT size) { @@ -310,33 +293,48 @@ md_number_to_chars (char * buf, valueT val, int n) } arelent * -tc_gen_reloc (asection *sec, fixS *fix) +tc_gen_reloc (asection *sec ATTRIBUTE_UNUSED, fixS *fixP) { - return gas_cgen_tc_gen_reloc (sec, fix); -} + bfd_reloc_code_real_type r_type = fixP->fx_r_type; + arelent *reloc; -/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. This - is called when the operand is an expression that couldn't be fully - resolved. Returns BFD_RELOC_NONE if no reloc type can be found. - *FIXP may be modified if desired. */ + reloc = XNEW (arelent); -bfd_reloc_code_real_type -md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED, - const CGEN_OPERAND *operand, - fixS *fixP) -{ - switch (operand->type) + if (fixP->fx_pcrel) + { + r_type = (r_type == BFD_RELOC_8 ? BFD_RELOC_8_PCREL + : r_type == BFD_RELOC_16 ? BFD_RELOC_16_PCREL + : r_type == BFD_RELOC_24 ? BFD_RELOC_24_PCREL + : r_type == BFD_RELOC_32 ? BFD_RELOC_32_PCREL + : r_type == BFD_RELOC_64 ? BFD_RELOC_64_PCREL + : r_type); + } + + reloc->howto = bfd_reloc_type_lookup (stdoutput, r_type); + + if (reloc->howto == (reloc_howto_type *) NULL) { - case BPF_OPERAND_IMM64: - return BFD_RELOC_BPF_64; - case BPF_OPERAND_DISP32: - fixP->fx_pcrel = 1; - return BFD_RELOC_BPF_DISP32; - default: - break; + as_bad_where (fixP->fx_file, fixP->fx_line, + _("relocation is not supported")); + return NULL; } - return BFD_RELOC_NONE; + + //XXX gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative); + + reloc->sym_ptr_ptr = XNEW (asymbol *); + *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); + + /* Use fx_offset for these cases. */ + if (fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY + || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT) + reloc->addend = fixP->fx_offset; + else + reloc->addend = fixP->fx_addnumber; + + reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; + return reloc; } + /* *FRAGP has been relaxed to its final size, and now needs to have the bytes inside it modified to conform to the new size. @@ -362,1556 +360,821 @@ md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED, } +/* Apply a fixS (fixup of an instruction or data that we didn't have + enough info to complete immediately) to the data in a frag. */ + void -md_apply_fix (fixS *fixP, valueT *valP, segT seg) +md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) { - /* Some fixups for instructions require special attention. This is - handled in the code block below. */ - if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) + char *where = fixP->fx_frag->fr_literal + fixP->fx_where; + + switch (fixP->fx_r_type) { - int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; - const CGEN_OPERAND *operand = cgen_operand_lookup_by_num (gas_cgen_cpu_desc, - opindex); - char *where; + case BFD_RELOC_BPF_DISP16: + /* Convert from bytes to number of 64-bit words to the target, + minus one. */ + *valP = (((long) (*valP)) - 8) / 8; + break; + case BFD_RELOC_BPF_DISP32: + /* eBPF supports two kind of CALL instructions: the so called + pseudo calls ("bpf to bpf") and external calls ("bpf to + kernel"). + + Both kind of calls use the same instruction (CALL). However, + external calls are constructed by passing a constant argument + to the instruction, whereas pseudo calls result from + expressions involving symbols. In practice, instructions + requiring a fixup are interpreted as pseudo-calls. If we are + executing this code, this is a pseudo call. + + The kernel expects for pseudo-calls to be annotated by having + BPF_PSEUDO_CALL in the SRC field of the instruction. But + beware the infamous nibble-swapping of eBPF and take + endianness into account here. + + Note that the CALL instruction has only one operand, so + this code is executed only once per instruction. */ + md_number_to_chars (where + 1, target_big_endian ? 0x01 : 0x10, 1); + + /* Convert from bytes to number of 64-bit words to the target, + minus one. */ + *valP = (((long) (*valP)) - 8) / 8; + break; + case BFD_RELOC_16_PCREL: + /* Convert from bytes to number of 64-bit words to the target, + minus one. */ + *valP = (((long) (*valP)) - 8) / 8; + break; + default: + break; + } - switch (operand->type) - { - case BPF_OPERAND_DISP32: - /* eBPF supports two kind of CALL instructions: the so - called pseudo calls ("bpf to bpf") and external calls - ("bpf to kernel"). - - Both kind of calls use the same instruction (CALL). - However, external calls are constructed by passing a - constant argument to the instruction, whereas pseudo - calls result from expressions involving symbols. In - practice, instructions requiring a fixup are interpreted - as pseudo-calls. If we are executing this code, this is - a pseudo call. - - The kernel expects for pseudo-calls to be annotated by - having BPF_PSEUDO_CALL in the SRC field of the - instruction. But beware the infamous nibble-swapping of - eBPF and take endianness into account here. - - Note that the CALL instruction has only one operand, so - this code is executed only once per instruction. */ - where = fixP->fx_frag->fr_literal + fixP->fx_where + 1; - where[0] = target_big_endian ? 0x01 : 0x10; - /* Fallthrough. */ - case BPF_OPERAND_DISP16: - /* The PC-relative displacement fields in jump instructions - shouldn't be in bytes. Instead, they hold the number of - 64-bit words to the target, _minus one_. */ - *valP = (((long) (*valP)) - 8) / 8; + if (fixP->fx_addsy == (symbolS *) NULL) + fixP->fx_done = 1; + + if (fixP->fx_done) + { + /* We're finished with this fixup. Install it because + bfd_install_relocation won't be called to do it. */ + switch (fixP->fx_r_type) + { + case BFD_RELOC_8: + md_number_to_chars (where, *valP, 1); + break; + case BFD_RELOC_16: + md_number_to_chars (where, *valP, 2); + break; + case BFD_RELOC_32: + md_number_to_chars (where, *valP, 4); + break; + case BFD_RELOC_64: + md_number_to_chars (where, *valP, 8); + break; + case BFD_RELOC_BPF_DISP16: + md_number_to_chars (where + 2, (uint16_t) *valP, 2); break; - default: + case BFD_RELOC_BPF_DISP32: + md_number_to_chars (where + 4, (uint32_t) *valP, 4); break; - } + case BFD_RELOC_16_PCREL: + md_number_to_chars (where + 2, (uint32_t) *valP, 2); + break; + default: + as_bad_where (fixP->fx_file, fixP->fx_line, + _("internal error: can't install fix for reloc type %d (`%s')"), + fixP->fx_r_type, bfd_get_reloc_code_name (fixP->fx_r_type)); + break; + } } - /* And now invoke CGEN's handler, which will eventually install - *valP into the corresponding operand. */ - gas_cgen_md_apply_fix (fixP, valP, seg); + /* Tuck `value' away for use by tc_gen_reloc. + See the comment describing fx_addnumber in write.h. + This field is misnamed (or misused :-). */ + fixP->fx_addnumber = *valP; } -/* - The BPF pseudo grammar: - - instruction : bpf_alu_insn - | bpf_alu32_insn - | bpf_jump_insn - | bpf_load_store_insn - | bpf_load_store32_insn - | bpf_non_generic_load - | bpf_endianness_conv_insn - | bpf_64_imm_load_insn - | bpf_atomic_insn - ; - - bpf_alu_insn : BPF_REG bpf_alu_operator register_or_imm32 - ; - - bpf_alu32_insn : BPF_REG32 bpf_alu_operator register32_or_imm32 - ; - - bpf_jump_insn : BPF_JA offset - | IF BPF_REG bpf_jump_operator register_or_imm32 BPF_JA offset - | IF BPF_REG32 bpf_jump_operator register_or_imm32 BPF_JA offset - | BPF_CALL offset - | BPF_EXIT - ; - - bpf_load_store_insn : BPF_REG CHR_EQUAL bpf_size_cast BPF_CHR_OPEN_BR \ - register_and_offset BPF_CHR_CLSE_BR - | bpf_size_cast register_and_offset CHR_EQUAL BPF_REG - ; - - bpf_load_store32_insn : BPF_REG CHR_EQUAL bpf_size_cast BPF_CHR_OPEN_BR \ - register32_and_offset BPF_CHR_CLSE_BR - | bpf_size_cast register_and_offset CHR_EQUAL BPF_REG32 - ; - - bpf_non_generic_load : BPF_REG_R0 CHR_EQUAL bpf_size_cast BPF_LD BPF_CHR_OPEN_BR \ - imm32 BPF_CHR_CLSE_BR - ; - - bpf_endianness_conv_insn : BPF_REG_N bpf_endianness_mnem BPF_REG_N - ; - - bpf_64_imm_load_insn : BPF_REG imm64 BPF_LL - ; - - bpf_atomic_insn : BPF_LOCK bpf_size_cast_32_64 register_and_offset BPF_ADD BPF_REG - - register_and_offset : BPF_CHR_OPEN_BR BPF_REG offset BPF_CHR_CLSE_BR - ; - - register32_and_offset : BPF_CHR_OPEN_BR BPF_REG32 offset BPF_CHR_CLSE_BR - ; - - bpf_size_cast : CHR_START BPF_CHR_OPEN_BR bpf_size CHR_START BPF_CHR_CLSE_BR - ; - - bpf_size_cast_32_64 : CHR_START BPF_CHR_OPEN_BR bpf_size_cast_32_64 CHR_STAR BPF_CHR_CLSE_BR - ; - - bpf_size_32_64 : BPF_CAST_U32 - | BPF_CAST_U64 - ; - - bpf_size : BPF_CAST_U8 - | BPF_CAST_U16 - | BPF_CAST_U32 - | BPF_CAST_U64 - ; - - bpf_jump_operator : BPF_JEQ - | BPF_JGT - | BPF_JGE - | BPF_JNE - | BPF_JSGT - | BPF_JSGE - | BPF_JLT - | BPF_JLE - | BPF_JSLT - | BPF_JSLE - ; - - bpf_alu_operator : BPF_ADD - | BPF_SUB - | BPF_MUL - | BPF_DIV - | BPF_OR - | BPF_AND - | BPF_LSH - | BPF_RSH - | BPF_NEG - | BPF_MOD - | BPF_XOR - | BPF_ARSH - | CHR_EQUAL - ; - - bpf_endianness_mnem : BPF_LE16 - | BPF_LE32 - | BPF_LE64 - | BPF_BE16 - | BPF_BE32 - | BPF_BE64 - ; - - offset : BPF_EXPR - | BPF_SYMBOL - ; - - register_or_imm32 : BPF_REG - | expression - ; - - register32_or_imm32 : BPF_REG32 - | expression - ; - - imm32 : BPF_EXPR - | BPF_SYMBOL - ; - - imm64 : BPF_EXPR - | BPF_SYMBOL - ; - - register_or_expression : BPF_EXPR - | BPF_REG - ; - - BPF_EXPR : GAS_EXPR - -*/ - -enum bpf_token_type - { - /* Keep grouped to quickly access. */ - BPF_ADD, - BPF_SUB, - BPF_MUL, - BPF_DIV, - BPF_OR, - BPF_AND, - BPF_LSH, - BPF_RSH, - BPF_MOD, - BPF_XOR, - BPF_MOV, - BPF_ARSH, - BPF_NEG, - - BPF_REG, - - BPF_IF, - BPF_GOTO, - - /* Keep grouped to quickly access. */ - BPF_JEQ, - BPF_JGT, - BPF_JGE, - BPF_JLT, - BPF_JLE, - BPF_JSET, - BPF_JNE, - BPF_JSGT, - BPF_JSGE, - BPF_JSLT, - BPF_JSLE, - - BPF_SYMBOL, - BPF_CHR_CLSE_BR, - BPF_CHR_OPEN_BR, - - /* Keep grouped to quickly access. */ - BPF_CAST_U8, - BPF_CAST_U16, - BPF_CAST_U32, - BPF_CAST_U64, - - /* Keep grouped to quickly access. */ - BPF_LE16, - BPF_LE32, - BPF_LE64, - BPF_BE16, - BPF_BE32, - BPF_BE64, - - BPF_LOCK, - - BPF_IND_CALL, - BPF_LD, - BPF_LL, - BPF_EXPR, - BPF_UNKNOWN, - }; - -static int -valid_expr (const char *e, const char **end_expr) -{ - invalid_expression = NULL; - char *hold = input_line_pointer; - expressionS exp; - - input_line_pointer = (char *) e; - deferred_expression (&exp); - *end_expr = input_line_pointer; - input_line_pointer = hold; +/* Parse an operand expression. Returns the first character that is + not part of the expression, or NULL in case of parse error. - return invalid_expression == NULL; -} + See md_operand below to see how exp_parse_failed is used. */ -static char * -build_bpf_non_generic_load (char *src, enum bpf_token_type cast, - const char *imm32) -{ - char *bpf_insn; - static const char *cast_rw[] = {"b", "h", "w", "dw"}; - - bpf_insn = xasprintf ("%s%s%s %s%s%s%s", - "ld", - src ? "ind" : "abs", - cast_rw[cast - BPF_CAST_U8], - src ? "%" : "", - src ? src : "", - src ? "," : "", - imm32); - return bpf_insn; -} +static int exp_parse_failed = 0; static char * -build_bpf_atomic_insn (char *dst, char *src, - enum bpf_token_type atomic_insn, - enum bpf_token_type cast, - const char *offset) +parse_expression (char *s, expressionS *exp) { - char *bpf_insn; - static const char *cast_rw[] = {"w", "dw"}; - static const char *mnem[] = {"xadd"}; - - bpf_insn = xasprintf ("%s%s [%%%s%s%s],%%%s", mnem[atomic_insn - BPF_ADD], - cast_rw[cast - BPF_CAST_U32], dst, - *offset != '+' ? "+" : "", - offset, src); - return bpf_insn; -} + char *saved_input_line_pointer = input_line_pointer; + char *saved_s = s; -static char * -build_bpf_jmp_insn (char *dst, char *src, - char *imm32, enum bpf_token_type op, - const char *sym, const char *offset) -{ - char *bpf_insn; - static const char *mnem[] = - { - "jeq", "jgt", "jge", "jlt", - "jle", "jset", "jne", "jsgt", - "jsge", "jslt", "jsle" - }; - - const char *in32 = (*dst == 'w' ? "32" : ""); - - *dst = 'r'; - if (src) - *src = 'r'; - - bpf_insn = xasprintf ("%s%s %%%s,%s%s,%s", - mnem[op - BPF_JEQ], in32, dst, - src ? "%" : "", - src ? src : imm32, - offset ? offset : sym); - return bpf_insn; -} + exp_parse_failed = 0; + input_line_pointer = s; + expression (exp); + s = input_line_pointer; + input_line_pointer = saved_input_line_pointer; -static char * -build_bpf_arithm_insn (char *dst, char *src, - int load64, const char *imm32, - enum bpf_token_type type) -{ - char *bpf_insn; - static const char *mnem[] = - { - "add", "sub", "mul", "div", - "or", "and", "lsh", "rsh", - "mod", "xor", "mov", "arsh", - "neg", - }; - const char *in32 = (*dst == 'w' ? "32" : ""); - - *dst = 'r'; - if (src) - *src = 'r'; - - if (type == BPF_NEG) - bpf_insn = xasprintf ("%s%s %%%s", mnem[type - BPF_ADD], in32, dst); - else if (load64) - bpf_insn = xasprintf ("%s %%%s,%s", "lddw", dst, imm32); - else - bpf_insn = xasprintf ("%s%s %%%s,%s%s", mnem[type - BPF_ADD], - in32, dst, - src ? "%" : "", - src ? src: imm32); - return bpf_insn; -} + switch (exp->X_op == O_absent || exp_parse_failed) + return NULL; -static char * -build_bpf_endianness (char *dst, enum bpf_token_type endianness) -{ - char *bpf_insn; - static const char *size[] = {"16", "32", "64"}; - int be = 1; - - if (endianness == BPF_LE16 - || endianness == BPF_LE32 - || endianness == BPF_LE64) - be = 0; - else - gas_assert (endianness == BPF_BE16 || endianness == BPF_BE32 || endianness == BPF_BE64); + /* The expression parser may consume trailing whitespaces. We have + to undo that since the instruction templates may be expecting + these whitespaces. */ + { + char *p; + for (p = s - 1; p >= saved_s && *p == ' '; --p) + --s; + } - bpf_insn = xasprintf ("%s %%%s,%s", be ? "endbe" : "endle", - dst, be ? size[endianness - BPF_BE16] : size[endianness - BPF_LE16]); - return bpf_insn; + return s; } -static char * -build_bpf_load_store_insn (char *dst, char *src, - enum bpf_token_type cast, - const char *offset, int isload) -{ - char *bpf_insn; - static const char *cast_rw[] = {"b", "h", "w", "dw"}; - - *dst = *src = 'r'; - if (isload) - bpf_insn = xasprintf ("%s%s %%%s,[%%%s%s%s]", "ldx", - cast_rw[cast - BPF_CAST_U8], dst, src, - *offset != '+' ? "+" : "", - offset); - else - bpf_insn = xasprintf ("%s%s [%%%s%s%s],%%%s", "stx", - cast_rw[cast - BPF_CAST_U8], dst, - *offset != '+' ? "+" : "", - offset, src); - return bpf_insn; -} +/* Parse a BPF register name and return the corresponding register + number. Return NULL in case of parse error, or a pointer to the + first character in S that is not part of the register name. */ -static int -look_for_reserved_word (const char *token, enum bpf_token_type *type) +static char * +parse_bpf_register (char *s, char rw, uint8_t *regno) { - int i; - static struct - { - const char *name; - enum bpf_token_type type; - } reserved_words[] = + if (asm_dialect == DIALECT_NORMAL) { - { - .name = "if", - .type = BPF_IF - }, - { - .name = "goto", - .type = BPF_GOTO - }, - { - .name = "le16", - .type = BPF_LE16 - }, - { - .name = "le32", - .type = BPF_LE32 - }, - { - .name = "le64", - .type = BPF_LE64 - }, - { - .name = "be16", - .type = BPF_BE16 - }, - { - .name = "be32", - .type = BPF_BE32 - }, - { - .name = "be64", - .type = BPF_BE64 - }, - { - .name = "lock", - .type = BPF_LOCK - }, - { - .name = "callx", - .type = BPF_IND_CALL - }, - { - .name = "skb", - .type = BPF_LD - }, - { - .name = "ll", - .type = BPF_LL - }, - { - .name = NULL, - } - }; + rw = 'r'; + if (*s != '%') + return NULL; + s += 1; - for (i = 0; reserved_words[i].name; ++i) - if (*reserved_words[i].name == *token - && !strcmp (reserved_words[i].name, token)) - { - *type = reserved_words[i].type; - return 1; - } + if (*s == 'f' && *(s + 1) == 'p') + { + *regno = 10; + s += 2; + return s; + } + } - return 0; -} + if (*s != rw) + return NULL; + s += 1; -static int -is_register (const char *token, int len) -{ - if (token[0] == 'r' || token[0] == 'w') - if ((len == 2 && isdigit (token[1])) - || (len == 3 && token[1] == '1' && token[2] == '0')) - return 1; + if (*s == '1') + { + if (*(s + 1) == '0') + { + *regno = 10; + s += 2; + } + else + { + *regno = 1; + s += 1; + } + } + else if (*s >= '0' && *s <= '9') + { + *regno = *s - '0'; + s += 1; + } - return 0; + return s; } -static enum bpf_token_type -is_cast (const char *token) -{ - static const char *cast_rw[] = {"u8", "u16", "u32", "u64"}; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE (cast_rw); ++i) - if (!strcmp (token, cast_rw[i])) - return BPF_CAST_U8 + i; +/* Collect a parse error message. */ - return BPF_UNKNOWN; -} +static int partial_match_length = 0; +static char *errmsg = NULL; -static enum bpf_token_type -get_token (const char **insn, char *token, size_t *tlen) +static void +parse_error (int length, const char *fmt, ...) { -#define GET() \ - (*str == '\0' \ - ? EOF \ - : *(unsigned char *)(str++)) - -#define UNGET() (--str) - -#define START_EXPR() \ - do \ - { \ - if (expr == NULL) \ - expr = str - 1; \ - } while (0) - -#define SCANNER_SKIP_WHITESPACE() \ - do \ - { \ - do \ - ch = GET (); \ - while (ch != EOF \ - && ((ch) == ' ' || (ch) == '\t')); \ - if (ch != EOF) \ - UNGET (); \ - } while (0) - - const char *str = *insn; - int ch, ch2 = 0; - enum bpf_token_type ttype = BPF_UNKNOWN; - size_t len = 0; - const char *expr = NULL; - const char *end_expr = NULL; - int state = 0; - int return_token = 0; - - while (1) + if (length > partial_match_length) { - ch = GET (); - - if (ch == EOF || len > MAX_TOKEN_SZ) - break; - - switch (pseudoc_lex[(unsigned char) ch]) - { - case LEX_IS_WHITESPACE: - SCANNER_SKIP_WHITESPACE (); - return_token = 1; - - switch (state) - { - case 12: /* >' ' */ - ttype = BPF_JGT; - break; - - case 17: /* ==' ' */ - ttype = BPF_JEQ; - break; - - case 18: /* <' ' */ - ttype = BPF_JLT; - break; - - case 20: /* &' ' */ - ttype = BPF_JSET; - break; - - case 22: /* s<' '*/ - ttype = BPF_JSLT; - break; - - case 14: /* s> ' ' */ - ttype = BPF_JSGT; - break; - - case 16: /* =' ' */ - ttype = BPF_MOV; - break; - - default: - return_token = 0; - } - break; - - case LEX_IS_EXCLA: - token[len++] = ch; - state = 21; - break; - - case LEX_IS_ARITHM_OP: - if (state == 16) - { - /* ='-' is handle as '=' */ - UNGET (); - ttype = BPF_MOV; - return_token = 1; - break; - } - - START_EXPR(); - token[len++] = ch; - switch (ch) - { -#define BPF_ARITHM_OP(op, type) \ - case (op): \ - state = 6; \ - ttype = (type); \ - break; - - BPF_ARITHM_OP('+', BPF_ADD); - BPF_ARITHM_OP('-', BPF_SUB); - BPF_ARITHM_OP('*', BPF_MUL); - BPF_ARITHM_OP('/', BPF_DIV); - BPF_ARITHM_OP('|', BPF_OR); - BPF_ARITHM_OP('%', BPF_MOD); - BPF_ARITHM_OP('^', BPF_XOR); - - case '&': - state = 20; /* '&' */ - break; - - case '<': - switch (state) - { - case 0: - state = 18; /* '<' */ - break; - - case 18: - state = 19; /* <'<' */ - break; - - case 8: - state = 22; /* s'<' */ - break; - } - break; - - case '>': - switch (state) - { - case 0: - state = 12; /* '>' */ - break; - - case 12: - state = 13; /* >'>' */ - break; - - case 8: - state = 14; /* s'>' */ - break; - - case 14: - state = 15; /* s>'>' */ - break; - } - break; - } - break; - - case LEX_IS_STAR: - switch (state) - { - case 0: - token[len++] = ch; - START_EXPR (); - state = 2; /* '*', It could be the fist cast char. */ - break; - - case 16: /* ='*' Not valid token. */ - ttype = BPF_MOV; - return_token = 1; - UNGET (); - break; - - case 4: /* *(uXX'*' */ - token[len++] = ch; - state = 5; - break; - } - break; - - case LEX_IS_OPEN_BR: - START_EXPR (); - token[len++] = ch; - return_token = 1; - - switch (state) - { - case 2: - state = 3; /* *'(' second char of a cast or expr. */ - return_token = 0; - break; - - case 6: - if (valid_expr (expr, &end_expr)) - { - len = end_expr - expr; - memcpy (token, expr, len); - ttype = BPF_EXPR; - str = end_expr; - } - else - { - len = 0; - while (*invalid_expression) - token[len++] = *invalid_expression++; - - token[len] = 0; - ttype = BPF_UNKNOWN; - } - break; - - default: - ttype = BPF_CHR_OPEN_BR; - SCANNER_SKIP_WHITESPACE (); - ch2 = GET (); - - if ((isdigit (ch2) || ch2 == '(') - && valid_expr (expr, &end_expr)) - { - len = end_expr - expr; - memcpy (token, expr, len); - ttype = BPF_EXPR; - str = end_expr; - } - else - UNGET (); - } - break; - - case LEX_IS_CLSE_BR: - token[len++] = ch; - - if (state == 0) - { - ttype = BPF_CHR_CLSE_BR; - return_token = 1; - } - else if (state == 5) /* *(uXX*')' */ - return_token = 1; - break; - - case LEX_IS_EQUAL: - token[len++] = ch; - return_token = 1; - - switch (state) - { - case 0: - state = 16; /* '=' */ - return_token = 0; - break; - - case 16: - state = 17; /* ='=' */ - return_token = 0; - break; - - case 2: /* *'=' */ - ttype = BPF_MUL; - break; - - case 10: /* s>>'=' */ - ttype = BPF_ARSH; - break; - - case 12: /* >'=' */ - ttype = BPF_JGE; - break; - - case 13: /* >>'=' */ - ttype = BPF_RSH; - break; - - case 14: /* s>'=' */ - ttype = BPF_JSGE; - break; - - case 15: /* s>>'=' */ - ttype = BPF_ARSH; - break; - - case 18: /* <'=' */ - ttype = BPF_JLE; - break; - - case 19: /* <<'=' */ - ttype = BPF_LSH; - break; - - case 20: /* &'=' */ - ttype = BPF_AND; - break; - - case 21: /* !'=' */ - ttype = BPF_JNE; - break; - - case 22: /* s<'=' */ - ttype = BPF_JSLE; - break; - } - break; - - case LEX_IS_SYMBOL_COMPONENT: - return_token = 1; - - switch (state) - { - case 17: /* =='sym' */ - ttype = BPF_JEQ; - break; - - case 12: /* >'sym' */ - ttype = BPF_JGT; - break; - - case 18: /* <'sym' */ - ttype = BPF_JLT; - break; - - case 20: /* &'sym' */ - ttype = BPF_JSET; - break; - - case 14: /*s>'sym' */ - ttype = BPF_JSGT; - break; - - case 22: /* s<'sym' */ - ttype = BPF_JSLT; - break; - - case 16: /* ='sym' */ - ttype = BPF_MOV; - break; - - default: - return_token = 0; - } - - if (return_token) - { - UNGET (); - break; - } - - START_EXPR (); - token[len++] = ch; - - while ((ch2 = GET ()) != EOF) - { - int type; - - type = pseudoc_lex[(unsigned char) ch2]; - if (type != LEX_IS_SYMBOL_COMPONENT) - break; - token[len++] = ch2; - } - - if (ch2 != EOF) - UNGET (); - - if (state == 0) - { - if (len == 1 && ch == 's') - state = 8; /* signed instructions: 's' */ - else - { - ttype = BPF_SYMBOL; - if (is_register (token, len)) - ttype = BPF_REG; - else if (look_for_reserved_word (token, &ttype)) - ; - else if ((pseudoc_lex[(unsigned char) *token] == LEX_IS_ARITHM_OP - || *token == '(' || isdigit(*token)) - && valid_expr (expr, &end_expr)) - { - len = end_expr - expr; - token[len] = '\0'; - ttype = BPF_EXPR; - str = end_expr; - } - - return_token = 1; - } - } - else if (state == 3) /* *('sym' */ - { - if ((ttype = is_cast (&token[2])) != BPF_UNKNOWN) - state = 4; /* *('uXX' */ - else - { - ttype = BPF_EXPR; - return_token = 1; - } - } - else if (state == 6) - { - if (ttype == BPF_SUB) /* neg */ - { - if (is_register (&token[1], len - 1)) - ttype = BPF_NEG; - else if (valid_expr(expr, &end_expr)) - { - len = end_expr - expr; - memcpy(token, expr, len); - ttype = BPF_EXPR; - str = end_expr; - } - else - { - len = 0; - while (*invalid_expression) - token[len++] = *invalid_expression++; - token[len] = 0; - ttype = BPF_UNKNOWN; - } - } - else if (valid_expr (expr, &end_expr)) - { - len = end_expr - expr; - memcpy(token, expr, len); - ttype = BPF_EXPR; - str = end_expr; - } - else - ttype = BPF_UNKNOWN; - - return_token = 1; - } - break; - } + va_list args; - if (return_token) - { - *tlen = len; - *insn = str; - break; - } + free (errmsg); + va_start (args, fmt); + errmsg = xvasprintf (fmt, args); + va_end (args); + partial_match_length = length; } - - return ttype; - -#undef GET -#undef UNGET -#undef START_EXPR -#undef SCANNER_SKIP_WHITESPACE -#undef BPF_ARITHM_OP } -/* - The parser represent a FSM for the grammar described above. So for example - the following rule: - - ` bpf_alu_insn : BPF_REG bpf_alu_operator register_or_imm32' - - Is parser as follows: - - 1. It starts in state 0. +/* Assemble a machine instruction in STR and emit the frags/bytes it + assembles to. */ - 2. Consumes next token, e.g: `BPF_REG' and set `state' variable to a - particular state to helps to identify, in this case, that a register - token has been read, a comment surrounded by a single quote in the - pseudo-c token is added along with the new `state' value to indicate - what the scanner has read, e.g.: - - state = 6; // dst_reg = str_cast ( 'src_reg' - - So, in `state 6' the scanner has consumed: a destination register - (BPF_REG), an equal character (BPF_MOV), a cast token (BPF_CAST), an - open parenthesis (BPF_CHR_OPEN_BR) and the source register (BPF_REG). - - 3. If the accumulated tokens represent a complete BPF pseudo-c syntax - instruction then, a validation of the terms is made, for example: if - the registers have the same sizes (32/64 bits), if a specific - destination register must be used, etc., after that, a builder: - build_bfp_{non_generic_load,atomic_insn,jmp_insn,arithm_insn,endianness,load_store_insn} - is invoked, internally, it translates the BPF pseudo-c instruction to - a BPF GAS instruction using the previous terms recollected by the - scanner. - - 4. If a successful build of BPF GAS instruction was done, a final - state is set to `ST_EOI' (End Of Instruction) meaning that is not - expecting for more tokens in such instruction. Otherwise if the - conditions to calling builder are not satisfied an error is emitted - and `parse_err' is set. -*/ - -static char * -bpf_pseudoc_to_normal_syntax (const char *str, char **errmsg) +void +md_assemble (char *str ATTRIBUTE_UNUSED) { -#define syntax_err(format, ...) \ - do \ - { \ - if (! parse_err) \ - { \ - parse_err = 1; \ - errbuf = xasprintf (format, ##__VA_ARGS__); \ - } \ - } while (0) - - enum bpf_token_type ttype; - enum bpf_token_type bpf_endianness = BPF_UNKNOWN, - bpf_atomic_insn; - enum bpf_token_type bpf_jmp_op = BPF_JEQ; /* Arbitrary. */ - enum bpf_token_type bpf_cast = BPF_CAST_U8; /* Arbitrary. */ - enum bpf_token_type bpf_arithm_op = BPF_ADD; /* Arbitrary. */ - char *bpf_insn = NULL; - char *errbuf = NULL; - char src_reg[3] = {0}; - char dst_reg[3] = {0}; - char str_imm32[40] = {0}; - char str_offset[40] = {0}; - char str_symbol[MAX_TOKEN_SZ] = {0}; - char token[MAX_TOKEN_SZ] = {0}; - int state = 0; - int parse_err = 0; - size_t tlen; - - while (*str) + /* There are two different syntaxes that can be used to write BPF + instructions. One is very conventional and like any other + assembly language where each instruction is conformed by an + instruction mnemonic followed by its operands. This is what we + call the "normal" syntax. The other syntax tries to look like C + statements. We have to support both syntaxes in this assembler. + + One of the many nuisances introduced by this eccentricity is that + in the pseudo-c syntax it is not possible to hash the opcodes + table by instruction mnemonic, because there is none. So we have + no other choice than to try to parse all instruction opcodes + until one matches. This is slow. + + Another problem is that emitting detailed diagnostics becomes + tricky, since the lack of mnemonic means it is not clear what + instruction was intended by the user, and we cannot emit + diagnostics for every attempted template. So if an instruction + is not parsed, we report the diagnostic corresponding to the + partially parsed instruction that was matched further. */ + + unsigned int idx = 0; + struct bpf_insn insn; + const struct bpf_opcode *opcode; + + /* Initialize the global diagnostic variables. See the parse_error + function above. */ + partial_match_length = 0; + errmsg = NULL; + +#define PARSE_ERROR(...) parse_error (s - str, __VA_ARGS__) + + while ((opcode = bpf_get_opcode (idx++)) != NULL) { - ttype = get_token (&str, token, &tlen); - if (ttype == BPF_UNKNOWN || state == ST_EOI) - { - syntax_err ("unexpected token: '%s'", token); - break; - } - - switch (ttype) - { - case BPF_UNKNOWN: - case BPF_LL: - break; - - case BPF_REG: - switch (state) - { - case 0: - memcpy (dst_reg, token, tlen); - state = 1; /* 'dst_reg' */ - break; - - case 3: - /* dst_reg bpf_op 'src_reg' */ - memcpy (src_reg, token, tlen); - if (*dst_reg == *src_reg) - bpf_insn = build_bpf_arithm_insn (dst_reg, src_reg, 0, - NULL, bpf_arithm_op); - else - { - syntax_err ("different register sizes: '%s', '%s'", - dst_reg, src_reg); - break; - } - state = ST_EOI; - break; - - case 5: - memcpy (src_reg, token, tlen); - state = 6; /* dst_reg = str_cast ( 'src_reg' */ - break; - - case 9: - memcpy (dst_reg, token, tlen); - state = 10; /* str_cast ( 'dst_reg' */ - break; - - case 11: - /* str_cast ( dst_reg offset ) = 'src_reg' */ - memcpy (src_reg, token, tlen); - bpf_insn = build_bpf_load_store_insn (dst_reg, src_reg, - bpf_cast, str_offset, 0); - state = ST_EOI; - break; - - case 14: - memcpy (dst_reg, token, tlen); - state = 15; /* if 'dst_reg' */ - break; - - case 16: - memcpy (src_reg, token, tlen); - state = 17; /* if dst_reg jmp_op 'src_reg' */ - break; - - case 24: - /* dst_reg = endianness src_reg */ - memcpy (src_reg, token, tlen); - if (*dst_reg == 'r' && !strcmp (dst_reg, src_reg)) - bpf_insn = build_bpf_endianness (dst_reg, bpf_endianness); - else - syntax_err ("invalid operand for instruction: '%s'", token); - - state = ST_EOI; - break; - - case 28: - memcpy (dst_reg, token, tlen); - state = 29; /* lock str_cast ( 'dst_reg' */ - break; - - case 32: - { - /* lock str_cast ( dst_reg offset ) atomic_insn 'src_reg' */ - int with_offset = *str_offset != '\0'; - - memcpy (src_reg, token, tlen); - if ((bpf_cast != BPF_CAST_U32 - && bpf_cast != BPF_CAST_U64) - || *dst_reg != 'r' - || *src_reg != 'r') - syntax_err ("invalid wide atomic instruction"); - else - bpf_insn = build_bpf_atomic_insn (dst_reg, src_reg, bpf_atomic_insn, - bpf_cast, with_offset ? str_offset : str_symbol); - } - - state = ST_EOI; - break; - - case 33: - /* callx 'dst_reg' */ - bpf_insn = xasprintf ("%s %%%s", "call", token); - state = ST_EOI; - break; - - case 35: - memcpy (src_reg, token, tlen); - state = 36; /* dst_reg = str_cast skb [ 'src_reg' */ - break; - } - break; - - case BPF_MOV: - case BPF_ADD: - case BPF_SUB: - case BPF_MUL: - case BPF_DIV: - case BPF_OR: - case BPF_AND: - case BPF_LSH: - case BPF_RSH: - case BPF_MOD: - case BPF_XOR: - case BPF_ARSH: - case BPF_NEG: - switch (state) - { - case 1: - state = 3; /* dst_reg 'arith_op' */ - bpf_arithm_op = ttype; - break; - - case 3: - if (ttype == BPF_NEG) - { - /* reg = -reg */ - bpf_arithm_op = ttype; - memcpy (src_reg, token + 1, tlen - 1); - if (strcmp (dst_reg, src_reg)) - { - syntax_err ("found: '%s', expected: -%s", token, dst_reg); - break; - } - - bpf_insn = build_bpf_arithm_insn (dst_reg, src_reg, 0, - NULL, bpf_arithm_op); - state = ST_EOI; - } - break; - - case 23: - memcpy (src_reg, token, tlen); - state = 11; /* str_cast ( dst_reg offset ) '=' */ - break; - - case 12: - if (ttype == BPF_MOV) - state = 13; /* str_cast ( dst_reg offset ) '=' */ - break; - - case 31: - bpf_atomic_insn = ttype; - state = 32; /* lock str_cast ( dst_reg offset ) 'atomic_insn' */ - break; - - default: - syntax_err ("unexpected '%s'", token); - state = ST_EOI; - } - break; - - case BPF_CAST_U8: - case BPF_CAST_U16: - case BPF_CAST_U32: - case BPF_CAST_U64: - bpf_cast = ttype; - switch (state) - { - case 3: - state = 4; /* dst_reg = 'str_cast' */ - break; - - case 0: - state = 8; /* 'str_cast' */ - break; - - case 26: - state = 27; /* lock 'str_cast' */ - break; - } - break; - - case BPF_CHR_OPEN_BR: - switch (state) - { - case 4: - state = 5; /* dst_reg = str_cast '(' */ - break; - - case 8: - state = 9; /* str_cast '(' */ - break; - - case 27: - state = 28; /* lock str_cast '(' */ - break; - - case 34: - state = 35; /* dst_reg = str_cast skb '[' */ - break; - } - break; + const char *p; + char *s; + const char *template + = (asm_dialect == DIALECT_PSEUDOC ? opcode->pseudoc : opcode->normal); + + /* Do not try to match opcodes with a higher version than the + selected ISA spec. */ + if (opcode->version > isa_spec) + continue; + + memset (&insn, 0, sizeof (struct bpf_insn)); + insn.size = 8; + for (s = str, p = template; *p != '\0';) + { + if (*p == ' ') + { + /* Expect zero or more spaces. */ + while (*s != '\0' && (*s == ' ' || *s == '\t')) + s += 1; + p += 1; + } + else if (*p == '%') + { + if (*(p + 1) == '%') + { + if (*s != '%') + { + PARSE_ERROR ("expected '%%'"); + break; + } + p += 2; + s += 1; + } + else if (*(p + 1) == 'w') + { + /* Expect zero or more spaces. */ + while (*s != '\0' && (*s == ' ' || *s == '\t')) + s += 1; + p += 2; + } + else if (*(p + 1) == 'W') + { + /* Expect one or more spaces. */ + if (*s != ' ' && *s != '\t') + { + PARSE_ERROR ("expected white space, got '%s'", + s); + break; + } + while (*s != '\0' && (*s == ' ' || *s == '\t')) + s += 1; + p += 2; + } + else if (strncmp (p, "%dr", 3) == 0) + { + uint8_t regno; + char *news = parse_bpf_register (s, 'r', ®no); + + if (news == NULL || (insn.has_dst && regno != insn.dst)) + { + if (news != NULL) + PARSE_ERROR ("expected register r%d, got r%d", + insn.dst, regno); + else + PARSE_ERROR ("expected register name, got '%s'", s); + break; + } + s = news; + insn.dst = regno; + insn.has_dst = 1; + p += 3; + } + else if (strncmp (p, "%sr", 3) == 0) + { + uint8_t regno; + char *news = parse_bpf_register (s, 'r', ®no); + + if (news == NULL || (insn.has_src && regno != insn.src)) + { + if (news != NULL) + PARSE_ERROR ("expected register r%d, got r%d", + insn.dst, regno); + else + PARSE_ERROR ("expected register name, got '%s'", s); + break; + } + s = news; + insn.src = regno; + insn.has_src = 1; + p += 3; + } + else if (strncmp (p, "%dw", 3) == 0) + { + uint8_t regno; + char *news = parse_bpf_register (s, 'w', ®no); + + if (news == NULL || (insn.has_dst && regno != insn.dst)) + { + if (news != NULL) + PARSE_ERROR ("expected register r%d, got r%d", + insn.dst, regno); + else + PARSE_ERROR ("expected register name, got '%s'", s); + break; + } + s = news; + insn.dst = regno; + insn.has_dst = 1; + p += 3; + } + else if (strncmp (p, "%sw", 3) == 0) + { + uint8_t regno; + char *news = parse_bpf_register (s, 'w', ®no); + + if (news == NULL || (insn.has_src && regno != insn.src)) + { + if (news != NULL) + PARSE_ERROR ("expected register r%d, got r%d", + insn.dst, regno); + else + PARSE_ERROR ("expected register name, got '%s'", s); + break; + } + s = news; + insn.src = regno; + insn.has_src = 1; + p += 3; + } + else if (strncmp (p, "%i32", 4) == 0 + || strncmp (p, "%I32", 4) == 0) + { + if (p[1] == 'I') + { + while (*s == ' ' || *s == '\t') + s += 1; + if (*s != '+' && *s != '-') + { + PARSE_ERROR ("expected `+' or `-', got `%c'", *s); + break; + } + } + + s = parse_expression (s, &insn.imm32); + if (s == NULL) + { + PARSE_ERROR ("expected signed 32-bit immediate"); + break; + } + insn.has_imm32 = 1; + p += 4; + } + else if (strncmp (p, "%o16", 4) == 0) + { + while (*s == ' ' || *s == '\t') + s += 1; + if (*s != '+' && *s != '-') + { + PARSE_ERROR ("expected `+' or `-', got `%c'", *s); + break; + } + + s = parse_expression (s, &insn.offset16); + if (s == NULL) + { + PARSE_ERROR ("expected signed 16-bit offset"); + break; + } + insn.has_offset16 = 1; + p += 4; + } + else if (strncmp (p, "%d16", 4) == 0) + { + s = parse_expression (s, &insn.disp16); + if (s == NULL) + { + PARSE_ERROR ("expected signed 16-bit displacement"); + break; + } + insn.has_disp16 = 1; + p += 4; + } + else if (strncmp (p, "%d32", 4) == 0) + { + s = parse_expression (s, &insn.disp32); + if (s == NULL) + { + PARSE_ERROR ("expected signed 32-bit displacement"); + break; + } + insn.has_disp32 = 1; + p += 4; + } + else if (strncmp (p, "%i64", 4) == 0) + { + s = parse_expression (s, &insn.imm64); + if (s == NULL) + { + PARSE_ERROR ("expected signed 64-bit immediate"); + break; + } + insn.has_imm64 = 1; + insn.size = 16; + p += 4; + } + else + as_fatal (_("invalid %%-tag in BPF opcode '%s'\n"), template); + } + else + { + /* Match a literal character. */ + if (*s != *p) + { + if (*s == '\0') + PARSE_ERROR ("expected '%c'", *p); + else if (*s == '%') + { + /* This is to workaround a bug in as_bad. */ + char tmp[3]; + + tmp[0] = '%'; + tmp[1] = '%'; + tmp[2] = '\0'; + + PARSE_ERROR ("expected '%c', got '%s'", *p, tmp); + } + else + PARSE_ERROR ("expected '%c', got '%c'", *p, *s); + break; + } + p += 1; + s += 1; + } + } - case BPF_CHR_CLSE_BR: - switch (state) - { - case 7: - /* dst_reg = str_cast ( imm32 ')' */ - bpf_insn = build_bpf_load_store_insn (dst_reg, src_reg, - bpf_cast, str_imm32, 1); - state = ST_EOI; - break; - - case 11: - state = 12; /* str_cast ( dst_reg imm32 ')' */ - break; - - case 21: - /* dst_reg = str_cast ( src_reg offset ')' */ - bpf_insn = build_bpf_load_store_insn (dst_reg, src_reg, - bpf_cast, str_offset, 1); - state = ST_EOI; - break; - - case 22: - state = 23; /* str_cast ( dst_reg offset ')' */ - break; - - case 30: - state = 31; /* lock str_cast ( dst_reg offset ')' */ - break; - - case 37: - /* dst_reg = str_cast skb [ src_reg imm32 ']' */ - if (*dst_reg != 'w' && !strcmp ("r0", dst_reg)) - bpf_insn = build_bpf_non_generic_load (*src_reg != '\0' ? src_reg : NULL, - bpf_cast, str_imm32); - else - syntax_err ("invalid register operand: '%s'", dst_reg); - - state = ST_EOI; - break; - } - break; + if (*p == '\0') + { + /* Allow white spaces at the end of the line. */ + while (*s != '\0' && (*s == ' ' || *s == '\t')) + s += 1; + if (*s == '\0') + /* We parsed an instruction successfully. */ + break; + PARSE_ERROR ("extra junk at end of line"); + } + } - case BPF_EXPR: - switch (state) - { - case 3: - { - /* dst_reg bpf_arithm_op 'imm32' */ - int load64 = 0; - - memcpy (str_imm32, token, tlen); - memset (token, 0, tlen); - - if ((ttype = get_token (&str, token, &tlen)) == BPF_LL - && bpf_arithm_op == BPF_MOV) - load64 = 1; - else if (ttype != BPF_UNKNOWN) - syntax_err ("unexpected token: '%s'", token); - - if (load64 && *dst_reg == 'w') - syntax_err ("unexpected register size: '%s'", dst_reg); - - if (! parse_err) - bpf_insn = build_bpf_arithm_insn (dst_reg, NULL, load64, - str_imm32, bpf_arithm_op); - state = ST_EOI; - } - break; - - case 18: - { - /* if dst_reg jmp_op src_reg goto 'offset' */ - int with_src = *src_reg != '\0'; - - memcpy (str_offset, token, tlen); - if (with_src && *dst_reg != *src_reg) - syntax_err ("different register size: '%s', '%s'", - dst_reg, src_reg); - else - bpf_insn = build_bpf_jmp_insn (dst_reg, with_src ? src_reg : NULL, - with_src ? NULL: str_imm32, - bpf_jmp_op, NULL, str_offset); - state = ST_EOI; - } - break; - - case 19: - /* goto 'offset' */ - memcpy (str_offset, token, tlen); - bpf_insn = xasprintf ("%s %s", "ja", str_offset); - state = ST_EOI; - break; - - case 6: - memcpy (str_offset, token, tlen); - state = 21; /* dst_reg = str_cast ( src_reg 'offset' */ - break; - - case 10: - memcpy (str_offset, token, tlen); - state = 22; /* str_cast ( dst_reg 'offset' */ - break; - - case 16: - memcpy (str_imm32, token, tlen); - state = 25; /* if dst_reg jmp_op 'imm32' */ - break; - - case 29: - memcpy (str_offset, token, tlen); - state = 30; /* lock str_cast ( dst_reg 'offset' */ - break; - - case 34: - /* dst_reg = str_cast skb 'imm32' */ - if (*dst_reg != 'w' && !strcmp ("r0", dst_reg)) - { - memcpy (str_imm32, token, tlen); - bpf_insn = build_bpf_non_generic_load (*src_reg != '\0' ? src_reg : NULL, - bpf_cast, str_imm32); - } - else - syntax_err ("invalid register operand: '%s'", dst_reg); - - state = ST_EOI; - break; - - case 36: - memcpy (str_imm32, token, tlen); - state = 37; /* dst_reg = str_cast skb [ src_reg 'imm32' */ - break; - } - break; + if (opcode == NULL) + { + as_bad (_("unrecognized instruction `%s'"), str); + if (errmsg != NULL) + { + as_bad (errmsg); + free (errmsg); + } - case BPF_IF: - if (state == 0) - state = 14; - break; + return; + } + insn.opcode = opcode->opcode; - case BPF_JSGT: - case BPF_JSLT: - case BPF_JSLE: - case BPF_JSGE: - case BPF_JGT: - case BPF_JGE: - case BPF_JLE: - case BPF_JSET: - case BPF_JNE: - case BPF_JLT: - case BPF_JEQ: - if (state == 15) - { - bpf_jmp_op = ttype; - state = 16; /* if dst_reg 'jmp_op' */ - } - break; +#undef PARSE_ERROR - case BPF_GOTO: - switch (state) - { - case 17: - case 25: - state = 18; /* if dst_reg jmp_op src_reg|imm32 'goto' */ - break; - - case 0: - state = 19; - break; - } - break; + /* Generate the frags and fixups for the parsed instruction. */ + { + char *this_frag = frag_more (insn.size); + char bytes[16]; + uint8_t src, dst; + int i; + + /* Zero all the bytes. */ + memset (bytes, 0, 16); + + /* First encode the opcodes. Note that we have to handle the + endianness groups of the BPF instructions: 8 | 4 | 4 | 16 | + 32. */ + if (target_big_endian) + { + /* code */ + bytes[0] = (insn.opcode >> 56) & 0xff; + /* regs */ + bytes[1] = (insn.opcode >> 48) & 0xff; + /* offset16 */ + bytes[2] = (insn.opcode >> 40) & 0xff; + bytes[3] = (insn.opcode >> 32) & 0xff; + /* imm32 */ + bytes[4] = (insn.opcode >> 24) & 0xff; + bytes[5] = (insn.opcode >> 16) & 0xff; + bytes[6] = (insn.opcode >> 8) & 0xff; + bytes[7] = insn.opcode & 0xff; + } + else + { + /* code */ + bytes[0] = (insn.opcode >> 56) & 0xff; + /* regs */ + bytes[1] = (((((insn.opcode >> 48) & 0xff) & 0xf) << 4) + | (((insn.opcode >> 48) & 0xff) & 0xf)); + /* offset16 */ + bytes[3] = (insn.opcode >> 40) & 0xff; + bytes[2] = (insn.opcode >> 32) & 0xff; + /* imm32 */ + bytes[7] = (insn.opcode >> 24) & 0xff; + bytes[6] = (insn.opcode >> 16) & 0xff; + bytes[5] = (insn.opcode >> 8) & 0xff; + bytes[4] = insn.opcode & 0xff; + } - case BPF_SYMBOL: - switch (state) - { - case 18: - { - /* if dst_reg jmp_op src_reg goto 'sym' */ - int with_src = *src_reg != '\0'; - - memcpy (str_symbol, token, tlen); - if (with_src && *dst_reg != *src_reg) - syntax_err ("different register size: '%s', '%s'", - dst_reg, src_reg); - else - bpf_insn = build_bpf_jmp_insn (dst_reg, with_src ? src_reg : NULL, - with_src ? NULL: str_imm32, - bpf_jmp_op, str_symbol, NULL); - state = ST_EOI; - } - break; - - case 19: - /* goto 'sym' */ - memcpy (str_symbol, token, tlen); - bpf_insn = xasprintf ("%s %s", "ja", str_symbol); - state = ST_EOI; - break; - - case 0: - state = ST_EOI; - break; - - case 3: - { - /* dst_reg arithm_op 'sym' */ - int load64 = 0; - - memcpy (str_symbol, token, tlen); - memset (token, 0, tlen); - - if ((ttype = get_token (&str, token, &tlen)) == BPF_LL - && bpf_arithm_op == BPF_MOV) - load64 = 1; - else if (ttype != BPF_UNKNOWN) - syntax_err ("unexpected token: '%s'", token); - - if (load64 && *dst_reg == 'w') - syntax_err ("unexpected register size: '%s'", dst_reg); - - if (! parse_err) - bpf_insn = build_bpf_arithm_insn (dst_reg, NULL, load64, - str_symbol, bpf_arithm_op); - state = ST_EOI; - } - break; - } - break; + /* Now the registers. */ + src = insn.has_src ? insn.src : 0; + dst = insn.has_dst ? insn.dst : 0; - case BPF_LE16: - case BPF_LE32: - case BPF_LE64: - case BPF_BE16: - case BPF_BE32: - case BPF_BE64: - bpf_endianness = ttype; - state = 24; /* dst_reg = 'endianness' */ - break; + if (target_big_endian) + bytes[1] = ((dst & 0xf) << 4) | (src & 0xf); + else + bytes[1] = ((src & 0xf) << 4) | (dst & 0xf); - case BPF_LOCK: - state = 26; - break; + /* Now the immediates. */ + if (insn.has_imm64) + { + switch (insn.imm64.X_op) + { + case O_constant: + { + uint64_t imm64 = insn.imm64.X_add_number; + + if (target_big_endian) + { + bytes[12] = (imm64 >> 56) & 0xff; + bytes[13] = (imm64 >> 48) & 0xff; + bytes[14] = (imm64 >> 40) & 0xff; + bytes[15] = (imm64 >> 32) & 0xff; + bytes[4] = (imm64 >> 24) & 0xff; + bytes[5] = (imm64 >> 16) & 0xff; + bytes[6] = (imm64 >> 8) & 0xff; + bytes[7] = imm64 & 0xff; + } + else + { + bytes[15] = (imm64 >> 56) & 0xff; + bytes[14] = (imm64 >> 48) & 0xff; + bytes[13] = (imm64 >> 40) & 0xff; + bytes[12] = (imm64 >> 32) & 0xff; + bytes[7] = (imm64 >> 24) & 0xff; + bytes[6] = (imm64 >> 16) & 0xff; + bytes[5] = (imm64 >> 8) & 0xff; + bytes[4] = imm64 & 0xff; + } + break; + } + case O_symbol: + case O_subtract: + case O_add: + { + reloc_howto_type *reloc_howto; + int size; + + reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_64); + if (!reloc_howto) + abort (); + + size = bfd_get_reloc_size (reloc_howto); + + fix_new_exp (frag_now, this_frag - frag_now->fr_literal, + size, &insn.imm64, reloc_howto->pc_relative, + BFD_RELOC_BPF_64); + break; + } + default: + abort (); + } + } - case BPF_IND_CALL: - state = 33; - break; + if (insn.has_imm32) + { + switch (insn.imm32.X_op) + { + case O_constant: + { + uint32_t imm32 = insn.imm32.X_add_number; + + if (target_big_endian) + { + bytes[4] = (imm32 >> 24) & 0xff; + bytes[5] = (imm32 >> 16) & 0xff; + bytes[6] = (imm32 >> 8) & 0xff; + bytes[7] = imm32 & 0xff; + } + else + { + bytes[7] = (imm32 >> 24) & 0xff; + bytes[6] = (imm32 >> 16) & 0xff; + bytes[5] = (imm32 >> 8) & 0xff; + bytes[4] = imm32 & 0xff; + } + break; + } + case O_symbol: + case O_subtract: + case O_add: + case O_uminus: + { + reloc_howto_type *reloc_howto; + int size; + + reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); + if (!reloc_howto) + abort (); + + size = bfd_get_reloc_size (reloc_howto); + + fix_new_exp (frag_now, this_frag - frag_now->fr_literal + 4, + size, &insn.imm32, reloc_howto->pc_relative, + BFD_RELOC_32); + break; + } + default: + abort (); + } + } - case BPF_LD: - state = 34; /* dst_reg = str_cast 'skb' */ - break; - } + if (insn.has_disp32) + { + switch (insn.disp32.X_op) + { + case O_constant: + { + uint32_t disp32 = insn.disp32.X_add_number; + + if (target_big_endian) + { + bytes[4] = (disp32 >> 24) & 0xff; + bytes[5] = (disp32 >> 16) & 0xff; + bytes[6] = (disp32 >> 8) & 0xff; + bytes[7] = disp32 & 0xff; + } + else + { + bytes[7] = (disp32 >> 24) & 0xff; + bytes[6] = (disp32 >> 16) & 0xff; + bytes[5] = (disp32 >> 8) & 0xff; + bytes[4] = disp32 & 0xff; + } + break; + } + case O_symbol: + case O_subtract: + case O_add: + { + reloc_howto_type *reloc_howto; + int size; + + reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP32); + if (!reloc_howto) + abort (); + + size = bfd_get_reloc_size (reloc_howto); + + fix_new_exp (frag_now, this_frag - frag_now->fr_literal, + size, &insn.disp32, reloc_howto->pc_relative, + BFD_RELOC_BPF_DISP32); + break; + } + default: + abort (); + } + } - memset (token, 0, tlen); - } + if (insn.has_offset16) + { + switch (insn.offset16.X_op) + { + case O_constant: + { + uint32_t offset16 = insn.offset16.X_add_number; + + if (target_big_endian) + { + bytes[2] = (offset16 >> 8) & 0xff; + bytes[3] = offset16 & 0xff; + } + else + { + bytes[3] = (offset16 >> 8) & 0xff; + bytes[2] = offset16 & 0xff; + } + break; + } + case O_symbol: + case O_subtract: + case O_add: + { + reloc_howto_type *reloc_howto; + int size; + + reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP16); + if (!reloc_howto) + abort (); + + size = bfd_get_reloc_size (reloc_howto); + + fix_new_exp (frag_now, this_frag - frag_now->fr_literal, + size, &insn.offset16, reloc_howto->pc_relative, + BFD_RELOC_BPF_DISP16); + break; + } + default: + abort (); + } + } - if (state != ST_EOI) - syntax_err ("incomplete instruction"); + if (insn.has_disp16) + { + switch (insn.disp16.X_op) + { + case O_constant: + { + uint32_t disp16 = insn.disp16.X_add_number; + + if (target_big_endian) + { + bytes[2] = (disp16 >> 8) & 0xff; + bytes[3] = disp16 & 0xff; + } + else + { + bytes[3] = (disp16 >> 8) & 0xff; + bytes[2] = disp16 & 0xff; + } + break; + } + case O_symbol: + case O_subtract: + case O_add: + { + reloc_howto_type *reloc_howto; + int size; + + reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP16); + if (!reloc_howto) + abort (); + + size = bfd_get_reloc_size (reloc_howto); + + fix_new_exp (frag_now, this_frag - frag_now->fr_literal, + size, &insn.disp16, reloc_howto->pc_relative, + BFD_RELOC_BPF_DISP16); + break; + } + default: + abort (); + } + } - *errmsg = errbuf; - return bpf_insn; + /* Emit bytes. */ + for (i = 0; i < insn.size; ++i) + { + md_number_to_chars (this_frag, (valueT) bytes[i], 1); + this_frag += 1; + } + } -#undef syntax_err + /* Emit DWARF2 debugging information. */ + dwarf2_emit_insn (insn.size); } -void -md_assemble (char *str) -{ - const CGEN_INSN *insn; - char *errmsg; - char *a_errmsg; - CGEN_FIELDS fields; - char *normal; - -#if CGEN_INT_INSN_P - CGEN_INSN_INT buffer[CGEN_MAX_INSN_SIZE / sizeof (CGEN_INT_INSN_P)]; -#else - unsigned char buffer[CGEN_MAX_INSN_SIZE]; -#endif - - gas_cgen_init_parse (); - insn = bpf_cgen_assemble_insn (gas_cgen_cpu_desc, str, &fields, - buffer, &errmsg); - if (insn == NULL) - { - normal = bpf_pseudoc_to_normal_syntax (str, &a_errmsg); - if (normal) - { - insn = bpf_cgen_assemble_insn (gas_cgen_cpu_desc, normal, &fields, - buffer, &a_errmsg); - xfree (normal); - } - - if (insn == NULL) - { - as_bad ("%s", errmsg); - if (a_errmsg) - { - as_bad ("%s", a_errmsg); - xfree (a_errmsg); - } - return; - } - } - - gas_cgen_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (&fields), - 0, /* zero to ban relaxable insns. */ - NULL); /* NULL so results not returned here. */ -} +/* Parse an operand that is machine-specific. */ void md_operand (expressionS *expressionP) { - invalid_expression = input_line_pointer - 1; - gas_cgen_md_operand (expressionP); + /* If this hook is invoked it means GAS failed to parse a generic + expression. We should inhibit the as_bad in expr.c, so we can fail + while parsing instruction alternatives. To do that, we change the + expression to not have an O_absent. But then we also need to set + exp_parse_failed to parse_expression above does the right thing. */ + ++input_line_pointer; + expressionP->X_op = O_constant; + expressionP->X_add_number = 0; + exp_parse_failed = 1; } - symbolS * md_undefined_symbol (char *name ATTRIBUTE_UNUSED) { @@ -1929,3 +1192,29 @@ md_atof (int type, char *litP, int *sizeP) { return ieee_md_atof (type, litP, sizeP, false); } + + +/* Determine whether the equal sign in the given string corresponds to + a BPF instruction, i.e. when it is not to be considered a symbol + assignment. */ + +bool +bpf_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char *str ATTRIBUTE_UNUSED) +{ + uint8_t regno; + + /* Only pseudo-c instructions can have equal signs, and of these, + all that could be confused with a symbol assignment all start + with a register name. */ + if (asm_dialect == DIALECT_PSEUDOC) + { + char *w = parse_bpf_register (str, 'w', ®no); + char *r = parse_bpf_register (str, 'r', ®no); + + if ((w != NULL && *w == '\0') + || (r != NULL && *r == '\0')) + return 1; + } + + return 0; +} diff --git a/gas/config/tc-bpf.h b/gas/config/tc-bpf.h index db604db..d57a66f 100644 --- a/gas/config/tc-bpf.h +++ b/gas/config/tc-bpf.h @@ -37,7 +37,6 @@ /* .-foo gets turned into PC relative relocs. */ #define DIFF_EXPR_OK 1 -#define GAS_CGEN_PCREL_R_TYPE(R_TYPE) gas_cgen_pcrel_r_type (R_TYPE) /* Call md_pcrel_from_section(), not md_pcrel_from(). */ #define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC) @@ -52,4 +51,5 @@ a jump to offset 0 means jump to the next instruction. */ #define md_single_noop_insn "ja 0" -#define TC_EQUAL_IN_INSN(c, s) 1 +#define TC_EQUAL_IN_INSN(c, s) bpf_tc_equal_in_insn ((c), (s)) +extern bool bpf_tc_equal_in_insn (int, char *); diff --git a/gas/configure b/gas/configure index 86d90ab..dbb3425 100755 --- a/gas/configure +++ b/gas/configure @@ -12301,7 +12301,6 @@ cat >>confdefs.h <<_ACEOF _ACEOF fi - using_cgen=yes ;; epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k) using_cgen=yes diff --git a/gas/configure.ac b/gas/configure.ac index 96eeb78..13adaad 100644 --- a/gas/configure.ac +++ b/gas/configure.ac @@ -454,7 +454,6 @@ changequote([,])dnl if test $this_target = $target ; then AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.]) fi - using_cgen=yes ;; epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k) using_cgen=yes diff --git a/gas/doc/c-bpf.texi b/gas/doc/c-bpf.texi index 0756796..4742f89 100644 --- a/gas/doc/c-bpf.texi +++ b/gas/doc/c-bpf.texi @@ -15,15 +15,15 @@ @cindex BPF support @menu -* BPF Options:: Options -* BPF Syntax:: Syntax -* BPF Directives:: Machine Directives -* BPF Opcodes:: Opcodes -* BPF Pseudo-C Syntax:: Alternative Pseudo-C Assembly Syntax +* BPF Options:: BPF specific command-line options. +* BPF Special Characters:: Comments and statements. +* BPF Registers:: Register names. +* BPF Directives:: Machine directives. +* BPF Instructions:: Machine instructions. @end menu @node BPF Options -@section Options +@section BPF Options @cindex BPF options (none) @cindex options for BPF (none) @@ -38,22 +38,29 @@ This option specifies that the assembler should emit big-endian eBPF. @item -EL This option specifies that the assembler should emit little-endian eBPF. + +@cindex @option{-mdialect} command-line options, BPF +@item -mdialect=@var{dialect} +This option specifies the assembly language dialect to recognize while +assembling. The assembler supports @option{normal} and +@option{pseudoc}. + +@cindex @option{-misa-spec} command-line options, BPF +@item -misa-spec=@var{spec} +This option specifies the version of the BPF instruction set to use +when assembling. The BPF ISA versions supported are @option{v1} @option{v2}, @option{v3} and @option{v4}. + +The value @option{xbpf} can be specified to recognize extra +instructions that are used by GCC for testing purposes. But beware +this is not valid BPF. @end table Note that if no endianness option is specified in the command line, the host endianness is used. @c man end -@node BPF Syntax -@section Syntax -@menu -* BPF-Chars:: Special Characters -* BPF-Regs:: Register Names -* BPF-Pseudo-Maps:: Pseudo map fds -@end menu - -@node BPF-Chars -@subsection Special Characters +@node BPF Special Characters +@section BPF Special Characters @cindex line comment character, BPF @cindex BPF line comment character @@ -64,50 +71,49 @@ the first character of a line, the whole line is treated as a comment. @cindex statement separator, BPF Statements and assembly directives are separated by newlines. -@node BPF-Regs -@subsection Register Names +@node BPF Registers +@section BPF Registers @cindex BPF register names @cindex register names, BPF The eBPF processor provides ten general-purpose 64-bit registers, which are read-write, and a read-only frame pointer register: +@noindent +In normal syntax: + @table @samp @item %r0 .. %r9 General-purpose registers. @item %r10 -Frame pointer register. +@itemx %fp +Read-only frame pointer register. @end table -Some registers have additional names, to reflect their role in the -eBPF ABI: +All BPF registers are 64-bit long. However, in the Pseudo-C syntax +registers can be referred using different names, which actually +reflect the kind of instruction they appear on: + +@noindent +In pseudoc syntax: @table @samp -@item %a -This is @samp{%r0}. -@item %ctx -This is @samp{%r6}. -@item %fp -This is @samp{%r10}. +@item r0..r9 +General-purpose register in an instruction that operates on its value +as if it was a 64-bit value. +@item w0..w9 +General-purpose register in an instruction that operates on its value +as if it was a 32-bit value. +@item r10 +Read-only frame pointer register. @end table -@node BPF-Pseudo-Maps -@subsection Pseudo Maps - -@cindex pseudo map fd, BPF -The @samp{LDDW} instruction can take a literal pseudo map file -descriptor as its second argument. This uses the syntax -@samp{%map_fd(N)} where @samp{N} is a signed number. - -For example, to load the address of the pseudo map with file -descriptor @samp{2} in register @samp{r1} we would do: - -@smallexample - lddw %r1, %map_fd(2) -@end smallexample +@noindent +Note that in the Pseudo-C syntax register names are not preceded by +@code{%} characters. @node BPF Directives -@section Machine Directives +@section BPF Directives @cindex machine directives, BPF @@ -128,8 +134,8 @@ The @code{.word} directive produces a 32 bit value. The @code{.dword} directive produces a 64 bit value. @end table -@node BPF Opcodes -@section Opcodes +@node BPF Instructions +@section BPF Instructions @cindex BPF opcodes @cindex opcodes for BPF @@ -137,10 +143,10 @@ In the instruction descriptions below the following field descriptors are used: @table @code -@item %d -Destination general-purpose register whose role is to be destination -of an operation. -@item %s +@item rd +Destination general-purpose register whose role is to be the +destination of an operation. +@item rs Source general-purpose register whose role is to be the source of an operation. @item disp16 @@ -150,104 +156,237 @@ minus one. 32-bit signed PC-relative offset, measured in number of 64-bit words, minus one. @item offset16 -Signed 16-bit immediate. +Signed 16-bit immediate representing an offset in bytes. +@item disp16 +Signed 16-bit immediate representing a displacement to a target, +measured in number of 64-bit words @emph{minus one}. @item imm32 Signed 32-bit immediate. @item imm64 Signed 64-bit immediate. @end table -@subsubsection Arithmetic instructions +@subsection Arithmetic instructions The destination register in these instructions act like an accumulator. +Note that in pseudoc syntax these instructions should use @code{r} +registers. + @table @code -@item add %d, (%s|imm32) +@item add rd, rs +@itemx add rd, imm32 +@itemx rd += rs +@itemx rd += imm32 64-bit arithmetic addition. -@item sub %d, (%s|imm32) + +@item sub rd, rs +@itemx sub rd, rs +@itemx rd -= rs +@itemx rd -= imm32 64-bit arithmetic subtraction. -@item mul %d, (%s|imm32) + +@item mul rd, rs +@itemx mul rd, imm32 +@itemx rd *= rs +@itemx rd *= imm32 64-bit arithmetic multiplication. -@item div %d, (%s|imm32) + +@item div rd, rs +@itemx div rd, imm32 +@itemx rd /= rs +@itemx rd /= imm32 64-bit arithmetic integer division. -@item mod %d, (%s|imm32) + +@item mod rd, rs +@itemx mod rd, imm32 +@itemx rd %= rs +@itemx rd %= imm32 64-bit integer remainder. -@item and %d, (%s|imm32) + +@item and rd, rs +@itemx and rd, imm32 +@itemx rd &= rs +@itemx rd &= imm32 64-bit bit-wise ``and'' operation. -@item or %d, (%s|imm32) + +@item or rd, rs +@itemx or rd, imm32 +@itemx rd |= rs +@itemx rd |= imm32 64-bit bit-wise ``or'' operation. -@item xor %d, (%s|imm32) + +@item xor rd, imm32 +@itemx xor rd, rs +@itemx rd ^= rs +@itemx rd ^= imm32 64-bit bit-wise exclusive-or operation. -@item lsh %d, (%s|imm32) -64-bit left shift, by @code{%s} or @code{imm32} bits. -@item rsh %d, (%s|imm32) -64-bit right logical shift, by @code{%s} or @code{imm32} bits. -@item arsh %d, (%s|imm32) -64-bit right arithmetic shift, by @code{%s} or @code{imm32} bits. -@item neg %d + +@item lsh rd, rs +@itemx ldh rd, imm32 +@itemx rd <<= rs +@itemx rd <<= imm32 +64-bit left shift, by @code{rs} or @code{imm32} bits. + +@item rsh %d, %s +@itemx rsh rd, imm32 +@itemx rd >>= rs +@itemx rd >>= imm32 +64-bit right logical shift, by @code{rs} or @code{imm32} bits. + +@item arsh rd, rs +@itemx arsh rd, imm32 +@itemx rd s>>= rs +@itemx rd s>>= imm32 +64-bit right arithmetic shift, by @code{rs} or @code{imm32} bits. + +@item neg rd, rs +@itemx neg rd, imm32 +@itemx rd = - rs +@itemx rd = - imm32 64-bit arithmetic negation. -@item mov %d, (%s|imm32) -Move the 64-bit value of @code{%s} in @code{%d}, or load @code{imm32} -in @code{%d}. + +Note that in the @code{rd = - imm32} syntax there must be at least +one white space between @code{-} and @code{imm32}. Otherwise the +instruction is parsed as a @code{mov rd, imm32} instruction with a +negative 32-bit immediate. This is a consequence of a syntactic +ambiguity in the pseudoc syntax. + +@item mov rd, rs +@itemx mov rd, imm32 +@itemx rd = rs +@itemx rd = imm32 +Move the 64-bit value of @code{rs} in @code{rd}, or load @code{imm32} +in @code{rd}. @end table -@subsubsection 32-bit arithmetic instructions +@subsection 32-bit arithmetic instructions The destination register in these instructions act as an accumulator. +Note that in pseudoc syntax these instructions should use @code{w} +registers. It is not allowed to mix @code{w} and @code{r} registers +in the same instruction. + @table @code -@item add32 %d, (%s|imm32) +@item add32 rd, rs +@itemx add32 rd, imm32 +@itemx rd += rs +@itemx rd += imm32 32-bit arithmetic addition. -@item sub32 %d, (%s|imm32) + +@item sub32 rd, rs +@itemx sub32 rd, imm32 +@itemx rd -= rs +@itemx rd += imm32 32-bit arithmetic subtraction. -@item mul32 %d, (%s|imm32) + +@item mul32 rd, rs +@itemx mul32 rd, imm32 +@itemx rd *= rs +@itemx rd *= imm32 32-bit arithmetic multiplication. -@item div32 %d, (%s|imm32) + +@item div32 rd, rs +@itemx div32 rd, imm32 +@itemx rd /= rs +@itemx rd /= imm32 32-bit arithmetic integer division. -@item mod32 %d, (%s|imm32) + +@item mod32 rd, rs +@itemx mod32 rd, imm32 +@itemx rd %= rs +@itemx rd %= imm32 32-bit integer remainder. -@item and32 %d, (%s|imm32) + +@item and32 rd, rs +@itemx and32 rd, imm32 +@itemx rd &= rs +@itemx rd &= imm32 32-bit bit-wise ``and'' operation. -@item or32 %d, (%s|imm32) + +@item or32 rd, rs +@itemx or32 rd, imm32 +@itemx rd |= rs +@itemx rd |= imm32 32-bit bit-wise ``or'' operation. -@item xor32 %d, (%s|imm32) + +@item xor32 rd, rs +@itemx xor32 rd, imm32 +@itemx rd ^= rs +@itemx rd ^= imm32 32-bit bit-wise exclusive-or operation. -@item lsh32 %d, (%s|imm32) -32-bit left shift, by @code{%s} or @code{imm32} bits. -@item rsh32 %d, (%s|imm32) -32-bit right logical shift, by @code{%s} or @code{imm32} bits. -@item arsh32 %d, (%s|imm32) -32-bit right arithmetic shift, by @code{%s} or @code{imm32} bits. -@item neg32 %d + +@item lsh32 rd, rs +@itemx lsh32 rd, imm32 +@itemx rd <<= rs +@itemx rd <<= imm32 +32-bit left shift, by @code{rs} or @code{imm32} bits. + +@item rsh32 rd, rs +@itemx rsh32 rd, imm32 +@itemx rd >>= rs +@itemx rd >>= imm32 +32-bit right logical shift, by @code{rs} or @code{imm32} bits. + +@item arsh32 rd, rs +@itemx arsh32 rd, imm32 +@itemx rd s>>= rs +@itemx rd s>>= imm32 +32-bit right arithmetic shift, by @code{rs} or @code{imm32} bits. + +@item neg32 rd, rs +@itemx neg32 rd, imm32 +@itemx rd = - rs +@itemx rd = - imm32 32-bit arithmetic negation. -@item mov32 %d, (%s|imm32) -Move the 32-bit value of @code{%s} in @code{%d}, or load @code{imm32} -in @code{%d}. + +Note that in the @code{rd = - imm32} syntax there must be at least +one white space between @code{-} and @code{imm32}. Otherwise the +instruction is parsed as a @code{mov32 rd, imm32} instruction with a +negative 32-bit immediate. This is a consequence of a syntactic +ambiguity in the pseudoc syntax. + +@item mov32 rd, rs +@itemx mov32 rd, imm32 +@itemx rd = rs +@itemx rd = imm32 +Move the 32-bit value of @code{rs} in @code{rd}, or load @code{imm32} +in @code{rd}. @end table -@subsubsection Endianness conversion instructions +@subsection Endianness conversion instructions @table @code -@item endle %d, (16|32|64) -Convert the 16-bit, 32-bit or 64-bit value in @code{%d} to -little-endian. -@item endbe %d, (16|32|64) -Convert the 16-bit, 32-bit or 64-bit value in @code{%d} to big-endian. +@item endle rd, 16 +@itemx endle rd, 32 +@itemx endle rd, 64 +@itemx rd = le16 rd +@itemx rd = le32 rd +@itemx rd = le64 rd +Convert the 16-bit, 32-bit or 64-bit value in @code{rd} to +little-endian and store it back in @code{rd}. +@item endbe %d, 16 +@itemx endbe %d, 32 +@itemx endbe %d, 64 +@itemx rd = be16 rd +@itemx rd = be32 rd +@itemx rd = be64 rd +Convert the 16-bit, 32-bit or 64-bit value in @code{rd} to big-endian +and store it back in @code{rd}. @end table -@subsubsection 64-bit load and pseudo maps +@subsection 64-bit load and pseudo maps @table @code -@item lddw %d, imm64 -Load the given signed 64-bit immediate, or pseudo map descriptor, to -the destination register @code{%d}. -@item lddw %d, %map_fd(N) -Load the address of the given pseudo map fd @emph{N} to the -destination register @code{%d}. +@item lddw rd, imm64 +@itemx rd = imm64 ll +Load the given signed 64-bit immediate to the destination register +@code{rd}. @end table -@subsubsection Load instructions for socket filters +@subsection Load instructions for socket filters The following instructions are intended to be used in socket filters, and are therefore not general-purpose: they make assumptions on the @@ -259,29 +398,43 @@ Absolute loads: @table @code @item ldabsdw imm32 +@itemx r0 = *(u64 *) skb[imm32] Absolute 64-bit load. + @item ldabsw imm32 +@itemx r0 = *(u32 *) skb[imm32] Absolute 32-bit load. + @item ldabsh imm32 +@itemx r0 = *(u16 *) skb[imm32] Absolute 16-bit load. + @item ldabsb imm32 +@itemx r0 = *(u8 *) skb[imm32] Absolute 8-bit load. @end table Indirect loads: @table @code -@item ldinddw %s, imm32 +@item ldinddw rs, imm32 +@itemx r0 = *(u64 *) skb[rs + imm32] Indirect 64-bit load. -@item ldindw %s, imm32 + +@item ldindw rs, imm32 +@itemx r0 = *(u32 *) skb[rs + imm32] Indirect 32-bit load. -@item ldindh %s, imm32 + +@item ldindh rs, imm32 +@itemx r0 = *(u16 *) skb[rs + imm32] Indirect 16-bit load. + @item ldindb %s, imm32 +@itemx r0 = *(u8 *) skb[rs + imm32] Indirect 8-bit load. @end table -@subsubsection Generic load/store instructions +@subsection Generic load/store instructions General-purpose load and store instructions are provided for several word sizes. @@ -289,43 +442,64 @@ word sizes. Load to register instructions: @table @code -@item ldxdw %d, [%s+offset16] +@item ldxdw rd, [rs + offset16] +@itemx rd = *(u64 *) (rs + offset16) Generic 64-bit load. -@item ldxw %d, [%s+offset16] + +@item ldxw rd, [rs + offset16] +@itemx rd = *(u32 *) (rs + offset16) Generic 32-bit load. -@item ldxh %d, [%s+offset16] + +@item ldxh rd, [rs + offset16] +@itemx rd = *(u16 *) (rs + offset16) Generic 16-bit load. -@item ldxb %d, [%s+offset16] + +@item ldxb rd, [rs + offset16] +@itemx rd = *(u8 *) (rs + offset16) Generic 8-bit load. @end table Store from register instructions: @table @code -@item stxdw [%d+offset16], %s +@item stxdw [rd + offset16], %s +@itemx *(u64 *) (rd + offset16) Generic 64-bit store. -@item stxw [%d+offset16], %s + +@item stxw [rd + offset16], %s +@itemx *(u32 *) (rd + offset16) Generic 32-bit store. -@item stxh [%d+offset16], %s + +@item stxh [rd + offset16], %s +@itemx *(u16 *) (rd + offset16) Generic 16-bit store. -@item stxb [%d+offset16], %s + +@item stxb [rd + offset16], %s +@itemx *(u8 *) (rd + offset16) Generic 8-bit store. @end table Store from immediates instructions: @table @code -@item stddw [%d+offset16], imm32 +@item stdw [rd + offset16], imm32 +@itemx *(u64 *) (rd + offset16) = imm32 Store immediate as 64-bit. -@item stdw [%d+offset16], imm32 + +@item stw [rd + offset16], imm32 +@itemx *(u32 *) (rd + offset16) = imm32 Store immediate as 32-bit. -@item stdh [%d+offset16], imm32 + +@item sth [rd + offset16], imm32 +@itemx *(u16 *) (rd + offset16) = imm32 Store immediate as 16-bit. -@item stdb [%d+offset16], imm32 + +@item stb [rd + offset16], imm32 +@itemx *(u8 *) (rd + offset16) = imm32 Store immediate as 8-bit. @end table -@subsubsection Jump instructions +@subsection Jump instructions eBPF provides the following compare-and-jump instructions, which compare the values of the two given registers, or the values of a @@ -333,29 +507,74 @@ register and an immediate, and perform a branch in case the comparison holds true. @table @code -@item ja %d,(%s|imm32),disp16 +@item ja disp16 +@itemx goto disp16 Jump-always. -@item jeq %d,(%s|imm32),disp16 + +@item jeq rd, rs, disp16 +@itemx jeq rd, imm32, disp16 +@itemx if rd == rs goto disp16 +@itemx if rd == imm32 goto disp16 Jump if equal, unsigned. -@item jgt %d,(%s|imm32),disp16 + +@item jgt rd, rs, disp16 +@itemx jgt rd, imm32, disp16 +@itemx if rd > rs goto disp16 +@itemx if rd > imm32 goto disp16 Jump if greater, unsigned. -@item jge %d,(%s|imm32),disp16 + +@item jge rd, rs, disp16 +@itemx jge rd, imm32, disp16 +@itemx if rd >= rs goto disp16 +@itemx if rd >= imm32 goto disp16 Jump if greater or equal. -@item jlt %d,(%s|imm32),disp16 + +@item jlt rd, rs, disp16 +@itemx jlt rd, imm32, disp16 +@itemx if rd < rs goto disp16 +@itemx if rd < imm32 goto disp16 Jump if lesser. -@item jle %d,(%s|imm32),disp16 + +@item jle rd , rs, disp16 +@itemx jle rd, imm32, disp16 +@itemx if rd <= rs goto disp16 +@itemx if rd <= imm32 goto disp16 Jump if lesser or equal. -@item jset %d,(%s|imm32),disp16 + +@item jset rd, rs, disp16 +@itemx jset rd, imm32, disp16 +@itemx if rd & rs goto disp16 +@itemx if rd & imm32 goto disp16 Jump if signed equal. -@item jne %d,(%s|imm32),disp16 + +@item jne rd, rs, disp16 +@itemx jne rd, imm32, disp16 +@itemx if rd != rs goto disp16 +@itemx if rd != imm32 goto disp16 Jump if not equal. -@item jsgt %d,(%s|imm32),disp16 + +@item jsgt rd, rs, disp16 +@itemx jsgt rd, imm32, disp16 +@itemx if rd s> rs goto disp16 +@itemx if rd s> imm32 goto disp16 Jump if signed greater. -@item jsge %d,(%s|imm32),disp16 + +@item jsge rd, rs, disp16 +@itemx jsge rd, imm32, disp16 +@itemx if rd s>= rd goto disp16 +@itemx if rd s>= imm32 goto disp16 Jump if signed greater or equal. -@item jslt %d,(%s|imm32),disp16 + +@item jslt rd, rs, disp16 +@itemx jslt rd, imm32, disp16 +@itemx if rd s< rs goto disp16 +@itemx if rd s< imm32 goto disp16 Jump if signed lesser. -@item jsle %d,(%s|imm32),disp16 + +@item jsle rd, rs, disp16 +@itemx jsle rd, imm32, disp16 +@itemx if rd s<= rs goto disp16 +@itemx if rd s<= imm32 goto disp16 Jump if signed lesser or equal. @end table @@ -363,7 +582,8 @@ A call instruction is provided in order to perform calls to other eBPF functions, or to external kernel helpers: @table @code -@item call (disp32|imm32) +@item call disp32 +@item call imm32 Jump and link to the offset @emph{disp32}, or to the kernel helper function identified by @emph{imm32}. @end table @@ -375,203 +595,187 @@ Finally: Terminate the eBPF program. @end table -@subsubsection Atomic instructions +@subsection 32-bit jump instructions -Atomic exchange-and-add instructions are provided in two flavors: one -for swapping 64-bit quantities and another for 32-bit quantities. +eBPF provides the following compare-and-jump instructions, which +compare the 32-bit values of the two given registers, or the values of +a register and an immediate, and perform a branch in case the +comparison holds true. -@table @code -@item xadddw [%d+offset16],%s -Exchange-and-add a 64-bit value at the specified location. -@item xaddw [%d+offset16],%s -Exchange-and-add a 32-bit value at the specified location. -@end table +These instructions are only available in BPF v3 or later. -@node BPF Pseudo-C Syntax -@section BPF Pseudo-C Syntax +@table @code +@item jeq32 rd, rs, disp16 +@itemx jeq32 rd, imm32, disp16 +@itemx if rd == rs goto disp16 +@itemx if rd == imm32 goto disp16 +Jump if equal, unsigned. -This assembler supports another syntax to denote BPF instructions, -which is an alternative to the normal looking syntax documented above. -This alternatative syntax, which we call @dfn{pseudo-C syntax}, is -supported by the LLVM/clang integrated assembler. +@item jgt32 rd, rs, disp16 +@itemx jgt32 rd, imm32, disp16 +@itemx if rd > rs goto disp16 +@itemx if rd > imm32 goto disp16 +Jump if greater, unsigned. -This syntax is very unconventional, but we need to support it in order -to support inline assembly in existing BPF programs. +@item jge32 rd, rs, disp16 +@itemx jge32 rd, imm32, disp16 +@itemx if rd >= rs goto disp16 +@itemx if rd >= imm32 goto disp16 +Jump if greater or equal. -Note that the assembler is able to parse sources in which both -syntaxes coexist: some instructions can use the usual assembly like -syntax, whereas some other instructions in the same file can use the -pseudo-C syntax. +@item jlt32 rd, rs, disp16 +@itemx jlt32 rd, imm32, disp16 +@itemx if rd < rs goto disp16 +@itemx if rd < imm32 goto disp16 +Jump if lesser. -@subsubsection Pseudo-C Register Names +@item jle32 rd , rs, disp16 +@itemx jle32 rd, imm32, disp16 +@itemx if rd <= rs goto disp16 +@itemx if rd <= imm32 goto disp16 +Jump if lesser or equal. -All BPF registers are 64-bit long. However, in the Pseudo-C syntax -registers can be referred using different names, which actually -reflect the kind of instruction they appear on: +@item jset32 rd, rs, disp16 +@itemx jset32 rd, imm32, disp16 +@itemx if rd & rs goto disp16 +@itemx if rd & imm32 goto disp16 +Jump if signed equal. -@table @samp -@item r0..r9 -General-purpose register in an instruction that operates on its value -as if it was a 64-bit value. -@item w0..w9 -General-purpose register in an instruction that operates on its value -as if it was a 32-bit value. -@end table +@item jne32 rd, rs, disp16 +@itemx jne32 rd, imm32, disp16 +@itemx if rd != rs goto disp16 +@itemx if rd != imm32 goto disp16 +Jump if not equal. -@noindent -Note that in the Pseudo-C syntax register names are not preceded by -@code{%} characters. +@item jsgt32 rd, rs, disp16 +@itemx jsgt32 rd, imm32, disp16 +@itemx if rd s> rs goto disp16 +@itemx if rd s> imm32 goto disp16 +Jump if signed greater. -@subsubsection Arithmetic instructions +@item jsge32 rd, rs, disp16 +@itemx jsge32 rd, imm32, disp16 +@itemx if rd s>= rd goto disp16 +@itemx if rd s>= imm32 goto disp16 +Jump if signed greater or equal. -In all the instructions below, the operations are 64-bit or 32-bit -depending on the names used to refer to the registers. For example -@code{r3 += r2} will perform 64-bit addition, whereas @code{w3 += w2} -will perform 32-bit addition. Mixing register prefixes is an error, -for example @code{r3 += w2}. +@item jslt32 rd, rs, disp16 +@itemx jslt32 rd, imm32, disp16 +@itemx if rd s< rs goto disp16 +@itemx if rd s< imm32 goto disp16 +Jump if signed lesser. -@table @code -@item dst_reg += (imm32|src_reg) -Arithmetic addition. -@item dst_reg -= (imm32|src_reg) -Arithmetic subtraction. -@item dst_reg *= (imm32|src_reg) -Arithmetic multiplication. -@item dst_reg /= (imm32|src_reg) -Arithmetic integer unsigned division. -@item dst_reg %= (imm32|src_reg) -Arithmetic integer unsigned remainder. -@item dst_reg &= (imm32|src_reg) -Bit-wise ``and'' operation. -@item dst_reg |= (imm32|src_reg) -Bit-wise ``or'' operation. -@item dst_reg ^= (imm32|src_reg) -Bit-wise exclusive-or operation. -@item dst_reg <<= (imm32|src_reg) -Left shift, by whatever specified number of bits. -@item dst_reg >>= (imm32|src_reg) -Right logical shift, by whatever specified number of bits. -@item dst_reg s>>= (imm32|src_reg) -Right arithmetic shift, by whatever specified number of bits. -@item dst_reg = (imm32|src_reg) -Move the value in @code{imm32} or @code{src_reg} in @code{dst_reg}. -@item dst_reg = -dst_reg -Arithmetic negation. +@item jsle32 rd, rs, disp16 +@itemx jsle32 rd, imm32, disp16 +@itemx if rd s<= rs goto disp16 +@itemx if rd s<= imm32 goto disp16 +Jump if signed lesser or equal. @end table -@subsubsection Endianness conversion instructions +@subsection Atomic instructions + +Atomic exchange-and-add instructions are provided in two flavors: one +for swapping 64-bit quantities and another for 32-bit quantities. @table @code -@item dst_reg = le16 src_reg -Convert the 16-bit value in @code{src_reg} to little-endian. -@item dst_reg = le32 src_reg -Convert the 32-bit value in @code{src_reg} to little-endian. -@item dst_reg = le64 src_reg -Convert the 64-bit value in @code{src_reg} to little-endian. -@item dst_reg = be16 src_reg -Convert the 16-bit value in @code{src_reg} to big-endian. -@item dst_reg = be32 src_reg -Convert the 32-bit value in @code{src_reg} to big-endian. -@item dst_reg = be64 src_reg -Convert the 64-bit value in @code{src_reg} to big-endian. +@item aadd [rd + offset16], rs +@itemx *(u64 *)(rd + offset16) = rs +Atomic add instruction. + +@item aor [rd + offset16], rs +@itemx *(u64 *) (rd + offset16) |= rs +Atomic or instruction. + +@item aand [rd + offset16], rs +@itemx *(u64 *) (rd + offset16) &= rs +Atomic and instruction. + +@item axor [rd + offset16], rs +@itemx *(u64 *) (rd + offset16) ^= rs +Atomic xor instruction +@item xaddw [%d+offset16],%s +Exchange-and-add a 32-bit value at the specified location. @end table -@subsubsection 64-bit load and pseudo maps +@noindent +The following variants perform fetching before the atomic operation. @table @code -@item dst_reg = imm64 ll -Load the given signed 64-bit immediate, or pseudo map descriptor, to -the destination register @code{dst_reg}. +@item afadd [dr + offset16], rs +@itemx ??? +Atomic fetch-and-add instruction. + +@item afor [dr + offset16], rs +@itemx ??? +Atomic fetch-and-or instruction. + +@item afand [dr + offset16], rs +@itemx ??? +Atomic fetch-and-and instruction. + +@item afxor [dr + offset16], rs +@itemx ??? +Atomic fetch-and-or instruction @end table -@subsubsection Load instructions for socket filters +The above instructions were introduced in the V3 of the BPF +instruction set. The following instruction is supported for backwards +compatibility: @table @code -@item r0 = *(u8 *)skb[imm32] -Absolute 8-bit load. -@item r0 = *(u16 *)skb[imm32] -Absolute 16-bit load. -@item r0 = *(u32 *)skb[imm32] -Absolute 32-bit load. -@item r0 = *(u64 *)skb[imm32] -Absolute 64-bit load. -@item r0 = *(u8 *)skb[src_reg + imm32] -Indirect 8-bit load. -@item r0 = *(u16 *)skb[src_reg + imm32] -Indirect 16-bit load. -@item r0 = *(u32 *)skb[src_reg + imm32] -Indirect 32-bit load. -@item r0 = *(u64 *)skb[src_reg + imm32] -Indirect 64-bit load. +@item xadddw [rd + offset16], rs +Alias to @code{aadd}. @end table -@subsubsection Generic load/store instructions +@subsection 32-bit atomic instructions + +Atomic exchange-and-add instructions are provided in two flavors: one +for swapping 32-bit quantities and another for 32-bit quantities. @table @code -@item dst_reg = *(u8 *)(src_reg + offset16) -Generic 8-bit load. -@item dst_reg = *(u16 *)(src_reg + offset16) -Generic 16-bit load. -@item dst_reg = *(u32 *)(src_reg + offset16) -Generic 32-bit load. -@item dst_reg = *(u64 *)(src_reg + offset16) -Generic 64-bit load. -@c XXX stb -@c NO PSEUDOC-SYNTAX -@c XXX sth -@c NO PSEUDOC-SYNTAX -@c XXX stw -@c NO PSEUDOC-SYNTAX -@c XXX stdw -@c NO PSEUDOC-SYNTAX -@item *(u8 *)(dst_reg + offset16) = src_reg -Generic 8-bit store. -@item *(u16 *)(dst_reg + offset16) = src_reg -Generic 16-bit store. -@item *(u32 *)(dst_reg + offset16) = src_reg -Generic 32-bit store. -@item *(u64 *)(dst_reg + offset16) = src_reg -Generic 64-bit store. +@item aadd32 [rd + offset16], rs +@itemx *(u32 *)(rd + offset16) = rs +Atomic add instruction. + +@item aor32 [rd + offset16], rs +@itemx *(u32 *) (rd + offset16) |= rs +Atomic or instruction. + +@item aand32 [rd + offset16], rs +@itemx *(u32 *) (rd + offset16) &= rs +Atomic and instruction. + +@item axor32 [rd + offset16], rs +@itemx *(u32 *) (rd + offset16) ^= rs +Atomic xor instruction @end table -@subsubsection Jump instructions +@noindent +The following variants perform fetching before the atomic operation. @table @code -@item goto disp16 -Jump-always. -@item if dst_reg == (imm32|src_reg) goto disp16 -Jump if equal. -@item if dst_reg & (imm32|src_reg) goto disp16 -Jump if signed equal. -@item if dst_reg != (imm32|src_reg) goto disp16 -Jump if not equal. -@item if dst_reg > (imm32|src_reg) goto disp16 -Jump if bigger, unsigned. -@item if dst_reg < (imm32|src_reg) goto disp16 -Jump if smaller, unsigned. -@item if dst_reg >= (imm32|src_reg) goto disp16 -Jump if bigger or equal, unsigned. -@item if dst_reg <= (imm32|src_reg) goto disp16 -Jump if smaller or equal, unsigned. -@item if dst_reg s> (imm32|src_reg) goto disp16 -Jump if bigger, signed. -@item if dst_reg s< (imm32|src_reg) goto disp16 -Jump if smaller, signed. -@item if dst_reg s>= (imm32|src_reg) goto disp16 -Jump if bigger or equal, signed. -@item if dst_reg s<= (imm32|src_reg) goto disp16 -Jump if smaller or equal, signed. -@item call imm32 -Jump and link. -@item exit -Terminate the eBPF program. +@item afadd32 [dr + offset16], rs +@itemx ??? +Atomic fetch-and-add instruction. + +@item afor32 [dr + offset16], rs +@itemx ??? +Atomic fetch-and-or instruction. + +@item afand32 [dr + offset16], rs +@itemx ??? +Atomic fetch-and-and instruction. + +@item afxor32 [dr + offset16], rs +@itemx ??? +Atomic fetch-and-or instruction @end table -@subsubsection Atomic instructions +The above instructions were introduced in the V3 of the BPF +instruction set. The following instruction is supported for backwards +compatibility: @table @code -@item lock *(u64 *)(dst_reg + offset16) += src_reg -Exchange-and-add a 64-bit value at the specified location. -@item lock *(u32 *)(dst_reg + offset16) += src_reg -Exchange-and-add a 32-bit value at the specified location. +@item xaddw [rd + offset16], rs +Alias to @code{aadd32}. @end table diff --git a/gas/testsuite/gas/all/assign-bad-recursive.d b/gas/testsuite/gas/all/assign-bad-recursive.d index 678be3e..aeec5d5 100644 --- a/gas/testsuite/gas/all/assign-bad-recursive.d +++ b/gas/testsuite/gas/all/assign-bad-recursive.d @@ -1,5 +1,4 @@ #name: bad recursive assignments #source: assign-bad-recursive.s #xfail: bfin-*-* -#notarget: *bpf-*-* #error_output: assign-bad-recursive.l diff --git a/gas/testsuite/gas/all/eqv-dot.d b/gas/testsuite/gas/all/eqv-dot.d index d97db14..fc40b09 100644 --- a/gas/testsuite/gas/all/eqv-dot.d +++ b/gas/testsuite/gas/all/eqv-dot.d @@ -2,7 +2,7 @@ #name: eqv involving dot # bfin doesn't support 'symbol = expression' # tic30 and tic4x have 4 octets per byte, tic54x has 2 octets per byte -#notarget: bfin-*-* *c30-*-* *c4x-*-* *c54x-*-* *bpf-*-* +#notarget: bfin-*-* *c30-*-* *c4x-*-* *c54x-*-* # linkrelax targets don't handle equivalence expressions well (nor any # other forward expression). mep uses complex relocs #xfail: am33_2.0-*-* crx-*-* h8300-*-* mn10200-*-* mn10300-*-* mep-*-* diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp index bab5a6c..007408f 100644 --- a/gas/testsuite/gas/all/gas.exp +++ b/gas/testsuite/gas/all/gas.exp @@ -105,7 +105,7 @@ if { [istarget "pdp11-*-*"] } then { run_dump_test eqv-dot } -if { ![istarget "bfin-*-*"] && ![istarget "bpf-*-*"] } then { +if { ![istarget "bfin-*-*"] } then { gas_test "assign-ok.s" "" "" "== assignment support" } gas_test_error "assign-bad.s" "" "== assignment for symbol already set" @@ -403,8 +403,7 @@ if { ([istarget "i*86-*-*pe*"] && ![istarget "i*86-*-openbsd*"]) \ gas_test "fastcall.s" "" "" "fastcall labels" } -if { ![istarget "bfin-*-*"] && ![istarget "nds32*-*-*"] \ - && ![istarget "bpf-*-*"] } then { +if { ![istarget "bfin-*-*"] && ![istarget "nds32*-*-*"] } then { run_dump_test assign } run_dump_test sleb128 diff --git a/gas/testsuite/gas/bpf/alu-be-pseudoc.d b/gas/testsuite/gas/bpf/alu-be-pseudoc.d index 0355d19..8d8c29e 100644 --- a/gas/testsuite/gas/bpf/alu-be-pseudoc.d +++ b/gas/testsuite/gas/bpf/alu-be-pseudoc.d @@ -1,5 +1,65 @@ -#as: --EB +#as: -EB -mdialect=pseudoc #source: alu-pseudoc.s -#objdump: -dr -#dump: alu-be.dump +#objdump: -dr -M hex,pseudoc #name: eBPF ALU64 instructions, big endian, pseudoc syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 07 20 00 00 00 00 02 9a r2\+=0x29a + 8: 07 30 00 00 ff ff fd 66 r3\+=0xfffffd66 + 10: 07 40 00 00 7e ad be ef r4\+=0x7eadbeef + 18: 0f 56 00 00 00 00 00 00 r5\+=r6 + 20: 17 20 00 00 00 00 02 9a r2-=0x29a + 28: 17 30 00 00 ff ff fd 66 r3-=0xfffffd66 + 30: 17 40 00 00 7e ad be ef r4-=0x7eadbeef + 38: 1f 56 00 00 00 00 00 00 r5-=r6 + 40: 27 20 00 00 00 00 02 9a r2\*=0x29a + 48: 27 30 00 00 ff ff fd 66 r3\*=0xfffffd66 + 50: 27 40 00 00 7e ad be ef r4\*=0x7eadbeef + 58: 2f 56 00 00 00 00 00 00 r5\*=r6 + 60: 37 20 00 00 00 00 02 9a r2/=0x29a + 68: 37 30 00 00 ff ff fd 66 r3/=0xfffffd66 + 70: 37 40 00 00 7e ad be ef r4/=0x7eadbeef + 78: 3f 56 00 00 00 00 00 00 r5/=r6 + 80: 47 20 00 00 00 00 02 9a r2|=0x29a + 88: 47 30 00 00 ff ff fd 66 r3|=0xfffffd66 + 90: 47 40 00 00 7e ad be ef r4|=0x7eadbeef + 98: 4f 56 00 00 00 00 00 00 r5|=r6 + a0: 57 20 00 00 00 00 02 9a r2&=0x29a + a8: 57 30 00 00 ff ff fd 66 r3&=0xfffffd66 + b0: 57 40 00 00 7e ad be ef r4&=0x7eadbeef + b8: 5f 56 00 00 00 00 00 00 r5&=r6 + c0: 67 20 00 00 00 00 02 9a r2<<=0x29a + c8: 67 30 00 00 ff ff fd 66 r3<<=0xfffffd66 + d0: 67 40 00 00 7e ad be ef r4<<=0x7eadbeef + d8: 6f 56 00 00 00 00 00 00 r5<<=r6 + e0: 77 20 00 00 00 00 02 9a r2>>=0x29a + e8: 77 30 00 00 ff ff fd 66 r3>>=0xfffffd66 + f0: 77 40 00 00 7e ad be ef r4>>=0x7eadbeef + f8: 7f 56 00 00 00 00 00 00 r5>>=r6 + 100: 97 20 00 00 00 00 02 9a r2%=0x29a + 108: 97 30 00 00 ff ff fd 66 r3%=0xfffffd66 + 110: 97 40 00 00 7e ad be ef r4%=0x7eadbeef + 118: 9f 56 00 00 00 00 00 00 r5%=r6 + 120: a7 20 00 00 00 00 02 9a r2\^=0x29a + 128: a7 30 00 00 ff ff fd 66 r3\^=0xfffffd66 + 130: a7 40 00 00 7e ad be ef r4\^=0x7eadbeef + 138: af 56 00 00 00 00 00 00 r5\^=r6 + 140: b7 20 00 00 00 00 02 9a r2=0x29a + 148: b7 30 00 00 ff ff fd 66 r3=0xfffffd66 + 150: b7 40 00 00 7e ad be ef r4=0x7eadbeef + 158: bf 56 00 00 00 00 00 00 r5=r6 + 160: c7 20 00 00 00 00 02 9a r2 s>>=0x29a + 168: c7 30 00 00 ff ff fd 66 r3 s>>=0xfffffd66 + 170: c7 40 00 00 7e ad be ef r4 s>>=0x7eadbeef + 178: cf 56 00 00 00 00 00 00 r5 s>>=r6 + 180: 8f 23 00 00 00 00 00 00 r2=-r3 + 188: d4 90 00 00 00 00 00 10 r9=le16 r9 + 190: d4 80 00 00 00 00 00 20 r8=le32 r8 + 198: d4 70 00 00 00 00 00 40 r7=le64 r7 + 1a0: dc 60 00 00 00 00 00 10 r6=be16 r6 + 1a8: dc 50 00 00 00 00 00 20 r5=be32 r5 + 1b0: dc 40 00 00 00 00 00 40 r4=be64 r4 diff --git a/gas/testsuite/gas/bpf/alu-be.d b/gas/testsuite/gas/bpf/alu-be.d index afd2a6c..170db4b 100644 --- a/gas/testsuite/gas/bpf/alu-be.d +++ b/gas/testsuite/gas/bpf/alu-be.d @@ -1,5 +1,65 @@ -#as: --EB +#as: -EB -mdialect=normal #source: alu.s -#objdump: -dr -#dump: alu-be.dump -#name: eBPF ALU64 instructions, big endian, normal syntax +#objdump: -dr -M hex +#name: eBPF ALU instructions, big endian, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 07 20 00 00 00 00 02 9a add %r2,0x29a + 8: 07 30 00 00 ff ff fd 66 add %r3,0xfffffd66 + 10: 07 40 00 00 7e ad be ef add %r4,0x7eadbeef + 18: 0f 56 00 00 00 00 00 00 add %r5,%r6 + 20: 17 20 00 00 00 00 02 9a sub %r2,0x29a + 28: 17 30 00 00 ff ff fd 66 sub %r3,0xfffffd66 + 30: 17 40 00 00 7e ad be ef sub %r4,0x7eadbeef + 38: 1f 56 00 00 00 00 00 00 sub %r5,%r6 + 40: 27 20 00 00 00 00 02 9a mul %r2,0x29a + 48: 27 30 00 00 ff ff fd 66 mul %r3,0xfffffd66 + 50: 27 40 00 00 7e ad be ef mul %r4,0x7eadbeef + 58: 2f 56 00 00 00 00 00 00 mul %r5,%r6 + 60: 37 20 00 00 00 00 02 9a div %r2,0x29a + 68: 37 30 00 00 ff ff fd 66 div %r3,0xfffffd66 + 70: 37 40 00 00 7e ad be ef div %r4,0x7eadbeef + 78: 3f 56 00 00 00 00 00 00 div %r5,%r6 + 80: 47 20 00 00 00 00 02 9a or %r2,0x29a + 88: 47 30 00 00 ff ff fd 66 or %r3,0xfffffd66 + 90: 47 40 00 00 7e ad be ef or %r4,0x7eadbeef + 98: 4f 56 00 00 00 00 00 00 or %r5,%r6 + a0: 57 20 00 00 00 00 02 9a and %r2,0x29a + a8: 57 30 00 00 ff ff fd 66 and %r3,0xfffffd66 + b0: 57 40 00 00 7e ad be ef and %r4,0x7eadbeef + b8: 5f 56 00 00 00 00 00 00 and %r5,%r6 + c0: 67 20 00 00 00 00 02 9a lsh %r2,0x29a + c8: 67 30 00 00 ff ff fd 66 lsh %r3,0xfffffd66 + d0: 67 40 00 00 7e ad be ef lsh %r4,0x7eadbeef + d8: 6f 56 00 00 00 00 00 00 lsh %r5,%r6 + e0: 77 20 00 00 00 00 02 9a rsh %r2,0x29a + e8: 77 30 00 00 ff ff fd 66 rsh %r3,0xfffffd66 + f0: 77 40 00 00 7e ad be ef rsh %r4,0x7eadbeef + f8: 7f 56 00 00 00 00 00 00 rsh %r5,%r6 + 100: 97 20 00 00 00 00 02 9a mod %r2,0x29a + 108: 97 30 00 00 ff ff fd 66 mod %r3,0xfffffd66 + 110: 97 40 00 00 7e ad be ef mod %r4,0x7eadbeef + 118: 9f 56 00 00 00 00 00 00 mod %r5,%r6 + 120: a7 20 00 00 00 00 02 9a xor %r2,0x29a + 128: a7 30 00 00 ff ff fd 66 xor %r3,0xfffffd66 + 130: a7 40 00 00 7e ad be ef xor %r4,0x7eadbeef + 138: af 56 00 00 00 00 00 00 xor %r5,%r6 + 140: b7 20 00 00 00 00 02 9a mov %r2,0x29a + 148: b7 30 00 00 ff ff fd 66 mov %r3,0xfffffd66 + 150: b7 40 00 00 7e ad be ef mov %r4,0x7eadbeef + 158: bf 56 00 00 00 00 00 00 mov %r5,%r6 + 160: c7 20 00 00 00 00 02 9a arsh %r2,0x29a + 168: c7 30 00 00 ff ff fd 66 arsh %r3,0xfffffd66 + 170: c7 40 00 00 7e ad be ef arsh %r4,0x7eadbeef + 178: cf 56 00 00 00 00 00 00 arsh %r5,%r6 + 180: 8f 23 00 00 00 00 00 00 neg %r2,%r3 + 188: d4 90 00 00 00 00 00 10 endle %r9,16 + 190: d4 80 00 00 00 00 00 20 endle %r8,32 + 198: d4 70 00 00 00 00 00 40 endle %r7,64 + 1a0: dc 60 00 00 00 00 00 10 endbe %r6,16 + 1a8: dc 50 00 00 00 00 00 20 endbe %r5,32 + 1b0: dc 40 00 00 00 00 00 40 endbe %r4,64 diff --git a/gas/testsuite/gas/bpf/alu-be.dump b/gas/testsuite/gas/bpf/alu-be.dump deleted file mode 100644 index d4a6f35..0000000 --- a/gas/testsuite/gas/bpf/alu-be.dump +++ /dev/null @@ -1,54 +0,0 @@ -.*: +file format .*bpf.* - -Disassembly of section .text: - -0+ <.text>: - 0: 07 20 00 00 00 00 02 9a add %r2,0x29a - 8: 07 30 00 00 ff ff fd 66 add %r3,-666 - 10: 07 40 00 00 7e ad be ef add %r4,0x7eadbeef - 18: 0f 56 00 00 00 00 00 00 add %r5,%r6 - 20: 17 20 00 00 00 00 02 9a sub %r2,0x29a - 28: 17 30 00 00 ff ff fd 66 sub %r3,-666 - 30: 17 40 00 00 7e ad be ef sub %r4,0x7eadbeef - 38: 1f 56 00 00 00 00 00 00 sub %r5,%r6 - 40: 27 20 00 00 00 00 02 9a mul %r2,0x29a - 48: 27 30 00 00 ff ff fd 66 mul %r3,-666 - 50: 27 40 00 00 7e ad be ef mul %r4,0x7eadbeef - 58: 2f 56 00 00 00 00 00 00 mul %r5,%r6 - 60: 37 20 00 00 00 00 02 9a div %r2,0x29a - 68: 37 30 00 00 ff ff fd 66 div %r3,-666 - 70: 37 40 00 00 7e ad be ef div %r4,0x7eadbeef - 78: 3f 56 00 00 00 00 00 00 div %r5,%r6 - 80: 47 20 00 00 00 00 02 9a or %r2,0x29a - 88: 47 30 00 00 ff ff fd 66 or %r3,-666 - 90: 47 40 00 00 7e ad be ef or %r4,0x7eadbeef - 98: 4f 56 00 00 00 00 00 00 or %r5,%r6 - a0: 57 20 00 00 00 00 02 9a and %r2,0x29a - a8: 57 30 00 00 ff ff fd 66 and %r3,-666 - b0: 57 40 00 00 7e ad be ef and %r4,0x7eadbeef - b8: 5f 56 00 00 00 00 00 00 and %r5,%r6 - c0: 67 20 00 00 00 00 02 9a lsh %r2,0x29a - c8: 67 30 00 00 ff ff fd 66 lsh %r3,-666 - d0: 67 40 00 00 7e ad be ef lsh %r4,0x7eadbeef - d8: 6f 56 00 00 00 00 00 00 lsh %r5,%r6 - e0: 77 20 00 00 00 00 02 9a rsh %r2,0x29a - e8: 77 30 00 00 ff ff fd 66 rsh %r3,-666 - f0: 77 40 00 00 7e ad be ef rsh %r4,0x7eadbeef - f8: 7f 56 00 00 00 00 00 00 rsh %r5,%r6 - 100: 97 20 00 00 00 00 02 9a mod %r2,0x29a - 108: 97 30 00 00 ff ff fd 66 mod %r3,-666 - 110: 97 40 00 00 7e ad be ef mod %r4,0x7eadbeef - 118: 9f 56 00 00 00 00 00 00 mod %r5,%r6 - 120: a7 20 00 00 00 00 02 9a xor %r2,0x29a - 128: a7 30 00 00 ff ff fd 66 xor %r3,-666 - 130: a7 40 00 00 7e ad be ef xor %r4,0x7eadbeef - 138: af 56 00 00 00 00 00 00 xor %r5,%r6 - 140: b7 20 00 00 00 00 02 9a mov %r2,0x29a - 148: b7 30 00 00 ff ff fd 66 mov %r3,-666 - 150: b7 40 00 00 7e ad be ef mov %r4,0x7eadbeef - 158: bf 56 00 00 00 00 00 00 mov %r5,%r6 - 160: c7 20 00 00 00 00 02 9a arsh %r2,0x29a - 168: c7 30 00 00 ff ff fd 66 arsh %r3,-666 - 170: c7 40 00 00 7e ad be ef arsh %r4,0x7eadbeef - 178: cf 56 00 00 00 00 00 00 arsh %r5,%r6 - 180: 87 20 00 00 00 00 00 00 neg %r2 diff --git a/gas/testsuite/gas/bpf/alu-pseudoc.d b/gas/testsuite/gas/bpf/alu-pseudoc.d index df13069..5d69e68 100644 --- a/gas/testsuite/gas/bpf/alu-pseudoc.d +++ b/gas/testsuite/gas/bpf/alu-pseudoc.d @@ -1,5 +1,65 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=pseudoc +#objdump: -dr -M hex,pseudoc #source: alu-pseudoc.s -#dump: alu.dump -#name: eBPF ALU64 instructions, pseudo-c syntax +#name: eBPF ALU instructions, pseudo-c syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 07 02 00 00 9a 02 00 00 r2\+=0x29a + 8: 07 03 00 00 66 fd ff ff r3\+=0xfffffd66 + 10: 07 04 00 00 ef be ad 7e r4\+=0x7eadbeef + 18: 0f 65 00 00 00 00 00 00 r5\+=r6 + 20: 17 02 00 00 9a 02 00 00 r2-=0x29a + 28: 17 03 00 00 66 fd ff ff r3-=0xfffffd66 + 30: 17 04 00 00 ef be ad 7e r4-=0x7eadbeef + 38: 1f 65 00 00 00 00 00 00 r5-=r6 + 40: 27 02 00 00 9a 02 00 00 r2\*=0x29a + 48: 27 03 00 00 66 fd ff ff r3\*=0xfffffd66 + 50: 27 04 00 00 ef be ad 7e r4\*=0x7eadbeef + 58: 2f 65 00 00 00 00 00 00 r5\*=r6 + 60: 37 02 00 00 9a 02 00 00 r2/=0x29a + 68: 37 03 00 00 66 fd ff ff r3/=0xfffffd66 + 70: 37 04 00 00 ef be ad 7e r4/=0x7eadbeef + 78: 3f 65 00 00 00 00 00 00 r5/=r6 + 80: 47 02 00 00 9a 02 00 00 r2|=0x29a + 88: 47 03 00 00 66 fd ff ff r3|=0xfffffd66 + 90: 47 04 00 00 ef be ad 7e r4|=0x7eadbeef + 98: 4f 65 00 00 00 00 00 00 r5|=r6 + a0: 57 02 00 00 9a 02 00 00 r2&=0x29a + a8: 57 03 00 00 66 fd ff ff r3&=0xfffffd66 + b0: 57 04 00 00 ef be ad 7e r4&=0x7eadbeef + b8: 5f 65 00 00 00 00 00 00 r5&=r6 + c0: 67 02 00 00 9a 02 00 00 r2<<=0x29a + c8: 67 03 00 00 66 fd ff ff r3<<=0xfffffd66 + d0: 67 04 00 00 ef be ad 7e r4<<=0x7eadbeef + d8: 6f 65 00 00 00 00 00 00 r5<<=r6 + e0: 77 02 00 00 9a 02 00 00 r2>>=0x29a + e8: 77 03 00 00 66 fd ff ff r3>>=0xfffffd66 + f0: 77 04 00 00 ef be ad 7e r4>>=0x7eadbeef + f8: 7f 65 00 00 00 00 00 00 r5>>=r6 + 100: 97 02 00 00 9a 02 00 00 r2%=0x29a + 108: 97 03 00 00 66 fd ff ff r3%=0xfffffd66 + 110: 97 04 00 00 ef be ad 7e r4%=0x7eadbeef + 118: 9f 65 00 00 00 00 00 00 r5%=r6 + 120: a7 02 00 00 9a 02 00 00 r2\^=0x29a + 128: a7 03 00 00 66 fd ff ff r3\^=0xfffffd66 + 130: a7 04 00 00 ef be ad 7e r4\^=0x7eadbeef + 138: af 65 00 00 00 00 00 00 r5\^=r6 + 140: b7 02 00 00 9a 02 00 00 r2=0x29a + 148: b7 03 00 00 66 fd ff ff r3=0xfffffd66 + 150: b7 04 00 00 ef be ad 7e r4=0x7eadbeef + 158: bf 65 00 00 00 00 00 00 r5=r6 + 160: c7 02 00 00 9a 02 00 00 r2 s>>=0x29a + 168: c7 03 00 00 66 fd ff ff r3 s>>=0xfffffd66 + 170: c7 04 00 00 ef be ad 7e r4 s>>=0x7eadbeef + 178: cf 65 00 00 00 00 00 00 r5 s>>=r6 + 180: 8f 32 00 00 00 00 00 00 r2=-r3 + 188: d4 09 00 00 10 00 00 00 r9=le16 r9 + 190: d4 08 00 00 20 00 00 00 r8=le32 r8 + 198: d4 07 00 00 40 00 00 00 r7=le64 r7 + 1a0: dc 06 00 00 10 00 00 00 r6=be16 r6 + 1a8: dc 05 00 00 20 00 00 00 r5=be32 r5 + 1b0: dc 04 00 00 40 00 00 00 r4=be64 r4 diff --git a/gas/testsuite/gas/bpf/alu-pseudoc.s b/gas/testsuite/gas/bpf/alu-pseudoc.s index 0f79929..a271bef 100644 --- a/gas/testsuite/gas/bpf/alu-pseudoc.s +++ b/gas/testsuite/gas/bpf/alu-pseudoc.s @@ -48,4 +48,10 @@ r3 s>>= -666 r4 s>>= 2125315823 r5 s>>= r6 - r2 = -r2 + r2 = - r3 + r9 = le16 r9 + r8 = le32 r8 + r7 = le64 r7 + r6 = be16 r6 + r5 = be32 r5 + r4 = be64 r4 diff --git a/gas/testsuite/gas/bpf/alu-xbpf.d b/gas/testsuite/gas/bpf/alu-xbpf.d deleted file mode 100644 index 7f97d49..0000000 --- a/gas/testsuite/gas/bpf/alu-xbpf.d +++ /dev/null @@ -1,17 +0,0 @@ -#as: --EL -mxbpf -#objdump: -dr -mxbpf -#name: xBPF ALU64 insns - -.*: +file format .*bpf.* - -Disassembly of section \.text: - -0+ <\.text>: - 0: e7 02 00 00 02 00 00 00 sdiv %r2,2 - 8: e7 03 00 00 fd ff ff ff sdiv %r3,-3 - 10: e7 04 00 00 ef be ad 7e sdiv %r4,0x7eadbeef - 18: ef 25 00 00 00 00 00 00 sdiv %r5,%r2 - 20: f7 02 00 00 03 00 00 00 smod %r2,3 - 28: f7 03 00 00 fc ff ff ff smod %r3,-4 - 30: f7 04 00 00 ef be ad 7e smod %r4,0x7eadbeef - 38: ff 25 00 00 00 00 00 00 smod %r5,%r2 diff --git a/gas/testsuite/gas/bpf/alu-xbpf.s b/gas/testsuite/gas/bpf/alu-xbpf.s deleted file mode 100644 index ebcebd7..0000000 --- a/gas/testsuite/gas/bpf/alu-xbpf.s +++ /dev/null @@ -1,11 +0,0 @@ - # Tests for xBPF-specific alu instructions - .text - sdiv %r2, 2 - sdiv %r3, -3 - sdiv %r4, 0x7eadbeef - sdiv %r5, %r2 - - smod %r2, 3 - smod %r3, -4 - smod %r4, 0x7eadbeef - smod %r5, %r2 diff --git a/gas/testsuite/gas/bpf/alu.d b/gas/testsuite/gas/bpf/alu.d index 764ae44..476891b 100644 --- a/gas/testsuite/gas/bpf/alu.d +++ b/gas/testsuite/gas/bpf/alu.d @@ -1,5 +1,65 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=normal +#objdump: -dr -M hex #source: alu.s -#dump: alu.dump -#name: eBPF ALU64 instructions, normal syntax +#name: eBPF ALU instructions, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 07 02 00 00 9a 02 00 00 add %r2,0x29a + 8: 07 03 00 00 66 fd ff ff add %r3,0xfffffd66 + 10: 07 04 00 00 ef be ad 7e add %r4,0x7eadbeef + 18: 0f 65 00 00 00 00 00 00 add %r5,%r6 + 20: 17 02 00 00 9a 02 00 00 sub %r2,0x29a + 28: 17 03 00 00 66 fd ff ff sub %r3,0xfffffd66 + 30: 17 04 00 00 ef be ad 7e sub %r4,0x7eadbeef + 38: 1f 65 00 00 00 00 00 00 sub %r5,%r6 + 40: 27 02 00 00 9a 02 00 00 mul %r2,0x29a + 48: 27 03 00 00 66 fd ff ff mul %r3,0xfffffd66 + 50: 27 04 00 00 ef be ad 7e mul %r4,0x7eadbeef + 58: 2f 65 00 00 00 00 00 00 mul %r5,%r6 + 60: 37 02 00 00 9a 02 00 00 div %r2,0x29a + 68: 37 03 00 00 66 fd ff ff div %r3,0xfffffd66 + 70: 37 04 00 00 ef be ad 7e div %r4,0x7eadbeef + 78: 3f 65 00 00 00 00 00 00 div %r5,%r6 + 80: 47 02 00 00 9a 02 00 00 or %r2,0x29a + 88: 47 03 00 00 66 fd ff ff or %r3,0xfffffd66 + 90: 47 04 00 00 ef be ad 7e or %r4,0x7eadbeef + 98: 4f 65 00 00 00 00 00 00 or %r5,%r6 + a0: 57 02 00 00 9a 02 00 00 and %r2,0x29a + a8: 57 03 00 00 66 fd ff ff and %r3,0xfffffd66 + b0: 57 04 00 00 ef be ad 7e and %r4,0x7eadbeef + b8: 5f 65 00 00 00 00 00 00 and %r5,%r6 + c0: 67 02 00 00 9a 02 00 00 lsh %r2,0x29a + c8: 67 03 00 00 66 fd ff ff lsh %r3,0xfffffd66 + d0: 67 04 00 00 ef be ad 7e lsh %r4,0x7eadbeef + d8: 6f 65 00 00 00 00 00 00 lsh %r5,%r6 + e0: 77 02 00 00 9a 02 00 00 rsh %r2,0x29a + e8: 77 03 00 00 66 fd ff ff rsh %r3,0xfffffd66 + f0: 77 04 00 00 ef be ad 7e rsh %r4,0x7eadbeef + f8: 7f 65 00 00 00 00 00 00 rsh %r5,%r6 + 100: 97 02 00 00 9a 02 00 00 mod %r2,0x29a + 108: 97 03 00 00 66 fd ff ff mod %r3,0xfffffd66 + 110: 97 04 00 00 ef be ad 7e mod %r4,0x7eadbeef + 118: 9f 65 00 00 00 00 00 00 mod %r5,%r6 + 120: a7 02 00 00 9a 02 00 00 xor %r2,0x29a + 128: a7 03 00 00 66 fd ff ff xor %r3,0xfffffd66 + 130: a7 04 00 00 ef be ad 7e xor %r4,0x7eadbeef + 138: af 65 00 00 00 00 00 00 xor %r5,%r6 + 140: b7 02 00 00 9a 02 00 00 mov %r2,0x29a + 148: b7 03 00 00 66 fd ff ff mov %r3,0xfffffd66 + 150: b7 04 00 00 ef be ad 7e mov %r4,0x7eadbeef + 158: bf 65 00 00 00 00 00 00 mov %r5,%r6 + 160: c7 02 00 00 9a 02 00 00 arsh %r2,0x29a + 168: c7 03 00 00 66 fd ff ff arsh %r3,0xfffffd66 + 170: c7 04 00 00 ef be ad 7e arsh %r4,0x7eadbeef + 178: cf 65 00 00 00 00 00 00 arsh %r5,%r6 + 180: 8f 32 00 00 00 00 00 00 neg %r2,%r3 + 188: d4 09 00 00 10 00 00 00 endle %r9,16 + 190: d4 08 00 00 20 00 00 00 endle %r8,32 + 198: d4 07 00 00 40 00 00 00 endle %r7,64 + 1a0: dc 06 00 00 10 00 00 00 endbe %r6,16 + 1a8: dc 05 00 00 20 00 00 00 endbe %r5,32 + 1b0: dc 04 00 00 40 00 00 00 endbe %r4,64 diff --git a/gas/testsuite/gas/bpf/alu.dump b/gas/testsuite/gas/bpf/alu.dump deleted file mode 100644 index 2acc947..0000000 --- a/gas/testsuite/gas/bpf/alu.dump +++ /dev/null @@ -1,54 +0,0 @@ -.*: +file format .*bpf.* - -Disassembly of section .text: - -0+ <.text>: - 0: 07 02 00 00 9a 02 00 00 add %r2,0x29a - 8: 07 03 00 00 66 fd ff ff add %r3,-666 - 10: 07 04 00 00 ef be ad 7e add %r4,0x7eadbeef - 18: 0f 65 00 00 00 00 00 00 add %r5,%r6 - 20: 17 02 00 00 9a 02 00 00 sub %r2,0x29a - 28: 17 03 00 00 66 fd ff ff sub %r3,-666 - 30: 17 04 00 00 ef be ad 7e sub %r4,0x7eadbeef - 38: 1f 65 00 00 00 00 00 00 sub %r5,%r6 - 40: 27 02 00 00 9a 02 00 00 mul %r2,0x29a - 48: 27 03 00 00 66 fd ff ff mul %r3,-666 - 50: 27 04 00 00 ef be ad 7e mul %r4,0x7eadbeef - 58: 2f 65 00 00 00 00 00 00 mul %r5,%r6 - 60: 37 02 00 00 9a 02 00 00 div %r2,0x29a - 68: 37 03 00 00 66 fd ff ff div %r3,-666 - 70: 37 04 00 00 ef be ad 7e div %r4,0x7eadbeef - 78: 3f 65 00 00 00 00 00 00 div %r5,%r6 - 80: 47 02 00 00 9a 02 00 00 or %r2,0x29a - 88: 47 03 00 00 66 fd ff ff or %r3,-666 - 90: 47 04 00 00 ef be ad 7e or %r4,0x7eadbeef - 98: 4f 65 00 00 00 00 00 00 or %r5,%r6 - a0: 57 02 00 00 9a 02 00 00 and %r2,0x29a - a8: 57 03 00 00 66 fd ff ff and %r3,-666 - b0: 57 04 00 00 ef be ad 7e and %r4,0x7eadbeef - b8: 5f 65 00 00 00 00 00 00 and %r5,%r6 - c0: 67 02 00 00 9a 02 00 00 lsh %r2,0x29a - c8: 67 03 00 00 66 fd ff ff lsh %r3,-666 - d0: 67 04 00 00 ef be ad 7e lsh %r4,0x7eadbeef - d8: 6f 65 00 00 00 00 00 00 lsh %r5,%r6 - e0: 77 02 00 00 9a 02 00 00 rsh %r2,0x29a - e8: 77 03 00 00 66 fd ff ff rsh %r3,-666 - f0: 77 04 00 00 ef be ad 7e rsh %r4,0x7eadbeef - f8: 7f 65 00 00 00 00 00 00 rsh %r5,%r6 - 100: 97 02 00 00 9a 02 00 00 mod %r2,0x29a - 108: 97 03 00 00 66 fd ff ff mod %r3,-666 - 110: 97 04 00 00 ef be ad 7e mod %r4,0x7eadbeef - 118: 9f 65 00 00 00 00 00 00 mod %r5,%r6 - 120: a7 02 00 00 9a 02 00 00 xor %r2,0x29a - 128: a7 03 00 00 66 fd ff ff xor %r3,-666 - 130: a7 04 00 00 ef be ad 7e xor %r4,0x7eadbeef - 138: af 65 00 00 00 00 00 00 xor %r5,%r6 - 140: b7 02 00 00 9a 02 00 00 mov %r2,0x29a - 148: b7 03 00 00 66 fd ff ff mov %r3,-666 - 150: b7 04 00 00 ef be ad 7e mov %r4,0x7eadbeef - 158: bf 65 00 00 00 00 00 00 mov %r5,%r6 - 160: c7 02 00 00 9a 02 00 00 arsh %r2,0x29a - 168: c7 03 00 00 66 fd ff ff arsh %r3,-666 - 170: c7 04 00 00 ef be ad 7e arsh %r4,0x7eadbeef - 178: cf 65 00 00 00 00 00 00 arsh %r5,%r6 - 180: 87 02 00 00 00 00 00 00 neg %r2 diff --git a/gas/testsuite/gas/bpf/alu.s b/gas/testsuite/gas/bpf/alu.s index 18e60d5..bb3f926 100644 --- a/gas/testsuite/gas/bpf/alu.s +++ b/gas/testsuite/gas/bpf/alu.s @@ -48,4 +48,10 @@ arsh %r3, -666 arsh %r4, 0x7eadbeef arsh %r5, %r6 - neg %r2 + neg %r2, %r3 + endle %r9,16 + endle %r8,32 + endle %r7,64 + endbe %r6,16 + endbe %r5,32 + endbe %r4,64 diff --git a/gas/testsuite/gas/bpf/alu32-be-pseudoc.d b/gas/testsuite/gas/bpf/alu32-be-pseudoc.d index 396d7d4..6daad3b 100644 --- a/gas/testsuite/gas/bpf/alu32-be-pseudoc.d +++ b/gas/testsuite/gas/bpf/alu32-be-pseudoc.d @@ -1,5 +1,59 @@ -#as: --EB -#objdump: -dr +#as: -EB -mdialect=pseudoc +#objdump: -dr -M hex,pseudoc #source: alu32-pseudoc.s -#dump: alu32-be.dump -#name: eBPF ALU instructions, big-endian, pseudo-c syntax +#name: eBPF ALU32 instructions, big-endian, pseudo-c syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 04 20 00 00 00 00 02 9a w2\+=0x29a + 8: 04 30 00 00 ff ff fd 66 w3\+=0xfffffd66 + 10: 04 40 00 00 7e ad be ef w4\+=0x7eadbeef + 18: 0c 56 00 00 00 00 00 00 w5\+=w6 + 20: 14 20 00 00 00 00 02 9a w2-=0x29a + 28: 14 30 00 00 ff ff fd 66 w3-=0xfffffd66 + 30: 14 40 00 00 7e ad be ef w4-=0x7eadbeef + 38: 1c 56 00 00 00 00 00 00 w5-=w6 + 40: 24 20 00 00 00 00 02 9a w2\*=0x29a + 48: 24 30 00 00 ff ff fd 66 w3\*=0xfffffd66 + 50: 24 40 00 00 7e ad be ef w4\*=0x7eadbeef + 58: 2c 56 00 00 00 00 00 00 w5\*=w6 + 60: 34 20 00 00 00 00 02 9a w2/=0x29a + 68: 34 30 00 00 ff ff fd 66 w3/=0xfffffd66 + 70: 34 40 00 00 7e ad be ef w4/=0x7eadbeef + 78: 3c 56 00 00 00 00 00 00 w5/=w6 + 80: 44 20 00 00 00 00 02 9a w2|=0x29a + 88: 44 30 00 00 ff ff fd 66 w3|=0xfffffd66 + 90: 44 40 00 00 7e ad be ef w4|=0x7eadbeef + 98: 4c 56 00 00 00 00 00 00 w5|=w6 + a0: 54 20 00 00 00 00 02 9a w2&=0x29a + a8: 54 30 00 00 ff ff fd 66 w3&=0xfffffd66 + b0: 54 40 00 00 7e ad be ef w4&=0x7eadbeef + b8: 5c 56 00 00 00 00 00 00 w5&=w6 + c0: 64 20 00 00 00 00 02 9a w2<<=0x29a + c8: 64 30 00 00 ff ff fd 66 w3<<=0xfffffd66 + d0: 64 40 00 00 7e ad be ef w4<<=0x7eadbeef + d8: 6c 56 00 00 00 00 00 00 w5<<=w6 + e0: 74 20 00 00 00 00 02 9a w2>>=0x29a + e8: 74 30 00 00 ff ff fd 66 w3>>=0xfffffd66 + f0: 74 40 00 00 7e ad be ef w4>>=0x7eadbeef + f8: 7c 56 00 00 00 00 00 00 w5>>=w6 + 100: 94 20 00 00 00 00 02 9a w2%=0x29a + 108: 94 30 00 00 ff ff fd 66 w3%=0xfffffd66 + 110: 94 40 00 00 7e ad be ef w4%=0x7eadbeef + 118: 9c 56 00 00 00 00 00 00 w5%=w6 + 120: a4 20 00 00 00 00 02 9a w2\^=0x29a + 128: a4 30 00 00 ff ff fd 66 w3\^=0xfffffd66 + 130: a4 40 00 00 7e ad be ef w4\^=0x7eadbeef + 138: ac 56 00 00 00 00 00 00 w5\^=w6 + 140: b4 20 00 00 00 00 02 9a w2=0x29a + 148: b4 30 00 00 ff ff fd 66 w3=0xfffffd66 + 150: b4 40 00 00 7e ad be ef w4=0x7eadbeef + 158: bc 56 00 00 00 00 00 00 w5=w6 + 160: c4 20 00 00 00 00 02 9a w2 s>>=0x29a + 168: c4 30 00 00 ff ff fd 66 w3 s>>=0xfffffd66 + 170: c4 40 00 00 7e ad be ef w4 s>>=0x7eadbeef + 178: cc 56 00 00 00 00 00 00 w5 s>>=w6 + 180: 8c 23 00 00 00 00 00 00 w2=-w3 diff --git a/gas/testsuite/gas/bpf/alu32-be.d b/gas/testsuite/gas/bpf/alu32-be.d index 6ed9e55..6de8f06 100644 --- a/gas/testsuite/gas/bpf/alu32-be.d +++ b/gas/testsuite/gas/bpf/alu32-be.d @@ -1,5 +1,59 @@ -#as: --EB -#objdump: -dr -#source: alu32-pseudoc.s -#dump: alu32-be.dump -#name: eBPF ALU instructions, big-endian, normal syntax +#as: -EB -mdialect=normal +#objdump: -dr -M hex +#source: alu32.s +#name: eBPF ALU32 instructions, big-endian, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 04 20 00 00 00 00 02 9a add32 %r2,0x29a + 8: 04 30 00 00 ff ff fd 66 add32 %r3,0xfffffd66 + 10: 04 40 00 00 7e ad be ef add32 %r4,0x7eadbeef + 18: 0c 56 00 00 00 00 00 00 add32 %r5,%r6 + 20: 14 20 00 00 00 00 02 9a sub32 %r2,0x29a + 28: 14 30 00 00 ff ff fd 66 sub32 %r3,0xfffffd66 + 30: 14 40 00 00 7e ad be ef sub32 %r4,0x7eadbeef + 38: 1c 56 00 00 00 00 00 00 sub32 %r5,%r6 + 40: 24 20 00 00 00 00 02 9a mul32 %r2,0x29a + 48: 24 30 00 00 ff ff fd 66 mul32 %r3,0xfffffd66 + 50: 24 40 00 00 7e ad be ef mul32 %r4,0x7eadbeef + 58: 2c 56 00 00 00 00 00 00 mul32 %r5,%r6 + 60: 34 20 00 00 00 00 02 9a div32 %r2,0x29a + 68: 34 30 00 00 ff ff fd 66 div32 %r3,0xfffffd66 + 70: 34 40 00 00 7e ad be ef div32 %r4,0x7eadbeef + 78: 3c 56 00 00 00 00 00 00 div32 %r5,%r6 + 80: 44 20 00 00 00 00 02 9a or32 %r2,0x29a + 88: 44 30 00 00 ff ff fd 66 or32 %r3,0xfffffd66 + 90: 44 40 00 00 7e ad be ef or32 %r4,0x7eadbeef + 98: 4c 56 00 00 00 00 00 00 or32 %r5,%r6 + a0: 54 20 00 00 00 00 02 9a and32 %r2,0x29a + a8: 54 30 00 00 ff ff fd 66 and32 %r3,0xfffffd66 + b0: 54 40 00 00 7e ad be ef and32 %r4,0x7eadbeef + b8: 5c 56 00 00 00 00 00 00 and32 %r5,%r6 + c0: 64 20 00 00 00 00 02 9a lsh32 %r2,0x29a + c8: 64 30 00 00 ff ff fd 66 lsh32 %r3,0xfffffd66 + d0: 64 40 00 00 7e ad be ef lsh32 %r4,0x7eadbeef + d8: 6c 56 00 00 00 00 00 00 lsh32 %r5,%r6 + e0: 74 20 00 00 00 00 02 9a rsh32 %r2,0x29a + e8: 74 30 00 00 ff ff fd 66 rsh32 %r3,0xfffffd66 + f0: 74 40 00 00 7e ad be ef rsh32 %r4,0x7eadbeef + f8: 7c 56 00 00 00 00 00 00 rsh32 %r5,%r6 + 100: 94 20 00 00 00 00 02 9a mod32 %r2,0x29a + 108: 94 30 00 00 ff ff fd 66 mod32 %r3,0xfffffd66 + 110: 94 40 00 00 7e ad be ef mod32 %r4,0x7eadbeef + 118: 9c 56 00 00 00 00 00 00 mod32 %r5,%r6 + 120: a4 20 00 00 00 00 02 9a xor32 %r2,0x29a + 128: a4 30 00 00 ff ff fd 66 xor32 %r3,0xfffffd66 + 130: a4 40 00 00 7e ad be ef xor32 %r4,0x7eadbeef + 138: ac 56 00 00 00 00 00 00 xor32 %r5,%r6 + 140: b4 20 00 00 00 00 02 9a mov32 %r2,0x29a + 148: b4 30 00 00 ff ff fd 66 mov32 %r3,0xfffffd66 + 150: b4 40 00 00 7e ad be ef mov32 %r4,0x7eadbeef + 158: bc 56 00 00 00 00 00 00 mov32 %r5,%r6 + 160: c4 20 00 00 00 00 02 9a arsh32 %r2,0x29a + 168: c4 30 00 00 ff ff fd 66 arsh32 %r3,0xfffffd66 + 170: c4 40 00 00 7e ad be ef arsh32 %r4,0x7eadbeef + 178: cc 56 00 00 00 00 00 00 arsh32 %r5,%r6 + 180: 8c 23 00 00 00 00 00 00 neg32 %r2,%r3 diff --git a/gas/testsuite/gas/bpf/alu32-be.dump b/gas/testsuite/gas/bpf/alu32-be.dump deleted file mode 100644 index a224267..0000000 --- a/gas/testsuite/gas/bpf/alu32-be.dump +++ /dev/null @@ -1,60 +0,0 @@ -.*: +file format .*bpf.* - -Disassembly of section .text: - -0+ <.text>: - 0: 04 20 00 00 00 00 02 9a add32 %r2,0x29a - 8: 04 30 00 00 ff ff fd 66 add32 %r3,-666 - 10: 04 40 00 00 7e ad be ef add32 %r4,0x7eadbeef - 18: 0c 56 00 00 00 00 00 00 add32 %r5,%r6 - 20: 14 20 00 00 00 00 02 9a sub32 %r2,0x29a - 28: 14 30 00 00 ff ff fd 66 sub32 %r3,-666 - 30: 14 40 00 00 7e ad be ef sub32 %r4,0x7eadbeef - 38: 1c 56 00 00 00 00 00 00 sub32 %r5,%r6 - 40: 24 20 00 00 00 00 02 9a mul32 %r2,0x29a - 48: 24 30 00 00 ff ff fd 66 mul32 %r3,-666 - 50: 24 40 00 00 7e ad be ef mul32 %r4,0x7eadbeef - 58: 2c 56 00 00 00 00 00 00 mul32 %r5,%r6 - 60: 34 20 00 00 00 00 02 9a div32 %r2,0x29a - 68: 34 30 00 00 ff ff fd 66 div32 %r3,-666 - 70: 34 40 00 00 7e ad be ef div32 %r4,0x7eadbeef - 78: 3c 56 00 00 00 00 00 00 div32 %r5,%r6 - 80: 44 20 00 00 00 00 02 9a or32 %r2,0x29a - 88: 44 30 00 00 ff ff fd 66 or32 %r3,-666 - 90: 44 40 00 00 7e ad be ef or32 %r4,0x7eadbeef - 98: 4c 56 00 00 00 00 00 00 or32 %r5,%r6 - a0: 54 20 00 00 00 00 02 9a and32 %r2,0x29a - a8: 54 30 00 00 ff ff fd 66 and32 %r3,-666 - b0: 54 40 00 00 7e ad be ef and32 %r4,0x7eadbeef - b8: 5c 56 00 00 00 00 00 00 and32 %r5,%r6 - c0: 64 20 00 00 00 00 02 9a lsh32 %r2,0x29a - c8: 64 30 00 00 ff ff fd 66 lsh32 %r3,-666 - d0: 64 40 00 00 7e ad be ef lsh32 %r4,0x7eadbeef - d8: 6c 56 00 00 00 00 00 00 lsh32 %r5,%r6 - e0: 74 20 00 00 00 00 02 9a rsh32 %r2,0x29a - e8: 74 30 00 00 ff ff fd 66 rsh32 %r3,-666 - f0: 74 40 00 00 7e ad be ef rsh32 %r4,0x7eadbeef - f8: 7c 56 00 00 00 00 00 00 rsh32 %r5,%r6 - 100: 94 20 00 00 00 00 02 9a mod32 %r2,0x29a - 108: 94 30 00 00 ff ff fd 66 mod32 %r3,-666 - 110: 94 40 00 00 7e ad be ef mod32 %r4,0x7eadbeef - 118: 9c 56 00 00 00 00 00 00 mod32 %r5,%r6 - 120: a4 20 00 00 00 00 02 9a xor32 %r2,0x29a - 128: a4 30 00 00 ff ff fd 66 xor32 %r3,-666 - 130: a4 40 00 00 7e ad be ef xor32 %r4,0x7eadbeef - 138: ac 56 00 00 00 00 00 00 xor32 %r5,%r6 - 140: b4 20 00 00 00 00 02 9a mov32 %r2,0x29a - 148: b4 30 00 00 ff ff fd 66 mov32 %r3,-666 - 150: b4 40 00 00 7e ad be ef mov32 %r4,0x7eadbeef - 158: bc 56 00 00 00 00 00 00 mov32 %r5,%r6 - 160: c4 20 00 00 00 00 02 9a arsh32 %r2,0x29a - 168: c4 30 00 00 ff ff fd 66 arsh32 %r3,-666 - 170: c4 40 00 00 7e ad be ef arsh32 %r4,0x7eadbeef - 178: cc 56 00 00 00 00 00 00 arsh32 %r5,%r6 - 180: 84 20 00 00 00 00 00 00 neg32 %r2 - 188: d4 90 00 00 00 00 00 10 endle %r9,16 - 190: d4 80 00 00 00 00 00 20 endle %r8,32 - 198: d4 70 00 00 00 00 00 40 endle %r7,64 - 1a0: dc 60 00 00 00 00 00 10 endbe %r6,16 - 1a8: dc 50 00 00 00 00 00 20 endbe %r5,32 - 1b0: dc 40 00 00 00 00 00 40 endbe %r4,64 diff --git a/gas/testsuite/gas/bpf/alu32-pseudoc.d b/gas/testsuite/gas/bpf/alu32-pseudoc.d index 98b9921..f339c80 100644 --- a/gas/testsuite/gas/bpf/alu32-pseudoc.d +++ b/gas/testsuite/gas/bpf/alu32-pseudoc.d @@ -1,5 +1,59 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=pseudoc +#objdump: -dr -M hex,pseudoc #source: alu32-pseudoc.s -#dump: alu32.dump -#name: eBPF ALU instructions, pseudo-c syntax +#name: eBPF ALU32 instructions, pseudo-c syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 04 02 00 00 9a 02 00 00 w2\+=0x29a + 8: 04 03 00 00 66 fd ff ff w3\+=0xfffffd66 + 10: 04 04 00 00 ef be ad 7e w4\+=0x7eadbeef + 18: 0c 65 00 00 00 00 00 00 w5\+=w6 + 20: 14 02 00 00 9a 02 00 00 w2-=0x29a + 28: 14 03 00 00 66 fd ff ff w3-=0xfffffd66 + 30: 14 04 00 00 ef be ad 7e w4-=0x7eadbeef + 38: 1c 65 00 00 00 00 00 00 w5-=w6 + 40: 24 02 00 00 9a 02 00 00 w2\*=0x29a + 48: 24 03 00 00 66 fd ff ff w3\*=0xfffffd66 + 50: 24 04 00 00 ef be ad 7e w4\*=0x7eadbeef + 58: 2c 65 00 00 00 00 00 00 w5\*=w6 + 60: 34 02 00 00 9a 02 00 00 w2/=0x29a + 68: 34 03 00 00 66 fd ff ff w3/=0xfffffd66 + 70: 34 04 00 00 ef be ad 7e w4/=0x7eadbeef + 78: 3c 65 00 00 00 00 00 00 w5/=w6 + 80: 44 02 00 00 9a 02 00 00 w2|=0x29a + 88: 44 03 00 00 66 fd ff ff w3|=0xfffffd66 + 90: 44 04 00 00 ef be ad 7e w4|=0x7eadbeef + 98: 4c 65 00 00 00 00 00 00 w5|=w6 + a0: 54 02 00 00 9a 02 00 00 w2&=0x29a + a8: 54 03 00 00 66 fd ff ff w3&=0xfffffd66 + b0: 54 04 00 00 ef be ad 7e w4&=0x7eadbeef + b8: 5c 65 00 00 00 00 00 00 w5&=w6 + c0: 64 02 00 00 9a 02 00 00 w2<<=0x29a + c8: 64 03 00 00 66 fd ff ff w3<<=0xfffffd66 + d0: 64 04 00 00 ef be ad 7e w4<<=0x7eadbeef + d8: 6c 65 00 00 00 00 00 00 w5<<=w6 + e0: 74 02 00 00 9a 02 00 00 w2>>=0x29a + e8: 74 03 00 00 66 fd ff ff w3>>=0xfffffd66 + f0: 74 04 00 00 ef be ad 7e w4>>=0x7eadbeef + f8: 7c 65 00 00 00 00 00 00 w5>>=w6 + 100: 94 02 00 00 9a 02 00 00 w2%=0x29a + 108: 94 03 00 00 66 fd ff ff w3%=0xfffffd66 + 110: 94 04 00 00 ef be ad 7e w4%=0x7eadbeef + 118: 9c 65 00 00 00 00 00 00 w5%=w6 + 120: a4 02 00 00 9a 02 00 00 w2\^=0x29a + 128: a4 03 00 00 66 fd ff ff w3\^=0xfffffd66 + 130: a4 04 00 00 ef be ad 7e w4\^=0x7eadbeef + 138: ac 65 00 00 00 00 00 00 w5\^=w6 + 140: b4 02 00 00 9a 02 00 00 w2=0x29a + 148: b4 03 00 00 66 fd ff ff w3=0xfffffd66 + 150: b4 04 00 00 ef be ad 7e w4=0x7eadbeef + 158: bc 65 00 00 00 00 00 00 w5=w6 + 160: c4 02 00 00 9a 02 00 00 w2 s>>=0x29a + 168: c4 03 00 00 66 fd ff ff w3 s>>=0xfffffd66 + 170: c4 04 00 00 ef be ad 7e w4 s>>=0x7eadbeef + 178: cc 65 00 00 00 00 00 00 w5 s>>=w6 + 180: 8c 32 00 00 00 00 00 00 w2=-w3 diff --git a/gas/testsuite/gas/bpf/alu32-pseudoc.s b/gas/testsuite/gas/bpf/alu32-pseudoc.s index a29f6ea..0a0d41f 100644 --- a/gas/testsuite/gas/bpf/alu32-pseudoc.s +++ b/gas/testsuite/gas/bpf/alu32-pseudoc.s @@ -1,16 +1,16 @@ # Tests for the ALU eBPF pseudo-C instructions .text - W2 += 666 - W3 += -666 - W4 += 2125315823 - W5 += w6 - W2 -= 666 - W3 -= -666 - W4 -= 2125315823 - W5 -= w6 - W2 *= 666 - W3 *= -666 - W4 *= 2125315823 + w2 += 666 + w3 += -666 + w4 += 2125315823 + w5 += w6 + w2 -= 666 + w3 -= -666 + w4 -= 2125315823 + w5 -= w6 + w2 *= 666 + w3 *= -666 + w4 *= 2125315823 w5 *= w6 w2 /= 666 w3 /= -666 @@ -48,10 +48,4 @@ w3 s>>= -666 w4 s>>= 2125315823 w5 s>>= w6 - w2 = -w2 - r9 = le16 r9 - r8 = le32 r8 - r7 = le64 r7 - r6 = be16 r6 - r5 = be32 r5 - r4 = be64 r4 + w2 = - w3 diff --git a/gas/testsuite/gas/bpf/alu32-xbpf.d b/gas/testsuite/gas/bpf/alu32-xbpf.d deleted file mode 100644 index 03411d6..0000000 --- a/gas/testsuite/gas/bpf/alu32-xbpf.d +++ /dev/null @@ -1,17 +0,0 @@ -#as: --EL -mxbpf -#objdump: -dr -mxbpf -#name: xBPF ALU32 insns - -.*: +file format .*bpf.* - -Disassembly of section \.text: - -0+ <\.text>: - 0: e4 02 00 00 02 00 00 00 sdiv32 %r2,2 - 8: e4 03 00 00 fd ff ff ff sdiv32 %r3,-3 - 10: e4 04 00 00 ef be ad 7e sdiv32 %r4,0x7eadbeef - 18: ec 25 00 00 00 00 00 00 sdiv32 %r5,%r2 - 20: f4 02 00 00 03 00 00 00 smod32 %r2,3 - 28: f4 03 00 00 fc ff ff ff smod32 %r3,-4 - 30: f4 04 00 00 ef be ad 7e smod32 %r4,0x7eadbeef - 38: fc 25 00 00 00 00 00 00 smod32 %r5,%r2 diff --git a/gas/testsuite/gas/bpf/alu32-xbpf.s b/gas/testsuite/gas/bpf/alu32-xbpf.s deleted file mode 100644 index 9ce5a26..0000000 --- a/gas/testsuite/gas/bpf/alu32-xbpf.s +++ /dev/null @@ -1,11 +0,0 @@ - # Tests for xBPF-specific alu instructions - .text - sdiv32 %r2, 2 - sdiv32 %r3, -3 - sdiv32 %r4, 0x7eadbeef - sdiv32 %r5, %r2 - - smod32 %r2, 3 - smod32 %r3, -4 - smod32 %r4, 0x7eadbeef - smod32 %r5, %r2 diff --git a/gas/testsuite/gas/bpf/alu32.d b/gas/testsuite/gas/bpf/alu32.d index 87efc20..712d1c7 100644 --- a/gas/testsuite/gas/bpf/alu32.d +++ b/gas/testsuite/gas/bpf/alu32.d @@ -1,5 +1,59 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=normal +#objdump: -dr -M hex #source: alu32.s -#dump: alu32.dump -#name: eBPF ALU instructions, normal syntax +#name: eBPF ALU32 instructions, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 04 02 00 00 9a 02 00 00 add32 %r2,0x29a + 8: 04 03 00 00 66 fd ff ff add32 %r3,0xfffffd66 + 10: 04 04 00 00 ef be ad 7e add32 %r4,0x7eadbeef + 18: 0c 65 00 00 00 00 00 00 add32 %r5,%r6 + 20: 14 02 00 00 9a 02 00 00 sub32 %r2,0x29a + 28: 14 03 00 00 66 fd ff ff sub32 %r3,0xfffffd66 + 30: 14 04 00 00 ef be ad 7e sub32 %r4,0x7eadbeef + 38: 1c 65 00 00 00 00 00 00 sub32 %r5,%r6 + 40: 24 02 00 00 9a 02 00 00 mul32 %r2,0x29a + 48: 24 03 00 00 66 fd ff ff mul32 %r3,0xfffffd66 + 50: 24 04 00 00 ef be ad 7e mul32 %r4,0x7eadbeef + 58: 2c 65 00 00 00 00 00 00 mul32 %r5,%r6 + 60: 34 02 00 00 9a 02 00 00 div32 %r2,0x29a + 68: 34 03 00 00 66 fd ff ff div32 %r3,0xfffffd66 + 70: 34 04 00 00 ef be ad 7e div32 %r4,0x7eadbeef + 78: 3c 65 00 00 00 00 00 00 div32 %r5,%r6 + 80: 44 02 00 00 9a 02 00 00 or32 %r2,0x29a + 88: 44 03 00 00 66 fd ff ff or32 %r3,0xfffffd66 + 90: 44 04 00 00 ef be ad 7e or32 %r4,0x7eadbeef + 98: 4c 65 00 00 00 00 00 00 or32 %r5,%r6 + a0: 54 02 00 00 9a 02 00 00 and32 %r2,0x29a + a8: 54 03 00 00 66 fd ff ff and32 %r3,0xfffffd66 + b0: 54 04 00 00 ef be ad 7e and32 %r4,0x7eadbeef + b8: 5c 65 00 00 00 00 00 00 and32 %r5,%r6 + c0: 64 02 00 00 9a 02 00 00 lsh32 %r2,0x29a + c8: 64 03 00 00 66 fd ff ff lsh32 %r3,0xfffffd66 + d0: 64 04 00 00 ef be ad 7e lsh32 %r4,0x7eadbeef + d8: 6c 65 00 00 00 00 00 00 lsh32 %r5,%r6 + e0: 74 02 00 00 9a 02 00 00 rsh32 %r2,0x29a + e8: 74 03 00 00 66 fd ff ff rsh32 %r3,0xfffffd66 + f0: 74 04 00 00 ef be ad 7e rsh32 %r4,0x7eadbeef + f8: 7c 65 00 00 00 00 00 00 rsh32 %r5,%r6 + 100: 94 02 00 00 9a 02 00 00 mod32 %r2,0x29a + 108: 94 03 00 00 66 fd ff ff mod32 %r3,0xfffffd66 + 110: 94 04 00 00 ef be ad 7e mod32 %r4,0x7eadbeef + 118: 9c 65 00 00 00 00 00 00 mod32 %r5,%r6 + 120: a4 02 00 00 9a 02 00 00 xor32 %r2,0x29a + 128: a4 03 00 00 66 fd ff ff xor32 %r3,0xfffffd66 + 130: a4 04 00 00 ef be ad 7e xor32 %r4,0x7eadbeef + 138: ac 65 00 00 00 00 00 00 xor32 %r5,%r6 + 140: b4 02 00 00 9a 02 00 00 mov32 %r2,0x29a + 148: b4 03 00 00 66 fd ff ff mov32 %r3,0xfffffd66 + 150: b4 04 00 00 ef be ad 7e mov32 %r4,0x7eadbeef + 158: bc 65 00 00 00 00 00 00 mov32 %r5,%r6 + 160: c4 02 00 00 9a 02 00 00 arsh32 %r2,0x29a + 168: c4 03 00 00 66 fd ff ff arsh32 %r3,0xfffffd66 + 170: c4 04 00 00 ef be ad 7e arsh32 %r4,0x7eadbeef + 178: cc 65 00 00 00 00 00 00 arsh32 %r5,%r6 + 180: 8c 32 00 00 00 00 00 00 neg32 %r2,%r3 diff --git a/gas/testsuite/gas/bpf/alu32.dump b/gas/testsuite/gas/bpf/alu32.dump deleted file mode 100644 index 223f74f..0000000 --- a/gas/testsuite/gas/bpf/alu32.dump +++ /dev/null @@ -1,60 +0,0 @@ -.*: +file format .*bpf.* - -Disassembly of section .text: - -0+ <.text>: - 0: 04 02 00 00 9a 02 00 00 add32 %r2,0x29a - 8: 04 03 00 00 66 fd ff ff add32 %r3,-666 - 10: 04 04 00 00 ef be ad 7e add32 %r4,0x7eadbeef - 18: 0c 65 00 00 00 00 00 00 add32 %r5,%r6 - 20: 14 02 00 00 9a 02 00 00 sub32 %r2,0x29a - 28: 14 03 00 00 66 fd ff ff sub32 %r3,-666 - 30: 14 04 00 00 ef be ad 7e sub32 %r4,0x7eadbeef - 38: 1c 65 00 00 00 00 00 00 sub32 %r5,%r6 - 40: 24 02 00 00 9a 02 00 00 mul32 %r2,0x29a - 48: 24 03 00 00 66 fd ff ff mul32 %r3,-666 - 50: 24 04 00 00 ef be ad 7e mul32 %r4,0x7eadbeef - 58: 2c 65 00 00 00 00 00 00 mul32 %r5,%r6 - 60: 34 02 00 00 9a 02 00 00 div32 %r2,0x29a - 68: 34 03 00 00 66 fd ff ff div32 %r3,-666 - 70: 34 04 00 00 ef be ad 7e div32 %r4,0x7eadbeef - 78: 3c 65 00 00 00 00 00 00 div32 %r5,%r6 - 80: 44 02 00 00 9a 02 00 00 or32 %r2,0x29a - 88: 44 03 00 00 66 fd ff ff or32 %r3,-666 - 90: 44 04 00 00 ef be ad 7e or32 %r4,0x7eadbeef - 98: 4c 65 00 00 00 00 00 00 or32 %r5,%r6 - a0: 54 02 00 00 9a 02 00 00 and32 %r2,0x29a - a8: 54 03 00 00 66 fd ff ff and32 %r3,-666 - b0: 54 04 00 00 ef be ad 7e and32 %r4,0x7eadbeef - b8: 5c 65 00 00 00 00 00 00 and32 %r5,%r6 - c0: 64 02 00 00 9a 02 00 00 lsh32 %r2,0x29a - c8: 64 03 00 00 66 fd ff ff lsh32 %r3,-666 - d0: 64 04 00 00 ef be ad 7e lsh32 %r4,0x7eadbeef - d8: 6c 65 00 00 00 00 00 00 lsh32 %r5,%r6 - e0: 74 02 00 00 9a 02 00 00 rsh32 %r2,0x29a - e8: 74 03 00 00 66 fd ff ff rsh32 %r3,-666 - f0: 74 04 00 00 ef be ad 7e rsh32 %r4,0x7eadbeef - f8: 7c 65 00 00 00 00 00 00 rsh32 %r5,%r6 - 100: 94 02 00 00 9a 02 00 00 mod32 %r2,0x29a - 108: 94 03 00 00 66 fd ff ff mod32 %r3,-666 - 110: 94 04 00 00 ef be ad 7e mod32 %r4,0x7eadbeef - 118: 9c 65 00 00 00 00 00 00 mod32 %r5,%r6 - 120: a4 02 00 00 9a 02 00 00 xor32 %r2,0x29a - 128: a4 03 00 00 66 fd ff ff xor32 %r3,-666 - 130: a4 04 00 00 ef be ad 7e xor32 %r4,0x7eadbeef - 138: ac 65 00 00 00 00 00 00 xor32 %r5,%r6 - 140: b4 02 00 00 9a 02 00 00 mov32 %r2,0x29a - 148: b4 03 00 00 66 fd ff ff mov32 %r3,-666 - 150: b4 04 00 00 ef be ad 7e mov32 %r4,0x7eadbeef - 158: bc 65 00 00 00 00 00 00 mov32 %r5,%r6 - 160: c4 02 00 00 9a 02 00 00 arsh32 %r2,0x29a - 168: c4 03 00 00 66 fd ff ff arsh32 %r3,-666 - 170: c4 04 00 00 ef be ad 7e arsh32 %r4,0x7eadbeef - 178: cc 65 00 00 00 00 00 00 arsh32 %r5,%r6 - 180: 84 02 00 00 00 00 00 00 neg32 %r2 - 188: d4 09 00 00 10 00 00 00 endle %r9,16 - 190: d4 08 00 00 20 00 00 00 endle %r8,32 - 198: d4 07 00 00 40 00 00 00 endle %r7,64 - 1a0: dc 06 00 00 10 00 00 00 endbe %r6,16 - 1a8: dc 05 00 00 20 00 00 00 endbe %r5,32 - 1b0: dc 04 00 00 40 00 00 00 endbe %r4,64 diff --git a/gas/testsuite/gas/bpf/alu32.s b/gas/testsuite/gas/bpf/alu32.s index 7b6f014..f43ea4a 100644 --- a/gas/testsuite/gas/bpf/alu32.s +++ b/gas/testsuite/gas/bpf/alu32.s @@ -48,10 +48,4 @@ arsh32 %r3, -666 arsh32 %r4, 0x7eadbeef arsh32 %r5, %r6 - neg32 %r2 - endle %r9,16 - endle %r8,32 - endle %r7,64 - endbe %r6,16 - endbe %r5,32 - endbe %r4,64 + neg32 %r2, %r3 diff --git a/gas/testsuite/gas/bpf/atomic-be-pseudoc.d b/gas/testsuite/gas/bpf/atomic-be-pseudoc.d new file mode 100644 index 0000000..a57322e --- /dev/null +++ b/gas/testsuite/gas/bpf/atomic-be-pseudoc.d @@ -0,0 +1,12 @@ +#as: -EB -mdialect=pseudoc +#objdump: -dr -M hex,pseudoc +#source: atomic-pseudoc.s +#name: eBPF atomic instructions, pseudoc syntax, big endian + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: db 12 1e ef 00 00 00 00 \*\(u64\*\)\(r1\+0x1eef\)\+=r2 + 8: c3 12 1e ef 00 00 00 00 \*\(u32\*\)\(r1\+0x1eef\)\+=r2 diff --git a/gas/testsuite/gas/bpf/atomic-be.d b/gas/testsuite/gas/bpf/atomic-be.d index b252571..fa81d8f 100644 --- a/gas/testsuite/gas/bpf/atomic-be.d +++ b/gas/testsuite/gas/bpf/atomic-be.d @@ -1,7 +1,6 @@ -#as: --EB +#as: -EB -mdialect=normal #source: atomic.s -#source: atomic-pseudoc.s -#objdump: -dr +#objdump: -dr -M hex,v1 #name: eBPF atomic instructions, big endian .*: +file format .*bpf.* diff --git a/gas/testsuite/gas/bpf/atomic-pseudoc.d b/gas/testsuite/gas/bpf/atomic-pseudoc.d index 3b0e5c5..3aafd47 100644 --- a/gas/testsuite/gas/bpf/atomic-pseudoc.d +++ b/gas/testsuite/gas/bpf/atomic-pseudoc.d @@ -1,5 +1,12 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=pseudoc +#objdump: -dr -M hex,pseudoc #source: atomic-pseudoc.s -#dump: atomic.dump -#name: eBPF atomic instructions, normal syntax +#name: eBPF atomic instructions, pseudoc syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: db 21 ef 1e 00 00 00 00 \*\(u64\*\)\(r1\+0x1eef\)\+=r2 + 8: c3 21 ef 1e 00 00 00 00 \*\(u32\*\)\(r1\+0x1eef\)\+=r2 diff --git a/gas/testsuite/gas/bpf/atomic-pseudoc.s b/gas/testsuite/gas/bpf/atomic-pseudoc.s index 1a4f218..ac73cad 100644 --- a/gas/testsuite/gas/bpf/atomic-pseudoc.s +++ b/gas/testsuite/gas/bpf/atomic-pseudoc.s @@ -1,4 +1,4 @@ # Test for eBPF ADDW and ADDDW pseudo-C instructions .text - lock *(u64 *)(r1 + 7919) += r2 - lock *(u32 *)(r1 + 7919) += r2 + *(u64 *)(r1 + 7919) += r2 + *(u32 *)(r1 + 7919) += r2 diff --git a/gas/testsuite/gas/bpf/atomic.d b/gas/testsuite/gas/bpf/atomic.d index c48ba9a..0a27cae 100644 --- a/gas/testsuite/gas/bpf/atomic.d +++ b/gas/testsuite/gas/bpf/atomic.d @@ -1,5 +1,12 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=normal +#objdump: -dr -M hex #source: atomic.s -#dump: atomic.dump #name: eBPF atomic instructions, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: db 21 ef 1e 00 00 00 00 aadd \[%r1\+0x1eef\],%r2 + 8: c3 21 ef 1e 00 00 00 00 aadd32 \[%r1\+0x1eef\],%r2 diff --git a/gas/testsuite/gas/bpf/atomic.dump b/gas/testsuite/gas/bpf/atomic.dump deleted file mode 100644 index 45dd25b..0000000 --- a/gas/testsuite/gas/bpf/atomic.dump +++ /dev/null @@ -1,7 +0,0 @@ -.*: +file format .*bpf.* - -Disassembly of section .text: - -0+ <.text>: - 0: db 21 ef 1e 00 00 00 00 xadddw \[%r1\+0x1eef\],%r2 - 8: c3 21 ef 1e 00 00 00 00 xaddw \[%r1\+0x1eef\],%r2 diff --git a/gas/testsuite/gas/bpf/atomic.s b/gas/testsuite/gas/bpf/atomic.s index 0119b24..4669f4a 100644 --- a/gas/testsuite/gas/bpf/atomic.s +++ b/gas/testsuite/gas/bpf/atomic.s @@ -1,5 +1,5 @@ # Test for eBPF ADDW and ADDDW instructions .text - xadddw [%r1+0x1eef], %r2 - xaddw [%r1+0x1eef], %r2 + aadd [%r1+0x1eef], %r2 + aadd32 [%r1+0x1eef], %r2 diff --git a/gas/testsuite/gas/bpf/bpf.exp b/gas/testsuite/gas/bpf/bpf.exp index 5d91805..adf413f 100644 --- a/gas/testsuite/gas/bpf/bpf.exp +++ b/gas/testsuite/gas/bpf/bpf.exp @@ -18,6 +18,10 @@ # Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. if {[istarget bpf*-*-*]} { + # Little-endian BPF tests + run_dump_test call + run_dump_test exit + run_dump_test data run_dump_test lddw run_dump_test lddw-pseudoc run_dump_test alu @@ -30,13 +34,15 @@ if {[istarget bpf*-*-*]} { run_dump_test jump-pseudoc run_dump_test jump32 run_dump_test jump32-pseudoc - run_dump_test call - run_dump_test exit run_dump_test atomic run_dump_test atomic-pseudoc - run_dump_test data - run_dump_test pseudoc-normal + run_dump_test indcall-1 + run_dump_test indcall-1-pseudoc + # Big-endian BPF tests + run_dump_test call-be + run_dump_test exit-be + run_dump_test data-be run_dump_test lddw-be run_dump_test lddw-be-pseudoc run_dump_test alu-be @@ -44,17 +50,11 @@ if {[istarget bpf*-*-*]} { run_dump_test alu32-be run_dump_test alu32-be-pseudoc run_dump_test mem-be + run_dump_test mem-be-pseudoc run_dump_test jump-be - run_dump_test call-be - run_dump_test exit-be + run_dump_test jump-be-pseudoc + run_dump_test jump32-be + run_dump_test jump32-be-pseudoc run_dump_test atomic-be - run_dump_test data-be - run_dump_test pseudoc-normal-be - - run_dump_test indcall-1 - run_dump_test indcall-1-pseudoc - run_list_test indcall-bad-1 - - run_dump_test alu-xbpf - run_dump_test alu32-xbpf + run_dump_test atomic-be-pseudoc } diff --git a/gas/testsuite/gas/bpf/call-be.d b/gas/testsuite/gas/bpf/call-be.d index bd3b50f..55e4e70 100644 --- a/gas/testsuite/gas/bpf/call-be.d +++ b/gas/testsuite/gas/bpf/call-be.d @@ -1,6 +1,6 @@ -#as: --EB +#as: -EB -mdialect=normal #source: call.s -#objdump: -dr +#objdump: -dr -M dec #name: eBPF CALL instruction, big endian .*: +file format .*bpf.* diff --git a/gas/testsuite/gas/bpf/call.d b/gas/testsuite/gas/bpf/call.d index daefbd0..a85cb7f 100644 --- a/gas/testsuite/gas/bpf/call.d +++ b/gas/testsuite/gas/bpf/call.d @@ -1,5 +1,5 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=normal +#objdump: -dr -M dec #name: eBPF CALL instruction .*: +file format .*bpf.* diff --git a/gas/testsuite/gas/bpf/data-be.d b/gas/testsuite/gas/bpf/data-be.d index 010f08f..3a8b68b 100644 --- a/gas/testsuite/gas/bpf/data-be.d +++ b/gas/testsuite/gas/bpf/data-be.d @@ -1,4 +1,4 @@ -#as: --EB +#as: -EB -mdialect=normal #source: data.s #objdump: -s -j .data #name: eBPF data directives, big endian diff --git a/gas/testsuite/gas/bpf/data.d b/gas/testsuite/gas/bpf/data.d index 6824e8b..9fa108b6 100644 --- a/gas/testsuite/gas/bpf/data.d +++ b/gas/testsuite/gas/bpf/data.d @@ -1,4 +1,4 @@ -#as: --EL +#as: -EL -mdialect=normal #objdump: -s -j .data #name: eBPF data directives diff --git a/gas/testsuite/gas/bpf/exit-be.d b/gas/testsuite/gas/bpf/exit-be.d index d3b88c7..b83af3e 100644 --- a/gas/testsuite/gas/bpf/exit-be.d +++ b/gas/testsuite/gas/bpf/exit-be.d @@ -1,6 +1,6 @@ -#as: --EB +#as: -EB -mdialect=normal #source: exit.s -#objdump: -dr +#objdump: -dr -M hex #name: eBPF EXIT instruction, big endian .*: +file format .*bpf.* diff --git a/gas/testsuite/gas/bpf/exit.d b/gas/testsuite/gas/bpf/exit.d index 87bc91b..68ef902 100644 --- a/gas/testsuite/gas/bpf/exit.d +++ b/gas/testsuite/gas/bpf/exit.d @@ -1,5 +1,5 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=normal +#objdump: -dr -M hex #name: eBPF EXIT instruction .*: +file format .*bpf.* diff --git a/gas/testsuite/gas/bpf/indcall-1-pseudoc.d b/gas/testsuite/gas/bpf/indcall-1-pseudoc.d index b04e656..7a95bad 100644 --- a/gas/testsuite/gas/bpf/indcall-1-pseudoc.d +++ b/gas/testsuite/gas/bpf/indcall-1-pseudoc.d @@ -1,5 +1,23 @@ -#as: -mxbpf --EL -#objdump: -mxbpf -dr +#as: -EL -mdialect=pseudoc -misa-spec=xbpf +#objdump: -M xbpf,pseudoc,dec -dr #source: indcall-1-pseudoc.s -#dump: indcall-1.dump #name: BPF indirect call 1, pseudoc syntax + +.*: +file format .*bpf.* + +Disassembly of section \.text: + +0000000000000000 <main>: + 0: b7 00 00 00 01 00 00 00 r0=1 + 8: b7 01 00 00 01 00 00 00 r1=1 + 10: b7 02 00 00 02 00 00 00 r2=2 + 18: 18 06 00 00 38 00 00 00 r6=56 ll + 20: 00 00 00 00 00 00 00 00[ ]* + 18: R_BPF_64_64 .text + 28: 8d 06 00 00 00 00 00 00 callx r6 + 30: 95 00 00 00 00 00 00 00 exit + +0000000000000038 <bar>: + 38: b7 00 00 00 00 00 00 00 r0=0 + 40: 95 00 00 00 00 00 00 00 exit +#pass diff --git a/gas/testsuite/gas/bpf/indcall-1.d b/gas/testsuite/gas/bpf/indcall-1.d index e04b98b..51103bb 100644 --- a/gas/testsuite/gas/bpf/indcall-1.d +++ b/gas/testsuite/gas/bpf/indcall-1.d @@ -1,5 +1,23 @@ -#as: -mxbpf --EL -#objdump: -mxbpf -dr +#as: -EL -misa-spec=xbpf +#objdump: -dr -M xbpf,dec #source: indcall-1.s -#dump: indcall-1.dump #name: BPF indirect call 1, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section \.text: + +0000000000000000 <main>: + 0: b7 00 00 00 01 00 00 00 mov %r0,1 + 8: b7 01 00 00 01 00 00 00 mov %r1,1 + 10: b7 02 00 00 02 00 00 00 mov %r2,2 + 18: 18 06 00 00 38 00 00 00 lddw %r6,56 + 20: 00 00 00 00 00 00 00 00[ ]* + 18: R_BPF_64_64 .text + 28: 8d 06 00 00 00 00 00 00 call %r6 + 30: 95 00 00 00 00 00 00 00 exit + +0000000000000038 <bar>: + 38: b7 00 00 00 00 00 00 00 mov %r0,0 + 40: 95 00 00 00 00 00 00 00 exit +#pass diff --git a/gas/testsuite/gas/bpf/indcall-1.dump b/gas/testsuite/gas/bpf/indcall-1.dump deleted file mode 100644 index 7793574..0000000 --- a/gas/testsuite/gas/bpf/indcall-1.dump +++ /dev/null @@ -1,18 +0,0 @@ -.*: +file format .*bpf.* - -Disassembly of section \.text: - -0000000000000000 <main>: - 0: b7 00 00 00 01 00 00 00 mov %r0,1 - 8: b7 01 00 00 01 00 00 00 mov %r1,1 - 10: b7 02 00 00 02 00 00 00 mov %r2,2 - 18: 18 06 00 00 38 00 00 00 lddw %r6,0x38 - 20: 00 00 00 00 00 00 00 00[ ]* - 18: R_BPF_64_64 .text - 28: 8d 06 00 00 00 00 00 00 call %r6 - 30: 95 00 00 00 00 00 00 00 exit - -0000000000000038 <bar>: - 38: b7 00 00 00 00 00 00 00 mov %r0,0 - 40: 95 00 00 00 00 00 00 00 exit -#pass diff --git a/gas/testsuite/gas/bpf/indcall-bad-1.l b/gas/testsuite/gas/bpf/indcall-bad-1.l deleted file mode 100644 index 8386736..0000000 --- a/gas/testsuite/gas/bpf/indcall-bad-1.l +++ /dev/null @@ -1,5 +0,0 @@ -.*: Assembler messages: -.* Error: bad expression -.* Error: illegal operand `call %r6' -.* Error: unexpected token: '%r6' -#pass diff --git a/gas/testsuite/gas/bpf/indcall-bad-1.s b/gas/testsuite/gas/bpf/indcall-bad-1.s deleted file mode 100644 index 0cdc4ab..0000000 --- a/gas/testsuite/gas/bpf/indcall-bad-1.s +++ /dev/null @@ -1 +0,0 @@ - call %r6 diff --git a/gas/testsuite/gas/bpf/jump-be-pseudoc.d b/gas/testsuite/gas/bpf/jump-be-pseudoc.d new file mode 100644 index 0000000..3874d58 --- /dev/null +++ b/gas/testsuite/gas/bpf/jump-be-pseudoc.d @@ -0,0 +1,32 @@ +#as: -EB -mdialect=pseudoc +#source: jump-pseudoc.s +#objdump: -dr -M dec,pseudoc +#name: eBPF JUMP instructions, big endian + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 05 00 00 03 00 00 00 00 goto 3 + 8: 0f 11 00 00 00 00 00 00 r1\+=r1 + 10: 15 30 00 01 00 00 00 03 if r3==3 goto 1 + 18: 1d 34 00 00 00 00 00 00 if r3==r4 goto 0 + 20: 35 30 ff fd 00 00 00 03 if r3>=3 goto -3 + 28: 3d 34 ff fc 00 00 00 00 if r3>=r4 goto -4 + 30: a5 30 00 01 00 00 00 03 if r3<3 goto 1 + 38: ad 34 00 00 00 00 00 00 if r3<r4 goto 0 + 40: b5 30 00 01 00 00 00 03 if r3<=3 goto 1 + 48: bd 34 00 00 00 00 00 00 if r3<=r4 goto 0 + 50: 45 30 00 01 00 00 00 03 if r3&3 goto 1 + 58: 4d 34 00 00 00 00 00 00 if r3&r4 goto 0 + 60: 55 30 00 01 00 00 00 03 if r3!=3 goto 1 + 68: 5d 34 00 00 00 00 00 00 if r3!=r4 goto 0 + 70: 65 30 00 01 00 00 00 03 if r3s>3 goto 1 + 78: 6d 34 00 00 00 00 00 00 if r3s>r4 goto 0 + 80: 75 30 00 01 00 00 00 03 if r3s>=3 goto 1 + 88: 7d 34 00 00 00 00 00 00 if r3s>=r4 goto 0 + 90: c5 30 00 01 00 00 00 03 if r3s<3 goto 1 + 98: cd 34 00 00 00 00 00 00 if r3s<r4 goto 0 + a0: d5 30 00 01 00 00 00 03 if r3s<=3 goto 1 + a8: dd 34 00 00 00 00 00 00 if r3s<=r4 goto 0 diff --git a/gas/testsuite/gas/bpf/jump-be.d b/gas/testsuite/gas/bpf/jump-be.d index 7e235e6..7c8a765 100644 --- a/gas/testsuite/gas/bpf/jump-be.d +++ b/gas/testsuite/gas/bpf/jump-be.d @@ -1,7 +1,6 @@ -#as: --EB +#as: -EB -mdialect=normal #source: jump.s -#source: jump-pseudoc.s -#objdump: -dr +#objdump: -dr -M dec #name: eBPF JUMP instructions, big endian .*: +file format .*bpf.* diff --git a/gas/testsuite/gas/bpf/jump-pseudoc.d b/gas/testsuite/gas/bpf/jump-pseudoc.d index bc17266..644d2be 100644 --- a/gas/testsuite/gas/bpf/jump-pseudoc.d +++ b/gas/testsuite/gas/bpf/jump-pseudoc.d @@ -1,5 +1,32 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=pseudoc +#objdump: -dr -M dec,pseudoc #source: jump-pseudoc.s -#dump: jump.dump #name: eBPF JUMP instructions, pseudoc syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 05 00 03 00 00 00 00 00 goto 3 + 8: 0f 11 00 00 00 00 00 00 r1\+=r1 + 10: 15 03 01 00 03 00 00 00 if r3==3 goto 1 + 18: 1d 43 00 00 00 00 00 00 if r3==r4 goto 0 + 20: 35 03 fd ff 03 00 00 00 if r3>=3 goto -3 + 28: 3d 43 fc ff 00 00 00 00 if r3>=r4 goto -4 + 30: a5 03 01 00 03 00 00 00 if r3<3 goto 1 + 38: ad 43 00 00 00 00 00 00 if r3<r4 goto 0 + 40: b5 03 01 00 03 00 00 00 if r3<=3 goto 1 + 48: bd 43 00 00 00 00 00 00 if r3<=r4 goto 0 + 50: 45 03 01 00 03 00 00 00 if r3&3 goto 1 + 58: 4d 43 00 00 00 00 00 00 if r3&r4 goto 0 + 60: 55 03 01 00 03 00 00 00 if r3!=3 goto 1 + 68: 5d 43 00 00 00 00 00 00 if r3!=r4 goto 0 + 70: 65 03 01 00 03 00 00 00 if r3s>3 goto 1 + 78: 6d 43 00 00 00 00 00 00 if r3s>r4 goto 0 + 80: 75 03 01 00 03 00 00 00 if r3s>=3 goto 1 + 88: 7d 43 00 00 00 00 00 00 if r3s>=r4 goto 0 + 90: c5 03 01 00 03 00 00 00 if r3s<3 goto 1 + 98: cd 43 00 00 00 00 00 00 if r3s<r4 goto 0 + a0: d5 03 01 00 03 00 00 00 if r3s<=3 goto 1 + a8: dd 43 00 00 00 00 00 00 if r3s<=r4 goto 0 diff --git a/gas/testsuite/gas/bpf/jump.d b/gas/testsuite/gas/bpf/jump.d index 082b3c3..742610a 100644 --- a/gas/testsuite/gas/bpf/jump.d +++ b/gas/testsuite/gas/bpf/jump.d @@ -1,5 +1,32 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=normal +#objdump: -dr -M dec #source: jump.s -#dump: jump.dump #name: eBPF JUMP instructions, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 05 00 03 00 00 00 00 00 ja 3 + 8: 0f 11 00 00 00 00 00 00 add %r1,%r1 + 10: 15 03 01 00 03 00 00 00 jeq %r3,3,1 + 18: 1d 43 00 00 00 00 00 00 jeq %r3,%r4,0 + 20: 35 03 fd ff 03 00 00 00 jge %r3,3,-3 + 28: 3d 43 fc ff 00 00 00 00 jge %r3,%r4,-4 + 30: a5 03 01 00 03 00 00 00 jlt %r3,3,1 + 38: ad 43 00 00 00 00 00 00 jlt %r3,%r4,0 + 40: b5 03 01 00 03 00 00 00 jle %r3,3,1 + 48: bd 43 00 00 00 00 00 00 jle %r3,%r4,0 + 50: 45 03 01 00 03 00 00 00 jset %r3,3,1 + 58: 4d 43 00 00 00 00 00 00 jset %r3,%r4,0 + 60: 55 03 01 00 03 00 00 00 jne %r3,3,1 + 68: 5d 43 00 00 00 00 00 00 jne %r3,%r4,0 + 70: 65 03 01 00 03 00 00 00 jsgt %r3,3,1 + 78: 6d 43 00 00 00 00 00 00 jsgt %r3,%r4,0 + 80: 75 03 01 00 03 00 00 00 jsge %r3,3,1 + 88: 7d 43 00 00 00 00 00 00 jsge %r3,%r4,0 + 90: c5 03 01 00 03 00 00 00 jslt %r3,3,1 + 98: cd 43 00 00 00 00 00 00 jslt %r3,%r4,0 + a0: d5 03 01 00 03 00 00 00 jsle %r3,3,1 + a8: dd 43 00 00 00 00 00 00 jsle %r3,%r4,0 diff --git a/gas/testsuite/gas/bpf/jump.dump b/gas/testsuite/gas/bpf/jump.dump deleted file mode 100644 index 6baad65..0000000 --- a/gas/testsuite/gas/bpf/jump.dump +++ /dev/null @@ -1,27 +0,0 @@ -.*: +file format .*bpf.* - -Disassembly of section .text: - -0+ <.text>: - 0: 05 00 03 00 00 00 00 00 ja 3 - 8: 0f 11 00 00 00 00 00 00 add %r1,%r1 - 10: 15 03 01 00 03 00 00 00 jeq %r3,3,1 - 18: 1d 43 00 00 00 00 00 00 jeq %r3,%r4,0 - 20: 35 03 fd ff 03 00 00 00 jge %r3,3,-3 - 28: 3d 43 fc ff 00 00 00 00 jge %r3,%r4,-4 - 30: a5 03 01 00 03 00 00 00 jlt %r3,3,1 - 38: ad 43 00 00 00 00 00 00 jlt %r3,%r4,0 - 40: b5 03 01 00 03 00 00 00 jle %r3,3,1 - 48: bd 43 00 00 00 00 00 00 jle %r3,%r4,0 - 50: 45 03 01 00 03 00 00 00 jset %r3,3,1 - 58: 4d 43 00 00 00 00 00 00 jset %r3,%r4,0 - 60: 55 03 01 00 03 00 00 00 jne %r3,3,1 - 68: 5d 43 00 00 00 00 00 00 jne %r3,%r4,0 - 70: 65 03 01 00 03 00 00 00 jsgt %r3,3,1 - 78: 6d 43 00 00 00 00 00 00 jsgt %r3,%r4,0 - 80: 75 03 01 00 03 00 00 00 jsge %r3,3,1 - 88: 7d 43 00 00 00 00 00 00 jsge %r3,%r4,0 - 90: c5 03 01 00 03 00 00 00 jslt %r3,3,1 - 98: cd 43 00 00 00 00 00 00 jslt %r3,%r4,0 - a0: d5 03 01 00 03 00 00 00 jsle %r3,3,1 - a8: dd 43 00 00 00 00 00 00 jsle %r3,%r4,0 diff --git a/gas/testsuite/gas/bpf/jump32-be-pseudoc.d b/gas/testsuite/gas/bpf/jump32-be-pseudoc.d new file mode 100644 index 0000000..ca20186 --- /dev/null +++ b/gas/testsuite/gas/bpf/jump32-be-pseudoc.d @@ -0,0 +1,32 @@ +#as: -EB -mdialect=pseudoc +#objdump: -dr -M dec,pseudoc +#source: jump32-pseudoc.s +#name: eBPF JUMP32 instructions, pseudoc syntax, big-endian + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 05 00 00 03 00 00 00 00 goto 3 + 8: 0f 11 00 00 00 00 00 00 r1\+=r1 + 10: 16 30 00 01 00 00 00 03 if w3==3 goto 1 + 18: 1e 34 00 00 00 00 00 00 if w3==w4 goto 0 + 20: 36 30 ff fd 00 00 00 03 if w3>=3 goto -3 + 28: 3e 34 ff fc 00 00 00 00 if w3>=w4 goto -4 + 30: a6 30 00 01 00 00 00 03 if w3<3 goto 1 + 38: ae 34 00 00 00 00 00 00 if w3<w4 goto 0 + 40: b6 30 00 01 00 00 00 03 if w3<=3 goto 1 + 48: be 34 00 00 00 00 00 00 if w3<=w4 goto 0 + 50: 46 30 00 01 00 00 00 03 if w3&3 goto 1 + 58: 4e 34 00 00 00 00 00 00 if w3&w4 goto 0 + 60: 56 30 00 01 00 00 00 03 if w3!=3 goto 1 + 68: 5e 34 00 00 00 00 00 00 if w3!=w4 goto 0 + 70: 66 30 00 01 00 00 00 03 if w3s>3 goto 1 + 78: 6e 34 00 00 00 00 00 00 if w3s>w4 goto 0 + 80: 76 30 00 01 00 00 00 03 if w3s>=3 goto 1 + 88: 7e 34 00 00 00 00 00 00 if w3s>=w4 goto 0 + 90: c6 30 00 01 00 00 00 03 if w3s<3 goto 1 + 98: ce 34 00 00 00 00 00 00 if w3s<w4 goto 0 + a0: d6 30 00 01 00 00 00 03 if w3s<=3 goto 1 + a8: de 34 00 00 00 00 00 00 if w3s<=w4 goto 0 diff --git a/gas/testsuite/gas/bpf/jump32-be.d b/gas/testsuite/gas/bpf/jump32-be.d new file mode 100644 index 0000000..446d338 --- /dev/null +++ b/gas/testsuite/gas/bpf/jump32-be.d @@ -0,0 +1,32 @@ +#as: -EB -mdialect=normal +#objdump: -dr -M dec +#source: jump32.s +#name: eBPF JUMP32 instructions, normal syntax, big-endian + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 05 00 00 03 00 00 00 00 ja 3 + 8: 0f 11 00 00 00 00 00 00 add %r1,%r1 + 10: 16 30 00 01 00 00 00 03 jeq32 %r3,3,1 + 18: 1e 34 00 00 00 00 00 00 jeq32 %r3,%r4,0 + 20: 36 30 ff fd 00 00 00 03 jge32 %r3,3,-3 + 28: 3e 34 ff fc 00 00 00 00 jge32 %r3,%r4,-4 + 30: a6 30 00 01 00 00 00 03 jlt32 %r3,3,1 + 38: ae 34 00 00 00 00 00 00 jlt32 %r3,%r4,0 + 40: b6 30 00 01 00 00 00 03 jle32 %r3,3,1 + 48: be 34 00 00 00 00 00 00 jle32 %r3,%r4,0 + 50: 46 30 00 01 00 00 00 03 jset32 %r3,3,1 + 58: 4e 34 00 00 00 00 00 00 jset32 %r3,%r4,0 + 60: 56 30 00 01 00 00 00 03 jne32 %r3,3,1 + 68: 5e 34 00 00 00 00 00 00 jne32 %r3,%r4,0 + 70: 66 30 00 01 00 00 00 03 jsgt32 %r3,3,1 + 78: 6e 34 00 00 00 00 00 00 jsgt32 %r3,%r4,0 + 80: 76 30 00 01 00 00 00 03 jsge32 %r3,3,1 + 88: 7e 34 00 00 00 00 00 00 jsge32 %r3,%r4,0 + 90: c6 30 00 01 00 00 00 03 jslt32 %r3,3,1 + 98: ce 34 00 00 00 00 00 00 jslt32 %r3,%r4,0 + a0: d6 30 00 01 00 00 00 03 jsle32 %r3,3,1 + a8: de 34 00 00 00 00 00 00 jsle32 %r3,%r4,0 diff --git a/gas/testsuite/gas/bpf/jump32-pseudoc.d b/gas/testsuite/gas/bpf/jump32-pseudoc.d index 55fb97b..27367d3 100644 --- a/gas/testsuite/gas/bpf/jump32-pseudoc.d +++ b/gas/testsuite/gas/bpf/jump32-pseudoc.d @@ -1,5 +1,32 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=pseudoc +#objdump: -dr -M dec,pseudoc #source: jump32-pseudoc.s -#dump: jump32.dump #name: eBPF JUMP32 instructions, pseudoc syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 05 00 03 00 00 00 00 00 goto 3 + 8: 0f 11 00 00 00 00 00 00 r1\+=r1 + 10: 16 03 01 00 03 00 00 00 if w3==3 goto 1 + 18: 1e 43 00 00 00 00 00 00 if w3==w4 goto 0 + 20: 36 03 fd ff 03 00 00 00 if w3>=3 goto -3 + 28: 3e 43 fc ff 00 00 00 00 if w3>=w4 goto -4 + 30: a6 03 01 00 03 00 00 00 if w3<3 goto 1 + 38: ae 43 00 00 00 00 00 00 if w3<w4 goto 0 + 40: b6 03 01 00 03 00 00 00 if w3<=3 goto 1 + 48: be 43 00 00 00 00 00 00 if w3<=w4 goto 0 + 50: 46 03 01 00 03 00 00 00 if w3&3 goto 1 + 58: 4e 43 00 00 00 00 00 00 if w3&w4 goto 0 + 60: 56 03 01 00 03 00 00 00 if w3!=3 goto 1 + 68: 5e 43 00 00 00 00 00 00 if w3!=w4 goto 0 + 70: 66 03 01 00 03 00 00 00 if w3s>3 goto 1 + 78: 6e 43 00 00 00 00 00 00 if w3s>w4 goto 0 + 80: 76 03 01 00 03 00 00 00 if w3s>=3 goto 1 + 88: 7e 43 00 00 00 00 00 00 if w3s>=w4 goto 0 + 90: c6 03 01 00 03 00 00 00 if w3s<3 goto 1 + 98: ce 43 00 00 00 00 00 00 if w3s<w4 goto 0 + a0: d6 03 01 00 03 00 00 00 if w3s<=3 goto 1 + a8: de 43 00 00 00 00 00 00 if w3s<=w4 goto 0 diff --git a/gas/testsuite/gas/bpf/jump32.d b/gas/testsuite/gas/bpf/jump32.d index c5efb41..e39dc38 100644 --- a/gas/testsuite/gas/bpf/jump32.d +++ b/gas/testsuite/gas/bpf/jump32.d @@ -1,5 +1,32 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=normal +#objdump: -dr -M dec #source: jump32.s -#dump: jump32.dump #name: eBPF JUMP32 instructions, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 05 00 03 00 00 00 00 00 ja 3 + 8: 0f 11 00 00 00 00 00 00 add %r1,%r1 + 10: 16 03 01 00 03 00 00 00 jeq32 %r3,3,1 + 18: 1e 43 00 00 00 00 00 00 jeq32 %r3,%r4,0 + 20: 36 03 fd ff 03 00 00 00 jge32 %r3,3,-3 + 28: 3e 43 fc ff 00 00 00 00 jge32 %r3,%r4,-4 + 30: a6 03 01 00 03 00 00 00 jlt32 %r3,3,1 + 38: ae 43 00 00 00 00 00 00 jlt32 %r3,%r4,0 + 40: b6 03 01 00 03 00 00 00 jle32 %r3,3,1 + 48: be 43 00 00 00 00 00 00 jle32 %r3,%r4,0 + 50: 46 03 01 00 03 00 00 00 jset32 %r3,3,1 + 58: 4e 43 00 00 00 00 00 00 jset32 %r3,%r4,0 + 60: 56 03 01 00 03 00 00 00 jne32 %r3,3,1 + 68: 5e 43 00 00 00 00 00 00 jne32 %r3,%r4,0 + 70: 66 03 01 00 03 00 00 00 jsgt32 %r3,3,1 + 78: 6e 43 00 00 00 00 00 00 jsgt32 %r3,%r4,0 + 80: 76 03 01 00 03 00 00 00 jsge32 %r3,3,1 + 88: 7e 43 00 00 00 00 00 00 jsge32 %r3,%r4,0 + 90: c6 03 01 00 03 00 00 00 jslt32 %r3,3,1 + 98: ce 43 00 00 00 00 00 00 jslt32 %r3,%r4,0 + a0: d6 03 01 00 03 00 00 00 jsle32 %r3,3,1 + a8: de 43 00 00 00 00 00 00 jsle32 %r3,%r4,0 diff --git a/gas/testsuite/gas/bpf/jump32.dump b/gas/testsuite/gas/bpf/jump32.dump deleted file mode 100644 index d99b92b..0000000 --- a/gas/testsuite/gas/bpf/jump32.dump +++ /dev/null @@ -1,27 +0,0 @@ -.*: +file format .*bpf.* - -Disassembly of section .text: - -0+ <.text>: - 0: 05 00 03 00 00 00 00 00 ja 3 - 8: 0f 11 00 00 00 00 00 00 add %r1,%r1 - 10: 16 03 01 00 03 00 00 00 jeq32 %r3,3,1 - 18: 1e 43 00 00 00 00 00 00 jeq32 %r3,%r4,0 - 20: 36 03 fd ff 03 00 00 00 jge32 %r3,3,-3 - 28: 3e 43 fc ff 00 00 00 00 jge32 %r3,%r4,-4 - 30: a6 03 01 00 03 00 00 00 jlt32 %r3,3,1 - 38: ae 43 00 00 00 00 00 00 jlt32 %r3,%r4,0 - 40: b6 03 01 00 03 00 00 00 jle32 %r3,3,1 - 48: be 43 00 00 00 00 00 00 jle32 %r3,%r4,0 - 50: 46 03 01 00 03 00 00 00 jset32 %r3,3,1 - 58: 4e 43 00 00 00 00 00 00 jset32 %r3,%r4,0 - 60: 56 03 01 00 03 00 00 00 jne32 %r3,3,1 - 68: 5e 43 00 00 00 00 00 00 jne32 %r3,%r4,0 - 70: 66 03 01 00 03 00 00 00 jsgt32 %r3,3,1 - 78: 6e 43 00 00 00 00 00 00 jsgt32 %r3,%r4,0 - 80: 76 03 01 00 03 00 00 00 jsge32 %r3,3,1 - 88: 7e 43 00 00 00 00 00 00 jsge32 %r3,%r4,0 - 90: c6 03 01 00 03 00 00 00 jslt32 %r3,3,1 - 98: ce 43 00 00 00 00 00 00 jslt32 %r3,%r4,0 - a0: d6 03 01 00 03 00 00 00 jsle32 %r3,3,1 - a8: de 43 00 00 00 00 00 00 jsle32 %r3,%r4,0 diff --git a/gas/testsuite/gas/bpf/lddw-be-pseudoc.d b/gas/testsuite/gas/bpf/lddw-be-pseudoc.d index e7b477a..940780b 100644 --- a/gas/testsuite/gas/bpf/lddw-be-pseudoc.d +++ b/gas/testsuite/gas/bpf/lddw-be-pseudoc.d @@ -1,5 +1,18 @@ -#as: --EB +#as: -EB -mdialect=pseudoc #source: lddw-pseudoc.s -#objdump: -dr -#dump: lddw-be.dump +#objdump: -dr -M hex,pseudoc #name: eBPF LDDW, big-endian, pseudoc syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 18 30 00 00 00 00 00 01 r3=0x1 ll + 8: 00 00 00 00 00 00 00 00 + 10: 18 40 00 00 de ad be ef r4=0xdeadbeef ll + 18: 00 00 00 00 00 00 00 00 + 20: 18 50 00 00 55 66 77 88 r5=0x1122334455667788 ll + 28: 00 00 00 00 11 22 33 44 + 30: 18 60 00 00 ff ff ff fe r6=0xfffffffffffffffe ll + 38: 00 00 00 00 ff ff ff ff diff --git a/gas/testsuite/gas/bpf/lddw-be.d b/gas/testsuite/gas/bpf/lddw-be.d index cf1bfba..c104378 100644 --- a/gas/testsuite/gas/bpf/lddw-be.d +++ b/gas/testsuite/gas/bpf/lddw-be.d @@ -1,5 +1,18 @@ -#as: --EB +#as: -EB -mdialect=normal #source: lddw.s -#objdump: -dr -#dump: lddw-be.dump +#objdump: -dr -M hex #name: eBPF LDDW, big-endian, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 18 30 00 00 00 00 00 01 lddw %r3,0x1 + 8: 00 00 00 00 00 00 00 00 + 10: 18 40 00 00 de ad be ef lddw %r4,0xdeadbeef + 18: 00 00 00 00 00 00 00 00 + 20: 18 50 00 00 55 66 77 88 lddw %r5,0x1122334455667788 + 28: 00 00 00 00 11 22 33 44 + 30: 18 60 00 00 ff ff ff fe lddw %r6,0xfffffffffffffffe + 38: 00 00 00 00 ff ff ff ff diff --git a/gas/testsuite/gas/bpf/lddw-be.dump b/gas/testsuite/gas/bpf/lddw-be.dump deleted file mode 100644 index 4de10f8..0000000 --- a/gas/testsuite/gas/bpf/lddw-be.dump +++ /dev/null @@ -1,13 +0,0 @@ -.*: +file format .*bpf.* - -Disassembly of section .text: - -0+ <.text>: - 0: 18 30 00 00 00 00 00 01 lddw %r3,1 - 8: 00 00 00 00 00 00 00 00 - 10: 18 40 00 00 de ad be ef lddw %r4,0xdeadbeef - 18: 00 00 00 00 00 00 00 00 - 20: 18 50 00 00 55 66 77 88 lddw %r5,0x1122334455667788 - 28: 00 00 00 00 11 22 33 44 - 30: 18 60 00 00 ff ff ff fe lddw %r6,-2 - 38: 00 00 00 00 ff ff ff ff diff --git a/gas/testsuite/gas/bpf/lddw-pseudoc.d b/gas/testsuite/gas/bpf/lddw-pseudoc.d index 838e012..3a5ce86 100644 --- a/gas/testsuite/gas/bpf/lddw-pseudoc.d +++ b/gas/testsuite/gas/bpf/lddw-pseudoc.d @@ -1,5 +1,18 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=pseudoc +#objdump: -dr -M hex,pseudoc #source: lddw-pseudoc.s -#dump: lddw.dump #name: eBPF LDDW, pseudoc syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 18 03 00 00 01 00 00 00 r3=0x1 ll + 8: 00 00 00 00 00 00 00 00 + 10: 18 04 00 00 ef be ad de r4=0xdeadbeef ll + 18: 00 00 00 00 00 00 00 00 + 20: 18 05 00 00 88 77 66 55 r5=0x1122334455667788 ll + 28: 00 00 00 00 44 33 22 11 + 30: 18 06 00 00 fe ff ff ff r6=0xfffffffffffffffe ll + 38: 00 00 00 00 ff ff ff ff diff --git a/gas/testsuite/gas/bpf/lddw.d b/gas/testsuite/gas/bpf/lddw.d index 82ff1b4..c7a0809 100644 --- a/gas/testsuite/gas/bpf/lddw.d +++ b/gas/testsuite/gas/bpf/lddw.d @@ -1,5 +1,18 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=normal +#objdump: -dr -M hex #source: lddw.s -#dump: lddw.dump #name: eBPF LDDW, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 18 03 00 00 01 00 00 00 lddw %r3,0x1 + 8: 00 00 00 00 00 00 00 00 + 10: 18 04 00 00 ef be ad de lddw %r4,0xdeadbeef + 18: 00 00 00 00 00 00 00 00 + 20: 18 05 00 00 88 77 66 55 lddw %r5,0x1122334455667788 + 28: 00 00 00 00 44 33 22 11 + 30: 18 06 00 00 fe ff ff ff lddw %r6,0xfffffffffffffffe + 38: 00 00 00 00 ff ff ff ff diff --git a/gas/testsuite/gas/bpf/lddw.dump b/gas/testsuite/gas/bpf/lddw.dump deleted file mode 100644 index 9f1485d..0000000 --- a/gas/testsuite/gas/bpf/lddw.dump +++ /dev/null @@ -1,13 +0,0 @@ -.*: +file format .*bpf.* - -Disassembly of section .text: - -0+ <.text>: - 0: 18 03 00 00 01 00 00 00 lddw %r3,1 - 8: 00 00 00 00 00 00 00 00 - 10: 18 04 00 00 ef be ad de lddw %r4,0xdeadbeef - 18: 00 00 00 00 00 00 00 00 - 20: 18 05 00 00 88 77 66 55 lddw %r5,0x1122334455667788 - 28: 00 00 00 00 44 33 22 11 - 30: 18 06 00 00 fe ff ff ff lddw %r6,-2 - 38: 00 00 00 00 ff ff ff ff diff --git a/gas/testsuite/gas/bpf/mem-be-pseudoc.d b/gas/testsuite/gas/bpf/mem-be-pseudoc.d new file mode 100644 index 0000000..ef13fe1 --- /dev/null +++ b/gas/testsuite/gas/bpf/mem-be-pseudoc.d @@ -0,0 +1,30 @@ +#as: -EB -mdialect=pseudoc +#objdump: -dr -M hex,pseudoc +#source: mem-pseudoc.s +#name: eBPF MEM instructions, modulus lddw, pseudo-c syntax, big-endian + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 20 00 00 00 00 00 be ef r0=\*\(u32\*\)skb\[0xbeef\] + 8: 28 00 00 00 00 00 be ef r0=\*\(u16\*\)skb\[0xbeef\] + 10: 30 00 00 00 00 00 be ef r0=\*\(u8\*\)skb\[0xbeef\] + 18: 38 00 00 00 00 00 be ef r0=\*\(u64\*\)skb\[0xbeef\] + 20: 40 03 00 00 00 00 be ef r0=\*\(u32\*\)skb\[r3\+0xbeef\] + 28: 48 05 00 00 00 00 be ef r0=\*\(u16\*\)skb\[r5\+0xbeef\] + 30: 50 07 00 00 00 00 be ef r0=\*\(u8\*\)skb\[r7\+0xbeef\] + 38: 58 09 00 00 00 00 be ef r0=\*\(u64\*\)skb\[r9\+0xbeef\] + 40: 61 21 7e ef 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x7eef\) + 48: 69 21 7e ef 00 00 00 00 r2=\*\(u16\*\)\(r1\+0x7eef\) + 50: 71 21 7e ef 00 00 00 00 r2=\*\(u8\*\)\(r1\+0x7eef\) + 58: 79 21 ff fe 00 00 00 00 r2=\*\(u64\*\)\(r1\+0xfffe\) + 60: 63 12 7e ef 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2 + 68: 6b 12 7e ef 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2 + 70: 73 12 7e ef 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2 + 78: 7b 12 ff fe 00 00 00 00 \*\(u64\*\)\(r1\+0xfffe\)=r2 + 80: 72 10 7e ef 11 22 33 44 \*\(u8\*\)\(r1\+0x7eef\)=0x11223344 + 88: 6a 10 7e ef 11 22 33 44 \*\(u16\*\)\(r1\+0x7eef\)=0x11223344 + 90: 62 10 7e ef 11 22 33 44 \*\(u32\*\)\(r1\+0x7eef\)=0x11223344 + 98: 7a 10 ff fe 11 22 33 44 \*\(u64\*\)\(r1\+0xfffe\)=0x11223344 diff --git a/gas/testsuite/gas/bpf/mem-be.d b/gas/testsuite/gas/bpf/mem-be.d index 148c55a..f24efaa 100644 --- a/gas/testsuite/gas/bpf/mem-be.d +++ b/gas/testsuite/gas/bpf/mem-be.d @@ -1,7 +1,6 @@ -#as: --EB +#as: -EB -mdialect=normal #source: mem.s -#source: mem-pseudoc.s -#objdump: -dr +#objdump: -dr -M hex #name: eBPF MEM instructions, modulus lddw, big endian .*: +file format .*bpf.* @@ -20,12 +19,12 @@ Disassembly of section .text: 40: 61 21 7e ef 00 00 00 00 ldxw %r2,\[%r1\+0x7eef\] 48: 69 21 7e ef 00 00 00 00 ldxh %r2,\[%r1\+0x7eef\] 50: 71 21 7e ef 00 00 00 00 ldxb %r2,\[%r1\+0x7eef\] - 58: 79 21 ff fe 00 00 00 00 ldxdw %r2,\[%r1\+-2\] + 58: 79 21 ff fe 00 00 00 00 ldxdw %r2,\[%r1\+0xfffe\] 60: 63 12 7e ef 00 00 00 00 stxw \[%r1\+0x7eef\],%r2 68: 6b 12 7e ef 00 00 00 00 stxh \[%r1\+0x7eef\],%r2 70: 73 12 7e ef 00 00 00 00 stxb \[%r1\+0x7eef\],%r2 - 78: 7b 12 ff fe 00 00 00 00 stxdw \[%r1\+-2\],%r2 + 78: 7b 12 ff fe 00 00 00 00 stxdw \[%r1\+0xfffe\],%r2 80: 72 10 7e ef 11 22 33 44 stb \[%r1\+0x7eef\],0x11223344 88: 6a 10 7e ef 11 22 33 44 sth \[%r1\+0x7eef\],0x11223344 90: 62 10 7e ef 11 22 33 44 stw \[%r1\+0x7eef\],0x11223344 - 98: 7a 10 ff fe 11 22 33 44 stdw \[%r1\+-2\],0x11223344 + 98: 7a 10 ff fe 11 22 33 44 stdw \[%r1\+0xfffe\],0x11223344 diff --git a/gas/testsuite/gas/bpf/mem-pseudoc.d b/gas/testsuite/gas/bpf/mem-pseudoc.d index ef5b895..4e8b7d0 100644 --- a/gas/testsuite/gas/bpf/mem-pseudoc.d +++ b/gas/testsuite/gas/bpf/mem-pseudoc.d @@ -1,5 +1,30 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=pseudoc +#objdump: -dr -M hex,pseudoc #source: mem-pseudoc.s -#dump: mem.dump #name: eBPF MEM instructions, modulus lddw, pseudo-c syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 20 00 00 00 ef be 00 00 r0=\*\(u32\*\)skb\[0xbeef\] + 8: 28 00 00 00 ef be 00 00 r0=\*\(u16\*\)skb\[0xbeef\] + 10: 30 00 00 00 ef be 00 00 r0=\*\(u8\*\)skb\[0xbeef\] + 18: 38 00 00 00 ef be 00 00 r0=\*\(u64\*\)skb\[0xbeef\] + 20: 40 30 00 00 ef be 00 00 r0=\*\(u32\*\)skb\[r3\+0xbeef\] + 28: 48 50 00 00 ef be 00 00 r0=\*\(u16\*\)skb\[r5\+0xbeef\] + 30: 50 70 00 00 ef be 00 00 r0=\*\(u8\*\)skb\[r7\+0xbeef\] + 38: 58 90 00 00 ef be 00 00 r0=\*\(u64\*\)skb\[r9\+0xbeef\] + 40: 61 12 ef 7e 00 00 00 00 r2=\*\(u32\*\)\(r1\+0x7eef\) + 48: 69 12 ef 7e 00 00 00 00 r2=\*\(u16\*\)\(r1\+0x7eef\) + 50: 71 12 ef 7e 00 00 00 00 r2=\*\(u8\*\)\(r1\+0x7eef\) + 58: 79 12 fe ff 00 00 00 00 r2=\*\(u64\*\)\(r1\+0xfffe\) + 60: 63 21 ef 7e 00 00 00 00 \*\(u32\*\)\(r1\+0x7eef\)=r2 + 68: 6b 21 ef 7e 00 00 00 00 \*\(u16\*\)\(r1\+0x7eef\)=r2 + 70: 73 21 ef 7e 00 00 00 00 \*\(u8\*\)\(r1\+0x7eef\)=r2 + 78: 7b 21 fe ff 00 00 00 00 \*\(u64\*\)\(r1\+0xfffe\)=r2 + 80: 72 01 ef 7e 44 33 22 11 \*\(u8\*\)\(r1\+0x7eef\)=0x11223344 + 88: 6a 01 ef 7e 44 33 22 11 \*\(u16\*\)\(r1\+0x7eef\)=0x11223344 + 90: 62 01 ef 7e 44 33 22 11 \*\(u32\*\)\(r1\+0x7eef\)=0x11223344 + 98: 7a 01 fe ff 44 33 22 11 \*\(u64\*\)\(r1\+0xfffe\)=0x11223344 diff --git a/gas/testsuite/gas/bpf/mem-pseudoc.s b/gas/testsuite/gas/bpf/mem-pseudoc.s index 06c2cfc..7b8c832 100644 --- a/gas/testsuite/gas/bpf/mem-pseudoc.s +++ b/gas/testsuite/gas/bpf/mem-pseudoc.s @@ -17,7 +17,7 @@ *(u16 *)(r1 + 32495) = r2 *(u8 *)(r1 + 32495) = r2 *(u64 *)(r1 - 2) = r2 - stb [%r1+0x7eef], 0x11223344 - sth [%r1+0x7eef], 0x11223344 - stw [%r1+0x7eef], 0x11223344 - stdw [%r1+-2], 0x11223344 + *(u8 *)(r1 + 0x7eef) = 0x11223344 + *(u16 *)(r1 + 0x7eef) = 0x11223344 + *(u32 *)(r1 + 0x7eef) = 0x11223344 + *(u64 *)(r1 + -2) = 0x11223344 diff --git a/gas/testsuite/gas/bpf/mem.d b/gas/testsuite/gas/bpf/mem.d index b01bdaa..669aae3 100644 --- a/gas/testsuite/gas/bpf/mem.d +++ b/gas/testsuite/gas/bpf/mem.d @@ -1,5 +1,30 @@ -#as: --EL -#objdump: -dr +#as: -EL -mdialect=normal +#objdump: -dr -M hex #source: mem.s -#dump: mem.dump #name: eBPF MEM instructions, modulus lddw, normal syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: 20 00 00 00 ef be 00 00 ldabsw 0xbeef + 8: 28 00 00 00 ef be 00 00 ldabsh 0xbeef + 10: 30 00 00 00 ef be 00 00 ldabsb 0xbeef + 18: 38 00 00 00 ef be 00 00 ldabsdw 0xbeef + 20: 40 30 00 00 ef be 00 00 ldindw %r3,0xbeef + 28: 48 50 00 00 ef be 00 00 ldindh %r5,0xbeef + 30: 50 70 00 00 ef be 00 00 ldindb %r7,0xbeef + 38: 58 90 00 00 ef be 00 00 ldinddw %r9,0xbeef + 40: 61 12 ef 7e 00 00 00 00 ldxw %r2,\[%r1\+0x7eef\] + 48: 69 12 ef 7e 00 00 00 00 ldxh %r2,\[%r1\+0x7eef\] + 50: 71 12 ef 7e 00 00 00 00 ldxb %r2,\[%r1\+0x7eef\] + 58: 79 12 fe ff 00 00 00 00 ldxdw %r2,\[%r1\+0xfffe\] + 60: 63 21 ef 7e 00 00 00 00 stxw \[%r1\+0x7eef\],%r2 + 68: 6b 21 ef 7e 00 00 00 00 stxh \[%r1\+0x7eef\],%r2 + 70: 73 21 ef 7e 00 00 00 00 stxb \[%r1\+0x7eef\],%r2 + 78: 7b 21 fe ff 00 00 00 00 stxdw \[%r1\+0xfffe\],%r2 + 80: 72 01 ef 7e 44 33 22 11 stb \[%r1\+0x7eef\],0x11223344 + 88: 6a 01 ef 7e 44 33 22 11 sth \[%r1\+0x7eef\],0x11223344 + 90: 62 01 ef 7e 44 33 22 11 stw \[%r1\+0x7eef\],0x11223344 + 98: 7a 01 fe ff 44 33 22 11 stdw \[%r1\+0xfffe\],0x11223344 diff --git a/gas/testsuite/gas/bpf/mem.dump b/gas/testsuite/gas/bpf/mem.dump deleted file mode 100644 index 6ad26bc..0000000 --- a/gas/testsuite/gas/bpf/mem.dump +++ /dev/null @@ -1,25 +0,0 @@ -.*: +file format .*bpf.* - -Disassembly of section .text: - -0+ <.text>: - 0: 20 00 00 00 ef be 00 00 ldabsw 0xbeef - 8: 28 00 00 00 ef be 00 00 ldabsh 0xbeef - 10: 30 00 00 00 ef be 00 00 ldabsb 0xbeef - 18: 38 00 00 00 ef be 00 00 ldabsdw 0xbeef - 20: 40 30 00 00 ef be 00 00 ldindw %r3,0xbeef - 28: 48 50 00 00 ef be 00 00 ldindh %r5,0xbeef - 30: 50 70 00 00 ef be 00 00 ldindb %r7,0xbeef - 38: 58 90 00 00 ef be 00 00 ldinddw %r9,0xbeef - 40: 61 12 ef 7e 00 00 00 00 ldxw %r2,\[%r1\+0x7eef\] - 48: 69 12 ef 7e 00 00 00 00 ldxh %r2,\[%r1\+0x7eef\] - 50: 71 12 ef 7e 00 00 00 00 ldxb %r2,\[%r1\+0x7eef\] - 58: 79 12 fe ff 00 00 00 00 ldxdw %r2,\[%r1\+-2\] - 60: 63 21 ef 7e 00 00 00 00 stxw \[%r1\+0x7eef\],%r2 - 68: 6b 21 ef 7e 00 00 00 00 stxh \[%r1\+0x7eef\],%r2 - 70: 73 21 ef 7e 00 00 00 00 stxb \[%r1\+0x7eef\],%r2 - 78: 7b 21 fe ff 00 00 00 00 stxdw \[%r1\+-2\],%r2 - 80: 72 01 ef 7e 44 33 22 11 stb \[%r1\+0x7eef\],0x11223344 - 88: 6a 01 ef 7e 44 33 22 11 sth \[%r1\+0x7eef\],0x11223344 - 90: 62 01 ef 7e 44 33 22 11 stw \[%r1\+0x7eef\],0x11223344 - 98: 7a 01 fe ff 44 33 22 11 stdw \[%r1\+-2\],0x11223344 diff --git a/gas/testsuite/gas/bpf/mem.s b/gas/testsuite/gas/bpf/mem.s index af6f41b..798a18e 100644 --- a/gas/testsuite/gas/bpf/mem.s +++ b/gas/testsuite/gas/bpf/mem.s @@ -21,4 +21,4 @@ stb [%r1+0x7eef], 0x11223344 sth [%r1+0x7eef], 0x11223344 stw [%r1+0x7eef], 0x11223344 - stdw [%r1+-2], 0x11223344 + stdw [%r1-2], 0x11223344 diff --git a/gas/testsuite/gas/bpf/pseudoc-normal-be.d b/gas/testsuite/gas/bpf/pseudoc-normal-be.d deleted file mode 100644 index 7a577ed..0000000 --- a/gas/testsuite/gas/bpf/pseudoc-normal-be.d +++ /dev/null @@ -1,214 +0,0 @@ -#as: --EB -#objdump: -dr -#source: pseudoc-normal.s -#name: eBPF clang (pseudo-C)/gas (normal) instructions - -.*: +file format .*bpf.* - -Disassembly of section .text: - -0+ <beg>: - 0: 07 10 00 00 00 00 00 aa add %r1,0xaa - 8: 07 10 00 00 00 00 00 aa add %r1,0xaa - 10: 0f 12 00 00 00 00 00 00 add %r1,%r2 - 18: 0f 12 00 00 00 00 00 00 add %r1,%r2 - 20: 17 10 00 00 00 00 00 aa sub %r1,0xaa - 28: 17 10 00 00 00 00 00 aa sub %r1,0xaa - 30: 1f 12 00 00 00 00 00 00 sub %r1,%r2 - 38: 1f 12 00 00 00 00 00 00 sub %r1,%r2 - 40: 27 10 00 00 00 00 00 aa mul %r1,0xaa - 48: 27 10 00 00 00 00 00 aa mul %r1,0xaa - 50: 2f 12 00 00 00 00 00 00 mul %r1,%r2 - 58: 2f 12 00 00 00 00 00 00 mul %r1,%r2 - 60: 37 10 00 00 00 00 00 aa div %r1,0xaa - 68: 37 10 00 00 00 00 00 aa div %r1,0xaa - 70: 3f 12 00 00 00 00 00 00 div %r1,%r2 - 78: 3f 12 00 00 00 00 00 00 div %r1,%r2 - 80: 47 10 00 00 00 00 00 aa or %r1,0xaa - 88: 47 10 00 00 00 00 00 aa or %r1,0xaa - 90: 4f 12 00 00 00 00 00 00 or %r1,%r2 - 98: 4f 12 00 00 00 00 00 00 or %r1,%r2 - a0: 57 10 00 00 00 00 00 aa and %r1,0xaa - a8: 57 10 00 00 00 00 00 aa and %r1,0xaa - b0: 5f 12 00 00 00 00 00 00 and %r1,%r2 - b8: 5f 12 00 00 00 00 00 00 and %r1,%r2 - c0: 67 10 00 00 00 00 00 aa lsh %r1,0xaa - c8: 67 10 00 00 00 00 00 aa lsh %r1,0xaa - d0: 6f 12 00 00 00 00 00 00 lsh %r1,%r2 - d8: 6f 12 00 00 00 00 00 00 lsh %r1,%r2 - e0: 77 10 00 00 00 00 00 aa rsh %r1,0xaa - e8: 77 10 00 00 00 00 00 aa rsh %r1,0xaa - f0: 7f 12 00 00 00 00 00 00 rsh %r1,%r2 - f8: 7f 12 00 00 00 00 00 00 rsh %r1,%r2 - 100: a7 10 00 00 00 00 00 aa xor %r1,0xaa - 108: a7 10 00 00 00 00 00 aa xor %r1,0xaa - 110: af 12 00 00 00 00 00 00 xor %r1,%r2 - 118: af 12 00 00 00 00 00 00 xor %r1,%r2 - 120: b7 10 00 00 00 00 00 aa mov %r1,0xaa - 128: b7 10 00 00 00 00 00 aa mov %r1,0xaa - 130: bf 12 00 00 00 00 00 00 mov %r1,%r2 - 138: bf 12 00 00 00 00 00 00 mov %r1,%r2 - 140: c7 10 00 00 00 00 00 aa arsh %r1,0xaa - 148: c7 10 00 00 00 00 00 aa arsh %r1,0xaa - 150: cf 12 00 00 00 00 00 00 arsh %r1,%r2 - 158: cf 12 00 00 00 00 00 00 arsh %r1,%r2 - 160: 87 10 00 00 00 00 00 00 neg %r1 - 168: 87 10 00 00 00 00 00 00 neg %r1 - 170: 04 10 00 00 00 00 00 aa add32 %r1,0xaa - 178: 04 10 00 00 00 00 00 aa add32 %r1,0xaa - 180: 0c 12 00 00 00 00 00 00 add32 %r1,%r2 - 188: 0c 12 00 00 00 00 00 00 add32 %r1,%r2 - 190: 14 10 00 00 00 00 00 aa sub32 %r1,0xaa - 198: 14 10 00 00 00 00 00 aa sub32 %r1,0xaa - 1a0: 1c 12 00 00 00 00 00 00 sub32 %r1,%r2 - 1a8: 1c 12 00 00 00 00 00 00 sub32 %r1,%r2 - 1b0: 24 10 00 00 00 00 00 aa mul32 %r1,0xaa - 1b8: 24 10 00 00 00 00 00 aa mul32 %r1,0xaa - 1c0: 2c 12 00 00 00 00 00 00 mul32 %r1,%r2 - 1c8: 2c 12 00 00 00 00 00 00 mul32 %r1,%r2 - 1d0: 34 10 00 00 00 00 00 aa div32 %r1,0xaa - 1d8: 34 10 00 00 00 00 00 aa div32 %r1,0xaa - 1e0: 3c 12 00 00 00 00 00 00 div32 %r1,%r2 - 1e8: 3c 12 00 00 00 00 00 00 div32 %r1,%r2 - 1f0: 44 10 00 00 00 00 00 aa or32 %r1,0xaa - 1f8: 44 10 00 00 00 00 00 aa or32 %r1,0xaa - 200: 4c 12 00 00 00 00 00 00 or32 %r1,%r2 - 208: 4c 12 00 00 00 00 00 00 or32 %r1,%r2 - 210: 54 10 00 00 00 00 00 aa and32 %r1,0xaa - 218: 54 10 00 00 00 00 00 aa and32 %r1,0xaa - 220: 5c 12 00 00 00 00 00 00 and32 %r1,%r2 - 228: 5c 12 00 00 00 00 00 00 and32 %r1,%r2 - 230: 64 10 00 00 00 00 00 aa lsh32 %r1,0xaa - 238: 64 10 00 00 00 00 00 aa lsh32 %r1,0xaa - 240: 6c 12 00 00 00 00 00 00 lsh32 %r1,%r2 - 248: 6c 12 00 00 00 00 00 00 lsh32 %r1,%r2 - 250: 74 10 00 00 00 00 00 aa rsh32 %r1,0xaa - 258: 74 10 00 00 00 00 00 aa rsh32 %r1,0xaa - 260: 7c 12 00 00 00 00 00 00 rsh32 %r1,%r2 - 268: 7c 12 00 00 00 00 00 00 rsh32 %r1,%r2 - 270: a4 10 00 00 00 00 00 aa xor32 %r1,0xaa - 278: a4 10 00 00 00 00 00 aa xor32 %r1,0xaa - 280: ac 12 00 00 00 00 00 00 xor32 %r1,%r2 - 288: ac 12 00 00 00 00 00 00 xor32 %r1,%r2 - 290: b4 10 00 00 00 00 00 aa mov32 %r1,0xaa - 298: b4 10 00 00 00 00 00 aa mov32 %r1,0xaa - 2a0: bc 12 00 00 00 00 00 00 mov32 %r1,%r2 - 2a8: bc 12 00 00 00 00 00 00 mov32 %r1,%r2 - 2b0: c4 10 00 00 00 00 00 aa arsh32 %r1,0xaa - 2b8: c4 10 00 00 00 00 00 aa arsh32 %r1,0xaa - 2c0: cc 12 00 00 00 00 00 00 arsh32 %r1,%r2 - 2c8: cc 12 00 00 00 00 00 00 arsh32 %r1,%r2 - 2d0: 84 10 00 00 00 00 00 00 neg32 %r1 - 2d8: 84 10 00 00 00 00 00 00 neg32 %r1 - 2e0: d4 10 00 00 00 00 00 10 endle %r1,16 - 2e8: d4 10 00 00 00 00 00 10 endle %r1,16 - 2f0: d4 10 00 00 00 00 00 20 endle %r1,32 - 2f8: d4 10 00 00 00 00 00 20 endle %r1,32 - 300: d4 10 00 00 00 00 00 40 endle %r1,64 - 308: d4 10 00 00 00 00 00 40 endle %r1,64 - 310: dc 10 00 00 00 00 00 10 endbe %r1,16 - 318: dc 10 00 00 00 00 00 10 endbe %r1,16 - 320: dc 10 00 00 00 00 00 20 endbe %r1,32 - 328: dc 10 00 00 00 00 00 20 endbe %r1,32 - 330: dc 10 00 00 00 00 00 40 endbe %r1,64 - 338: dc 10 00 00 00 00 00 40 endbe %r1,64 - 340: 71 12 00 aa 00 00 00 00 ldxb %r1,\[%r2\+0xaa\] - 348: 71 12 00 aa 00 00 00 00 ldxb %r1,\[%r2\+0xaa\] - 350: 69 12 00 aa 00 00 00 00 ldxh %r1,\[%r2\+0xaa\] - 358: 69 12 00 aa 00 00 00 00 ldxh %r1,\[%r2\+0xaa\] - 360: 61 12 00 aa 00 00 00 00 ldxw %r1,\[%r2\+0xaa\] - 368: 61 12 00 aa 00 00 00 00 ldxw %r1,\[%r2\+0xaa\] - 370: 79 12 00 aa 00 00 00 00 ldxdw %r1,\[%r2\+0xaa\] - 378: 79 12 00 aa 00 00 00 00 ldxdw %r1,\[%r2\+0xaa\] - 380: 73 12 00 aa 00 00 00 00 stxb \[%r1\+0xaa\],%r2 - 388: 73 12 00 aa 00 00 00 00 stxb \[%r1\+0xaa\],%r2 - 390: 6b 12 00 aa 00 00 00 00 stxh \[%r1\+0xaa\],%r2 - 398: 6b 12 00 aa 00 00 00 00 stxh \[%r1\+0xaa\],%r2 - 3a0: 63 12 00 aa 00 00 00 00 stxw \[%r1\+0xaa\],%r2 - 3a8: 63 12 00 aa 00 00 00 00 stxw \[%r1\+0xaa\],%r2 - 3b0: 7b 12 00 aa 00 00 00 00 stxdw \[%r1\+0xaa\],%r2 - 3b8: 7b 12 00 aa 00 00 00 00 stxdw \[%r1\+0xaa\],%r2 - 3c0: 05 00 00 bb 00 00 00 00 ja 187 - 3c8: 05 00 00 bb 00 00 00 00 ja 187 - 3d0: 15 10 00 bb 00 00 00 aa jeq %r1,0xaa,187 - 3d8: 15 10 00 bb 00 00 00 aa jeq %r1,0xaa,187 - 3e0: 1d 12 00 bb 00 00 00 00 jeq %r1,%r2,187 - 3e8: 1d 12 00 bb 00 00 00 00 jeq %r1,%r2,187 - 3f0: 25 10 00 bb 00 00 00 aa jgt %r1,0xaa,187 - 3f8: 25 10 00 bb 00 00 00 aa jgt %r1,0xaa,187 - 400: 2d 12 00 bb 00 00 00 00 jgt %r1,%r2,187 - 408: 2d 12 00 bb 00 00 00 00 jgt %r1,%r2,187 - 410: 35 10 00 bb 00 00 00 aa jge %r1,0xaa,187 - 418: 35 10 00 bb 00 00 00 aa jge %r1,0xaa,187 - 420: 3d 12 00 bb 00 00 00 00 jge %r1,%r2,187 - 428: 3d 12 00 bb 00 00 00 00 jge %r1,%r2,187 - 430: a5 10 00 bb 00 00 00 aa jlt %r1,0xaa,187 - 438: a5 10 00 bb 00 00 00 aa jlt %r1,0xaa,187 - 440: ad 12 00 bb 00 00 00 00 jlt %r1,%r2,187 - 448: ad 12 00 bb 00 00 00 00 jlt %r1,%r2,187 - 450: b5 10 00 bb 00 00 00 aa jle %r1,0xaa,187 - 458: b5 10 00 bb 00 00 00 aa jle %r1,0xaa,187 - 460: bd 12 00 bb 00 00 00 00 jle %r1,%r2,187 - 468: bd 12 00 bb 00 00 00 00 jle %r1,%r2,187 - 470: 45 10 00 bb 00 00 00 aa jset %r1,0xaa,187 - 478: 45 10 00 bb 00 00 00 aa jset %r1,0xaa,187 - 480: 4d 12 00 bb 00 00 00 00 jset %r1,%r2,187 - 488: 4d 12 00 bb 00 00 00 00 jset %r1,%r2,187 - 490: 55 10 00 bb 00 00 00 aa jne %r1,0xaa,187 - 498: 55 10 00 bb 00 00 00 aa jne %r1,0xaa,187 - 4a0: 5d 12 00 bb 00 00 00 00 jne %r1,%r2,187 - 4a8: 5d 12 00 bb 00 00 00 00 jne %r1,%r2,187 - 4b0: 65 10 00 bb 00 00 00 aa jsgt %r1,0xaa,187 - 4b8: 65 10 00 bb 00 00 00 aa jsgt %r1,0xaa,187 - 4c0: 6d 12 00 bb 00 00 00 00 jsgt %r1,%r2,187 - 4c8: 6d 12 00 bb 00 00 00 00 jsgt %r1,%r2,187 - 4d0: 75 10 00 bb 00 00 00 aa jsge %r1,0xaa,187 - 4d8: 75 10 00 bb 00 00 00 aa jsge %r1,0xaa,187 - 4e0: 7d 12 00 bb 00 00 00 00 jsge %r1,%r2,187 - 4e8: 7d 12 00 bb 00 00 00 00 jsge %r1,%r2,187 - 4f0: c5 10 00 bb 00 00 00 aa jslt %r1,0xaa,187 - 4f8: c5 10 00 bb 00 00 00 aa jslt %r1,0xaa,187 - 500: cd 12 00 bb 00 00 00 00 jslt %r1,%r2,187 - 508: cd 12 00 bb 00 00 00 00 jslt %r1,%r2,187 - 510: d5 10 00 bb 00 00 00 aa jsle %r1,0xaa,187 - 518: d5 10 00 bb 00 00 00 aa jsle %r1,0xaa,187 - 520: dd 12 00 bb 00 00 00 00 jsle %r1,%r2,187 - 528: dd 12 00 bb 00 00 00 00 jsle %r1,%r2,187 - 530: 85 00 00 00 00 00 00 aa call 170 - 538: 85 00 00 00 00 00 00 aa call 170 - 540: 95 00 00 00 00 00 00 00 exit - 548: 95 00 00 00 00 00 00 00 exit - 550: b7 60 00 00 00 00 06 20 mov %r6,0x620 - 558: 95 00 00 00 00 00 00 00 exit - 560: 20 00 00 00 00 00 00 aa ldabsw 0xaa - 568: 20 00 00 00 00 00 00 aa ldabsw 0xaa - 570: 50 07 00 00 00 00 00 aa ldindb %r7,0xaa - 578: 50 07 00 00 00 00 00 aa ldindb %r7,0xaa - 580: 20 00 00 00 00 00 00 aa ldabsw 0xaa - 588: 20 00 00 00 00 00 00 aa ldabsw 0xaa - 590: 50 07 00 00 00 00 00 aa ldindb %r7,0xaa - 598: 50 07 00 00 00 00 00 aa ldindb %r7,0xaa - 5a0: 18 30 00 00 00 00 00 01 lddw %r3,1 - 5a8: 00 00 00 00 00 00 00 00 - 5b0: 18 30 00 00 00 00 00 01 lddw %r3,1 - 5b8: 00 00 00 00 00 00 00 00 - 5c0: 18 40 00 00 ee ff 77 88 lddw %r4,-6144092013047351416 - 5c8: 00 00 00 00 aa bb cc dd - 5d0: 18 40 00 00 ee ff 77 88 lddw %r4,-6144092013047351416 - 5d8: 00 00 00 00 aa bb cc dd - 5e0: 18 50 00 00 55 66 77 88 lddw %r5,0x1122334455667788 - 5e8: 00 00 00 00 11 22 33 44 - 5f0: 18 50 00 00 55 66 77 88 lddw %r5,0x1122334455667788 - 5f8: 00 00 00 00 11 22 33 44 - 600: 18 60 00 00 00 00 06 20 lddw %r6,0x620 - 608: 00 00 00 00 00 00 00 00 - 600: R_BPF_64_64 .text - 610: 18 60 00 00 00 00 06 20 lddw %r6,0x620 - 618: 00 00 00 00 00 00 00 00 - 610: R_BPF_64_64 .text - -0000000000000620 <main>: - 620: c3 12 00 aa 00 00 00 00 xaddw \[%r1\+0xaa\],%r2 - 628: c3 12 00 aa 00 00 00 00 xaddw \[%r1\+0xaa\],%r2 - 630: db 12 00 aa 00 00 00 00 xadddw \[%r1\+0xaa\],%r2 - 638: db 12 00 aa 00 00 00 00 xadddw \[%r1\+0xaa\],%r2 diff --git a/gas/testsuite/gas/bpf/pseudoc-normal.d b/gas/testsuite/gas/bpf/pseudoc-normal.d deleted file mode 100644 index 5bece2a..0000000 --- a/gas/testsuite/gas/bpf/pseudoc-normal.d +++ /dev/null @@ -1,214 +0,0 @@ -#as: --EL -#objdump: -dr -#source: pseudoc-normal.s -#name: eBPF clang (pseudo-C)/gas (normal) instructions - -.*: +file format .*bpf.* - -Disassembly of section .text: - -0+ <beg>: - 0: 07 01 00 00 aa 00 00 00 add %r1,0xaa - 8: 07 01 00 00 aa 00 00 00 add %r1,0xaa - 10: 0f 21 00 00 00 00 00 00 add %r1,%r2 - 18: 0f 21 00 00 00 00 00 00 add %r1,%r2 - 20: 17 01 00 00 aa 00 00 00 sub %r1,0xaa - 28: 17 01 00 00 aa 00 00 00 sub %r1,0xaa - 30: 1f 21 00 00 00 00 00 00 sub %r1,%r2 - 38: 1f 21 00 00 00 00 00 00 sub %r1,%r2 - 40: 27 01 00 00 aa 00 00 00 mul %r1,0xaa - 48: 27 01 00 00 aa 00 00 00 mul %r1,0xaa - 50: 2f 21 00 00 00 00 00 00 mul %r1,%r2 - 58: 2f 21 00 00 00 00 00 00 mul %r1,%r2 - 60: 37 01 00 00 aa 00 00 00 div %r1,0xaa - 68: 37 01 00 00 aa 00 00 00 div %r1,0xaa - 70: 3f 21 00 00 00 00 00 00 div %r1,%r2 - 78: 3f 21 00 00 00 00 00 00 div %r1,%r2 - 80: 47 01 00 00 aa 00 00 00 or %r1,0xaa - 88: 47 01 00 00 aa 00 00 00 or %r1,0xaa - 90: 4f 21 00 00 00 00 00 00 or %r1,%r2 - 98: 4f 21 00 00 00 00 00 00 or %r1,%r2 - a0: 57 01 00 00 aa 00 00 00 and %r1,0xaa - a8: 57 01 00 00 aa 00 00 00 and %r1,0xaa - b0: 5f 21 00 00 00 00 00 00 and %r1,%r2 - b8: 5f 21 00 00 00 00 00 00 and %r1,%r2 - c0: 67 01 00 00 aa 00 00 00 lsh %r1,0xaa - c8: 67 01 00 00 aa 00 00 00 lsh %r1,0xaa - d0: 6f 21 00 00 00 00 00 00 lsh %r1,%r2 - d8: 6f 21 00 00 00 00 00 00 lsh %r1,%r2 - e0: 77 01 00 00 aa 00 00 00 rsh %r1,0xaa - e8: 77 01 00 00 aa 00 00 00 rsh %r1,0xaa - f0: 7f 21 00 00 00 00 00 00 rsh %r1,%r2 - f8: 7f 21 00 00 00 00 00 00 rsh %r1,%r2 - 100: a7 01 00 00 aa 00 00 00 xor %r1,0xaa - 108: a7 01 00 00 aa 00 00 00 xor %r1,0xaa - 110: af 21 00 00 00 00 00 00 xor %r1,%r2 - 118: af 21 00 00 00 00 00 00 xor %r1,%r2 - 120: b7 01 00 00 aa 00 00 00 mov %r1,0xaa - 128: b7 01 00 00 aa 00 00 00 mov %r1,0xaa - 130: bf 21 00 00 00 00 00 00 mov %r1,%r2 - 138: bf 21 00 00 00 00 00 00 mov %r1,%r2 - 140: c7 01 00 00 aa 00 00 00 arsh %r1,0xaa - 148: c7 01 00 00 aa 00 00 00 arsh %r1,0xaa - 150: cf 21 00 00 00 00 00 00 arsh %r1,%r2 - 158: cf 21 00 00 00 00 00 00 arsh %r1,%r2 - 160: 87 01 00 00 00 00 00 00 neg %r1 - 168: 87 01 00 00 00 00 00 00 neg %r1 - 170: 04 01 00 00 aa 00 00 00 add32 %r1,0xaa - 178: 04 01 00 00 aa 00 00 00 add32 %r1,0xaa - 180: 0c 21 00 00 00 00 00 00 add32 %r1,%r2 - 188: 0c 21 00 00 00 00 00 00 add32 %r1,%r2 - 190: 14 01 00 00 aa 00 00 00 sub32 %r1,0xaa - 198: 14 01 00 00 aa 00 00 00 sub32 %r1,0xaa - 1a0: 1c 21 00 00 00 00 00 00 sub32 %r1,%r2 - 1a8: 1c 21 00 00 00 00 00 00 sub32 %r1,%r2 - 1b0: 24 01 00 00 aa 00 00 00 mul32 %r1,0xaa - 1b8: 24 01 00 00 aa 00 00 00 mul32 %r1,0xaa - 1c0: 2c 21 00 00 00 00 00 00 mul32 %r1,%r2 - 1c8: 2c 21 00 00 00 00 00 00 mul32 %r1,%r2 - 1d0: 34 01 00 00 aa 00 00 00 div32 %r1,0xaa - 1d8: 34 01 00 00 aa 00 00 00 div32 %r1,0xaa - 1e0: 3c 21 00 00 00 00 00 00 div32 %r1,%r2 - 1e8: 3c 21 00 00 00 00 00 00 div32 %r1,%r2 - 1f0: 44 01 00 00 aa 00 00 00 or32 %r1,0xaa - 1f8: 44 01 00 00 aa 00 00 00 or32 %r1,0xaa - 200: 4c 21 00 00 00 00 00 00 or32 %r1,%r2 - 208: 4c 21 00 00 00 00 00 00 or32 %r1,%r2 - 210: 54 01 00 00 aa 00 00 00 and32 %r1,0xaa - 218: 54 01 00 00 aa 00 00 00 and32 %r1,0xaa - 220: 5c 21 00 00 00 00 00 00 and32 %r1,%r2 - 228: 5c 21 00 00 00 00 00 00 and32 %r1,%r2 - 230: 64 01 00 00 aa 00 00 00 lsh32 %r1,0xaa - 238: 64 01 00 00 aa 00 00 00 lsh32 %r1,0xaa - 240: 6c 21 00 00 00 00 00 00 lsh32 %r1,%r2 - 248: 6c 21 00 00 00 00 00 00 lsh32 %r1,%r2 - 250: 74 01 00 00 aa 00 00 00 rsh32 %r1,0xaa - 258: 74 01 00 00 aa 00 00 00 rsh32 %r1,0xaa - 260: 7c 21 00 00 00 00 00 00 rsh32 %r1,%r2 - 268: 7c 21 00 00 00 00 00 00 rsh32 %r1,%r2 - 270: a4 01 00 00 aa 00 00 00 xor32 %r1,0xaa - 278: a4 01 00 00 aa 00 00 00 xor32 %r1,0xaa - 280: ac 21 00 00 00 00 00 00 xor32 %r1,%r2 - 288: ac 21 00 00 00 00 00 00 xor32 %r1,%r2 - 290: b4 01 00 00 aa 00 00 00 mov32 %r1,0xaa - 298: b4 01 00 00 aa 00 00 00 mov32 %r1,0xaa - 2a0: bc 21 00 00 00 00 00 00 mov32 %r1,%r2 - 2a8: bc 21 00 00 00 00 00 00 mov32 %r1,%r2 - 2b0: c4 01 00 00 aa 00 00 00 arsh32 %r1,0xaa - 2b8: c4 01 00 00 aa 00 00 00 arsh32 %r1,0xaa - 2c0: cc 21 00 00 00 00 00 00 arsh32 %r1,%r2 - 2c8: cc 21 00 00 00 00 00 00 arsh32 %r1,%r2 - 2d0: 84 01 00 00 00 00 00 00 neg32 %r1 - 2d8: 84 01 00 00 00 00 00 00 neg32 %r1 - 2e0: d4 01 00 00 10 00 00 00 endle %r1,16 - 2e8: d4 01 00 00 10 00 00 00 endle %r1,16 - 2f0: d4 01 00 00 20 00 00 00 endle %r1,32 - 2f8: d4 01 00 00 20 00 00 00 endle %r1,32 - 300: d4 01 00 00 40 00 00 00 endle %r1,64 - 308: d4 01 00 00 40 00 00 00 endle %r1,64 - 310: dc 01 00 00 10 00 00 00 endbe %r1,16 - 318: dc 01 00 00 10 00 00 00 endbe %r1,16 - 320: dc 01 00 00 20 00 00 00 endbe %r1,32 - 328: dc 01 00 00 20 00 00 00 endbe %r1,32 - 330: dc 01 00 00 40 00 00 00 endbe %r1,64 - 338: dc 01 00 00 40 00 00 00 endbe %r1,64 - 340: 71 21 aa 00 00 00 00 00 ldxb %r1,\[%r2\+0xaa\] - 348: 71 21 aa 00 00 00 00 00 ldxb %r1,\[%r2\+0xaa\] - 350: 69 21 aa 00 00 00 00 00 ldxh %r1,\[%r2\+0xaa\] - 358: 69 21 aa 00 00 00 00 00 ldxh %r1,\[%r2\+0xaa\] - 360: 61 21 aa 00 00 00 00 00 ldxw %r1,\[%r2\+0xaa\] - 368: 61 21 aa 00 00 00 00 00 ldxw %r1,\[%r2\+0xaa\] - 370: 79 21 aa 00 00 00 00 00 ldxdw %r1,\[%r2\+0xaa\] - 378: 79 21 aa 00 00 00 00 00 ldxdw %r1,\[%r2\+0xaa\] - 380: 73 21 aa 00 00 00 00 00 stxb \[%r1\+0xaa\],%r2 - 388: 73 21 aa 00 00 00 00 00 stxb \[%r1\+0xaa\],%r2 - 390: 6b 21 aa 00 00 00 00 00 stxh \[%r1\+0xaa\],%r2 - 398: 6b 21 aa 00 00 00 00 00 stxh \[%r1\+0xaa\],%r2 - 3a0: 63 21 aa 00 00 00 00 00 stxw \[%r1\+0xaa\],%r2 - 3a8: 63 21 aa 00 00 00 00 00 stxw \[%r1\+0xaa\],%r2 - 3b0: 7b 21 aa 00 00 00 00 00 stxdw \[%r1\+0xaa\],%r2 - 3b8: 7b 21 aa 00 00 00 00 00 stxdw \[%r1\+0xaa\],%r2 - 3c0: 05 00 bb 00 00 00 00 00 ja 187 - 3c8: 05 00 bb 00 00 00 00 00 ja 187 - 3d0: 15 01 bb 00 aa 00 00 00 jeq %r1,0xaa,187 - 3d8: 15 01 bb 00 aa 00 00 00 jeq %r1,0xaa,187 - 3e0: 1d 21 bb 00 00 00 00 00 jeq %r1,%r2,187 - 3e8: 1d 21 bb 00 00 00 00 00 jeq %r1,%r2,187 - 3f0: 25 01 bb 00 aa 00 00 00 jgt %r1,0xaa,187 - 3f8: 25 01 bb 00 aa 00 00 00 jgt %r1,0xaa,187 - 400: 2d 21 bb 00 00 00 00 00 jgt %r1,%r2,187 - 408: 2d 21 bb 00 00 00 00 00 jgt %r1,%r2,187 - 410: 35 01 bb 00 aa 00 00 00 jge %r1,0xaa,187 - 418: 35 01 bb 00 aa 00 00 00 jge %r1,0xaa,187 - 420: 3d 21 bb 00 00 00 00 00 jge %r1,%r2,187 - 428: 3d 21 bb 00 00 00 00 00 jge %r1,%r2,187 - 430: a5 01 bb 00 aa 00 00 00 jlt %r1,0xaa,187 - 438: a5 01 bb 00 aa 00 00 00 jlt %r1,0xaa,187 - 440: ad 21 bb 00 00 00 00 00 jlt %r1,%r2,187 - 448: ad 21 bb 00 00 00 00 00 jlt %r1,%r2,187 - 450: b5 01 bb 00 aa 00 00 00 jle %r1,0xaa,187 - 458: b5 01 bb 00 aa 00 00 00 jle %r1,0xaa,187 - 460: bd 21 bb 00 00 00 00 00 jle %r1,%r2,187 - 468: bd 21 bb 00 00 00 00 00 jle %r1,%r2,187 - 470: 45 01 bb 00 aa 00 00 00 jset %r1,0xaa,187 - 478: 45 01 bb 00 aa 00 00 00 jset %r1,0xaa,187 - 480: 4d 21 bb 00 00 00 00 00 jset %r1,%r2,187 - 488: 4d 21 bb 00 00 00 00 00 jset %r1,%r2,187 - 490: 55 01 bb 00 aa 00 00 00 jne %r1,0xaa,187 - 498: 55 01 bb 00 aa 00 00 00 jne %r1,0xaa,187 - 4a0: 5d 21 bb 00 00 00 00 00 jne %r1,%r2,187 - 4a8: 5d 21 bb 00 00 00 00 00 jne %r1,%r2,187 - 4b0: 65 01 bb 00 aa 00 00 00 jsgt %r1,0xaa,187 - 4b8: 65 01 bb 00 aa 00 00 00 jsgt %r1,0xaa,187 - 4c0: 6d 21 bb 00 00 00 00 00 jsgt %r1,%r2,187 - 4c8: 6d 21 bb 00 00 00 00 00 jsgt %r1,%r2,187 - 4d0: 75 01 bb 00 aa 00 00 00 jsge %r1,0xaa,187 - 4d8: 75 01 bb 00 aa 00 00 00 jsge %r1,0xaa,187 - 4e0: 7d 21 bb 00 00 00 00 00 jsge %r1,%r2,187 - 4e8: 7d 21 bb 00 00 00 00 00 jsge %r1,%r2,187 - 4f0: c5 01 bb 00 aa 00 00 00 jslt %r1,0xaa,187 - 4f8: c5 01 bb 00 aa 00 00 00 jslt %r1,0xaa,187 - 500: cd 21 bb 00 00 00 00 00 jslt %r1,%r2,187 - 508: cd 21 bb 00 00 00 00 00 jslt %r1,%r2,187 - 510: d5 01 bb 00 aa 00 00 00 jsle %r1,0xaa,187 - 518: d5 01 bb 00 aa 00 00 00 jsle %r1,0xaa,187 - 520: dd 21 bb 00 00 00 00 00 jsle %r1,%r2,187 - 528: dd 21 bb 00 00 00 00 00 jsle %r1,%r2,187 - 530: 85 00 00 00 aa 00 00 00 call 170 - 538: 85 00 00 00 aa 00 00 00 call 170 - 540: 95 00 00 00 00 00 00 00 exit - 548: 95 00 00 00 00 00 00 00 exit - 550: b7 06 00 00 20 06 00 00 mov %r6,0x620 - 558: 95 00 00 00 00 00 00 00 exit - 560: 20 00 00 00 aa 00 00 00 ldabsw 0xaa - 568: 20 00 00 00 aa 00 00 00 ldabsw 0xaa - 570: 50 70 00 00 aa 00 00 00 ldindb %r7,0xaa - 578: 50 70 00 00 aa 00 00 00 ldindb %r7,0xaa - 580: 20 00 00 00 aa 00 00 00 ldabsw 0xaa - 588: 20 00 00 00 aa 00 00 00 ldabsw 0xaa - 590: 50 70 00 00 aa 00 00 00 ldindb %r7,0xaa - 598: 50 70 00 00 aa 00 00 00 ldindb %r7,0xaa - 5a0: 18 03 00 00 01 00 00 00 lddw %r3,1 - 5a8: 00 00 00 00 00 00 00 00 - 5b0: 18 03 00 00 01 00 00 00 lddw %r3,1 - 5b8: 00 00 00 00 00 00 00 00 - 5c0: 18 04 00 00 88 77 ff ee lddw %r4,-6144092013047351416 - 5c8: 00 00 00 00 dd cc bb aa - 5d0: 18 04 00 00 88 77 ff ee lddw %r4,-6144092013047351416 - 5d8: 00 00 00 00 dd cc bb aa - 5e0: 18 05 00 00 88 77 66 55 lddw %r5,0x1122334455667788 - 5e8: 00 00 00 00 44 33 22 11 - 5f0: 18 05 00 00 88 77 66 55 lddw %r5,0x1122334455667788 - 5f8: 00 00 00 00 44 33 22 11 - 600: 18 06 00 00 20 06 00 00 lddw %r6,0x620 - 608: 00 00 00 00 00 00 00 00 - 600: R_BPF_64_64 .text - 610: 18 06 00 00 20 06 00 00 lddw %r6,0x620 - 618: 00 00 00 00 00 00 00 00 - 610: R_BPF_64_64 .text - -0000000000000620 <main>: - 620: c3 21 aa 00 00 00 00 00 xaddw \[%r1\+0xaa\],%r2 - 628: c3 21 aa 00 00 00 00 00 xaddw \[%r1\+0xaa\],%r2 - 630: db 21 aa 00 00 00 00 00 xadddw \[%r1\+0xaa\],%r2 - 638: db 21 aa 00 00 00 00 00 xadddw \[%r1\+0xaa\],%r2 diff --git a/gas/testsuite/gas/bpf/pseudoc-normal.s b/gas/testsuite/gas/bpf/pseudoc-normal.s deleted file mode 100644 index b3467d1..0000000 --- a/gas/testsuite/gas/bpf/pseudoc-normal.s +++ /dev/null @@ -1,196 +0,0 @@ -# Tests for mixing pseudo-C and normal eBPF instructions -beg: - .text - add %r1,0xaa - r1 += 0xaa - add %r1,%r2 - r1 += r2 - sub %r1,0xaa - r1 -= 0xaa - sub %r1,%r2 - r1 -= r2 - mul %r1,0xaa - r1 *= 0xaa - mul %r1,%r2 - r1 *= r2 - div %r1,0xaa - r1 /= 0xaa - div %r1,%r2 - r1 /= r2 - or %r1,0xaa - r1 |= 0xaa - or %r1,%r2 - r1 |= r2 - and %r1,0xaa - r1 &= 0xaa - and %r1,%r2 - r1 &= r2 - lsh %r1,0xaa - r1 <<= 0xaa - lsh %r1,%r2 - r1 <<= r2 - rsh %r1,0xaa - r1 >>= 0xaa - rsh %r1,%r2 - r1 >>= r2 - xor %r1,0xaa - r1 ^= 0xaa - xor %r1,%r2 - r1 ^= r2 - mov %r1,0xaa - r1 = 0xaa - mov %r1,%r2 - r1 = r2 - arsh %r1,0xaa - r1 s>>= 0xaa - arsh %r1,%r2 - r1 s>>= r2 - neg %r1 - r1 = -r1 - add32 %r1,0xaa - w1 += 0xaa - add32 %r1,%r2 - w1 += w2 - sub32 %r1,0xaa - w1 -= 0xaa - sub32 %r1,%r2 - w1 -= w2 - mul32 %r1,0xaa - w1 *= 0xaa - mul32 %r1,%r2 - w1 *= w2 - div32 %r1,0xaa - w1 /= 0xaa - div32 %r1,%r2 - w1 /= w2 - or32 %r1,0xaa - w1 |= 0xaa - or32 %r1,%r2 - w1 |= w2 - and32 %r1,0xaa - w1 &= 0xaa - and32 %r1,%r2 - w1 &= w2 - lsh32 %r1,0xaa - w1 <<= 0xaa - lsh32 %r1,%r2 - w1 <<= w2 - rsh32 %r1,0xaa - w1 >>= 0xaa - rsh32 %r1,%r2 - w1 >>= w2 - xor32 %r1,0xaa - w1 ^= 0xaa - xor32 %r1,%r2 - w1 ^= w2 - mov32 %r1,0xaa - w1 = 0xaa - mov32 %r1,%r2 - w1 = w2 - arsh32 %r1,0xaa - w1 s>>= 0xaa - arsh32 %r1,%r2 - w1 s>>= w2 - neg32 %r1 - w1 = -w1 - endle %r1,16 - r1 = le16 r1 - endle %r1,32 - r1 = le32 r1 - endle %r1,64 - r1 = le64 r1 - endbe %r1,16 - r1 = be16 r1 - endbe %r1,32 - r1 = be32 r1 - endbe %r1,64 - r1 = be64 r1 - ldxb %r1,[%r2+0xaa] - r1 = *(u8 *)(r2 + 0xaa) - ldxh %r1,[%r2+0xaa] - r1 = *(u16 *)(r2 + 0xaa) - ldxw %r1,[%r2+0xaa] - r1 = *(u32 *)(r2 + 0xaa) - ldxdw %r1,[%r2+0xaa] - r1 = *(u64 *)(r2 + 0xaa) - stxb [%r1+0xaa],%r2 - *(u8 *)(r1 + 0xaa) = r2 - stxh [%r1+0xaa],%r2 - *(u16 *)(r1 + 0xaa) = r2 - stxw [%r1+0xaa],%r2 - *(u32 *)(r1 + 0xaa) = r2 - stxdw [%r1+0xaa],%r2 - *(u64 *)(r1 + 0xaa) = r2 - ja 187 - goto 0xbb - jeq %r1,0xaa,187 - if r1 == 0xaa goto 0xbb - jeq %r1,%r2,187 - if r1 == r2 goto 0xbb - jgt %r1,0xaa,187 - if r1 > 0xaa goto 0xbb - jgt %r1,%r2,187 - if r1 > r2 goto 0xbb - jge %r1,0xaa,187 - if r1 >= 0xaa goto 0xbb - jge %r1,%r2,187 - if r1 >= r2 goto 0xbb - jlt %r1,0xaa,187 - if r1 < 0xaa goto 0xbb - jlt %r1,%r2,187 - if r1 < r2 goto 0xbb - jle %r1,0xaa,187 - if r1 <= 0xaa goto 0xbb - jle %r1,%r2,187 - if r1 <= r2 goto 0xbb - jset %r1,0xaa,187 - if r1 & 0xaa goto 0xbb - jset %r1,%r2,187 - if r1 & r2 goto 0xbb - jne %r1,0xaa,187 - if r1 != 0xaa goto 0xbb - jne %r1,%r2,187 - if r1 != r2 goto 0xbb - jsgt %r1,0xaa,187 - if r1 s> 0xaa goto 0xbb - jsgt %r1,%r2,187 - if r1 s> r2 goto 0xbb - jsge %r1,0xaa,187 - if r1 s>= 0xaa goto 0xbb - jsge %r1,%r2,187 - if r1 s>= r2 goto 0xbb - jslt %r1,0xaa,187 - if r1 s< 0xaa goto 0xbb - jslt %r1,%r2,187 - if r1 s< r2 goto 0xbb - jsle %r1,0xaa,187 - if r1 s<= 0xaa goto 0xbb - jsle %r1,%r2,187 - if r1 s<= r2 goto 0xbb - call 170 - call 0xaa - exit - exit - mov %r6,main - beg - exit - ldabsw 0xaa - r0 = *(u32 *)skb[0xaa] - ldindb %r7,0xaa - r0 = *(u8 *)skb[r7 + 0xaa] - ldabsw 0xaa - r0 = *(u32 *)skb[0xaa] - ldindb %r7,0xaa - r0 = *(u8 *)skb[r7 + 0xaa] - lddw %r3,1 - r3 = 1 ll - lddw %r4,0xaabbccddeeff7788 - r4 = 0xaabbccddeeff7788 ll - r5 = 0x1122334455667788 ll - lddw %r5,0x1122334455667788 - lddw %r6,main - r6 = main ll - main: - lock *(u32 *)(r1 + 0xaa) += r2 - xaddw [%r1+0xaa],%r2 - lock *(u64 *)(r1 + 0xaa) += r2 - xadddw [%r1+0xaa],%r2 diff --git a/gas/testsuite/gas/bpf/spacing-pseudoc.d b/gas/testsuite/gas/bpf/spacing-pseudoc.d new file mode 100644 index 0000000..16f5763 --- /dev/null +++ b/gas/testsuite/gas/bpf/spacing-pseudoc.d @@ -0,0 +1,18 @@ +#as: -EB -mdialect=pseudoc +#source: spacing-pseudoc.s +#objdump: -dr -M hex,pseudoc +#name: spacing, pseudoc syntax + +.*: +file format .*bpf.* + +Disassembly of section .text: + +0+ <.text>: + 0: b7 04 00 00 ef be ad de r4=0xdeadbeef + 8: 18 04 00 00 ef be ad de r4=0xdeadbeef ll + 10: 00 00 00 00 00 00 00 00 + 18: 05 00 01 00 00 00 00 00 goto 0x1 + 20: 05 00 01 00 00 00 00 00 goto 0x1 + 28: 05 00 01 00 00 00 00 00 goto 0x1 + 30: 16 03 01 00 03 00 00 00 if w3==0x3 goto 0x1 + 38: 16 03 01 00 03 00 00 00 if w3==0x3 goto 0x1 diff --git a/gas/testsuite/gas/bpf/spacing-pseudoc.s b/gas/testsuite/gas/bpf/spacing-pseudoc.s new file mode 100644 index 0000000..3c19d9a --- /dev/null +++ b/gas/testsuite/gas/bpf/spacing-pseudoc.s @@ -0,0 +1,9 @@ + ;; This test checks that flexible spacing is supported in the + ;; pseudoc syntax. + r4 = 0xdeadbeefll + r4 = 0xdeadbeef ll + goto +1 + goto+1 + goto1 + if w3==3 goto+1 + if w3==3 goto1 |