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-rw-r--r--gas/ChangeLog8
-rw-r--r--gas/config/tc-i386.c15
-rw-r--r--gas/config/tc-i386.h3
-rw-r--r--gas/testsuite/ChangeLog7
-rw-r--r--gas/testsuite/gas/i386/i386.exp1
-rw-r--r--gas/testsuite/gas/i386/prescott.d37
-rw-r--r--gas/testsuite/gas/i386/prescott.s34
7 files changed, 104 insertions, 1 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 2368504..04997b0 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2003-06-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/config/tc-i386.c (md_assemble): Support Intel Precott New
+ Instructions.
+
+ * gas/config/tc-i386.h (CpuPNI): New.
+ (CpuUnknownFlags): Add CpuPNI.
+
2003-06-23 <davidm@hpl.hp.com>
* config/tc-ia64.c (pseudo_func): Add ABI constants for linux,
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index a10d9e6..5ac7e0c 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1413,6 +1413,21 @@ md_assemble (line)
if (i.tm.opcode_modifier & ImmExt)
{
+ if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
+ {
+ /* These Intel Precott New Instructions have the fixed
+ operands with an opcode suffix which is coded in the same
+ place as an 8-bit immediate field would be. Here we check
+ those operands and remove them afterwards. */
+ unsigned int x;
+
+ for (x = 0; x < i.operands; x++)
+ if (i.op[x].regs->reg_num != x)
+ as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
+ i.op[x].regs->reg_name, x + 1, i.tm.name);
+ i.operands = 0;
+ }
+
/* These AMD 3DNow! and Intel Katmai New Instructions have an
opcode suffix which is coded in the same place as an 8-bit
immediate field would be. Here we fake an 8-bit immediate
diff --git a/gas/config/tc-i386.h b/gas/config/tc-i386.h
index 295ccb9..5b93dbe 100644
--- a/gas/config/tc-i386.h
+++ b/gas/config/tc-i386.h
@@ -243,13 +243,14 @@ typedef struct
#define CpuSSE 0x1000 /* Streaming SIMD extensions required */
#define CpuSSE2 0x2000 /* Streaming SIMD extensions 2 required */
#define Cpu3dnow 0x4000 /* 3dnow! support required */
+#define CpuPNI 0x8000 /* Prescott New Instuctions required */
/* These flags are set by gas depending on the flag_code. */
#define Cpu64 0x4000000 /* 64bit support required */
#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
/* The default value for unknown CPUs - enable all features to avoid problems. */
-#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|Cpu3dnow|CpuK6|CpuAthlon)
+#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|CpuPNI|Cpu3dnow|CpuK6|CpuAthlon)
/* the bits in opcode_modifier are used to generate the final opcode from
the base_opcode. These bits also are used to detect alternate forms of
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index adbdc8f..967c85a 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2003-06-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/i386.exp: Add prescott.
+
+ * gas/i386/prescott.d: New file.
+ * gas/i386/prescott.s: Likewise.
+
2003-06-21 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
* gas/mips/elf-rel-got-n32.d: Remove special handling for n32 ABI.
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index cf87c5e..04bf95e 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -56,6 +56,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "absrel"
run_dump_test "pcrel"
run_dump_test "sub"
+ run_dump_test "prescott"
# PIC is only supported on ELF targets.
if { ([istarget "*-*-elf*"] || [istarget "*-*-linux*"] )
diff --git a/gas/testsuite/gas/i386/prescott.d b/gas/testsuite/gas/i386/prescott.d
new file mode 100644
index 0000000..9c5ba92
--- /dev/null
+++ b/gas/testsuite/gas/i386/prescott.d
@@ -0,0 +1,37 @@
+#objdump: -dw
+#name: i386 prescott
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <foo>:
+ 0: 66 0f d0 01 [ ]*addsubpd \(%ecx\),%xmm0
+ 4: 66 0f d0 ca [ ]*addsubpd %xmm2,%xmm1
+ 8: f2 0f d0 13 [ ]*addsubps \(%ebx\),%xmm2
+ c: f2 0f d0 dc [ ]*addsubps %xmm4,%xmm3
+ 10: df 88 90 90 90 90 [ ]*fisttp 0x90909090\(%eax\)
+ 16: db 88 90 90 90 90 [ ]*fisttpl 0x90909090\(%eax\)
+ 1c: dd 88 90 90 90 90 [ ]*fisttpll 0x90909090\(%eax\)
+ 22: dd 88 90 90 90 90 [ ]*fisttpll 0x90909090\(%eax\)
+ 28: dd 88 90 90 90 90 [ ]*fisttpll 0x90909090\(%eax\)
+ 2e: 66 0f 7c 65 00 [ ]*haddpd 0x0\(%ebp\),%xmm4
+ 33: 66 0f 7c ee [ ]*haddpd %xmm6,%xmm5
+ 37: f2 0f 7c 37 [ ]*haddps \(%edi\),%xmm6
+ 3b: f2 0f 7c f8 [ ]*haddps %xmm0,%xmm7
+ 3f: 66 0f 7d c1 [ ]*hsubpd %xmm1,%xmm0
+ 43: 66 0f 7d 0a [ ]*hsubpd \(%edx\),%xmm1
+ 47: f2 0f 7d d2 [ ]*hsubps %xmm2,%xmm2
+ 4b: f2 0f 7d 1c 24 [ ]*hsubps \(%esp,1\),%xmm3
+ 50: f2 0f f0 2e [ ]*lddqu \(%esi\),%xmm5
+ 54: 0f 01 c8 [ ]*monitor %eax,%ecx,%edx
+ 57: 0f 01 c8 [ ]*monitor %eax,%ecx,%edx
+ 5a: f2 0f 12 f7 [ ]*movddup %xmm7,%xmm6
+ 5e: f2 0f 12 38 [ ]*movddup \(%eax\),%xmm7
+ 62: f3 0f 16 01 [ ]*movshdup \(%ecx\),%xmm0
+ 66: f3 0f 16 ca [ ]*movshdup %xmm2,%xmm1
+ 6a: f3 0f 12 13 [ ]*movsldup \(%ebx\),%xmm2
+ 6e: f3 0f 12 dc [ ]*movsldup %xmm4,%xmm3
+ 72: 0f 01 c9 [ ]*mwait %eax,%ecx
+ 75: 0f 01 c9 [ ]*mwait %eax,%ecx
+ ...
diff --git a/gas/testsuite/gas/i386/prescott.s b/gas/testsuite/gas/i386/prescott.s
new file mode 100644
index 0000000..8a3651d
--- /dev/null
+++ b/gas/testsuite/gas/i386/prescott.s
@@ -0,0 +1,34 @@
+#Prescott New Instructions
+
+ .text
+foo:
+ addsubpd (%ecx),%xmm0
+ addsubpd %xmm2,%xmm1
+ addsubps (%ebx),%xmm2
+ addsubps %xmm4,%xmm3
+ fisttp 0x90909090(%eax)
+ fisttpl 0x90909090(%eax)
+ fisttpd 0x90909090(%eax)
+ fisttpq 0x90909090(%eax)
+ fisttpll 0x90909090(%eax)
+ haddpd 0x0(%ebp),%xmm4
+ haddpd %xmm6,%xmm5
+ haddps (%edi),%xmm6
+ haddps %xmm0,%xmm7
+ hsubpd %xmm1,%xmm0
+ hsubpd (%edx),%xmm1
+ hsubps %xmm2,%xmm2
+ hsubps (%esp,1),%xmm3
+ lddqu (%esi),%xmm5
+ monitor
+ monitor %eax,%ecx,%edx
+ movddup %xmm7,%xmm6
+ movddup (%eax),%xmm7
+ movshdup (%ecx),%xmm0
+ movshdup %xmm2,%xmm1
+ movsldup (%ebx),%xmm2
+ movsldup %xmm4,%xmm3
+ mwait
+ mwait %eax,%ecx
+
+ .p2align 4,0