diff options
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/ChangeLog | 23 | ||||
| -rw-r--r-- | gas/testsuite/gas/ppc/e6500.d | 8 |
2 files changed, 18 insertions, 13 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index dd4073a..bf5c3fc 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2012-08-20 Edmar Wienskoski <edmar@freescale.com> + + * gas/ppc/e6500.d: Changed opcode for vabsdub, vabsduh, vabsduw, + mviwsplt. + 2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com> * gas/i386/i386.exp: Run btver1 and btver2 test cases. @@ -36,15 +41,15 @@ * gas/mmix/err-fb-2.s: New test. 2012-08-13 Ian Bolton <ian.bolton@arm.com> - Laurent Desnogues <laurent.desnogues@arm.com> - Jim MacArthur <jim.macarthur@arm.com> - Marcus Shawcroft <marcus.shawcroft@arm.com> - Nigel Stephens <nigel.stephens@arm.com> - Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> - Richard Earnshaw <rearnsha@arm.com> - Sofiane Naci <sofiane.naci@arm.com> - Tejas Belagod <tejas.belagod@arm.com> - Yufeng Zhang <yufeng.zhang@arm.com> + Laurent Desnogues <laurent.desnogues@arm.com> + Jim MacArthur <jim.macarthur@arm.com> + Marcus Shawcroft <marcus.shawcroft@arm.com> + Nigel Stephens <nigel.stephens@arm.com> + Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + Richard Earnshaw <rearnsha@arm.com> + Sofiane Naci <sofiane.naci@arm.com> + Tejas Belagod <tejas.belagod@arm.com> + Yufeng Zhang <yufeng.zhang@arm.com> * gas/aarch64: New directory. * gas/aarch64/aarch64.exp: New file. diff --git a/gas/testsuite/gas/ppc/e6500.d b/gas/testsuite/gas/ppc/e6500.d index 892f144..079b35c 100644 --- a/gas/testsuite/gas/ppc/e6500.d +++ b/gas/testsuite/gas/ppc/e6500.d @@ -7,11 +7,11 @@ Disassembly of section \.text: 0+00 <start>: - 0: 10 01 10 c0 vabsdub v0,v1,v2 - 4: 10 01 11 00 vabsduh v0,v1,v2 - 8: 10 01 11 40 vabsduw v0,v1,v2 + 0: 10 01 14 03 vabsdub v0,v1,v2 + 4: 10 01 14 43 vabsduh v0,v1,v2 + 8: 10 01 14 83 vabsduw v0,v1,v2 c: 7c 01 10 dc mvidsplt v0,r1,r2 - 10: 7c 01 11 1c mviwsplt v0,r1,r2 + 10: 7c 01 10 5c mviwsplt v0,r1,r2 14: 7c 00 12 0a lvexbx v0,0,r2 18: 7c 01 12 0a lvexbx v0,r1,r2 1c: 7c 00 12 4a lvexhx v0,0,r2 |