diff options
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/ldst-reg-reg-offset.s | 6 |
3 files changed, 15 insertions, 0 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index c32ec63..345d396 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2014-02-27 Yufeng Zhang <yufeng.zhang@arm.com> + + * gas/aarch64/ldst-reg-reg-offset.s: Add tests. + * gas/aarch64/ldst-reg-reg-offset.d: Update. + 2014-02-21 Ilya Tocar <ilya.tocar@intel.com> * gas/i386/avx512pf-intel.d: Remove prefetchwt1. diff --git a/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d b/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d index 486d9c8..b720633 100644 --- a/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d +++ b/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d @@ -85,3 +85,7 @@ Disassembly of section \.text: 134: fc67fbe7 ldr d7, \[sp,x7,sxtx #3\] 138: 3ce7ebe7 ldr q7, \[sp,x7,sxtx\] 13c: 3ce7fbe7 ldr q7, \[sp,x7,sxtx #4\] + 140: f87ffbe1 ldr x1, \[sp,xzr,sxtx #3\] + 144: f83ffbe1 str x1, \[sp,xzr,sxtx #3\] + 148: b87fdbe1 ldr w1, \[sp,wzr,sxtw #2\] + 14c: b83fdbe1 str w1, \[sp,wzr,sxtw #2\] diff --git a/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.s b/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.s index afa7c4d..195c830 100644 --- a/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.s +++ b/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.s @@ -86,3 +86,9 @@ func: ld_or_st str ld_or_st ldr + + /* When the index register is of register 31, it should be ZR. */ + ldr x1, [sp, xzr, sxtx #3] + str x1, [sp, xzr, sxtx #3] + ldr w1, [sp, wzr, sxtw #2] + str w1, [sp, wzr, sxtw #2] |