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-rw-r--r--gas/testsuite/gas/arm/armv8_2-a.d51
-rw-r--r--gas/testsuite/gas/arm/armv8_2-a.s44
2 files changed, 95 insertions, 0 deletions
diff --git a/gas/testsuite/gas/arm/armv8_2-a.d b/gas/testsuite/gas/arm/armv8_2-a.d
new file mode 100644
index 0000000..92845de
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_2-a.d
@@ -0,0 +1,51 @@
+#name: ARMv8.2-A
+#objdump: -dr
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+ [0-9a-f]+: e320f010 esb
+
+[0-9a-f]+ <.*>:
+ [0-9a-f]+: f3af 8010 esb
+
+[0-9a-f]+ <.*>:
+ [0-9a-f]+: ee100f11 mrc 15, 0, r0, cr0, cr1, \{0\}
+ [0-9a-f]+: ee100fd2 mrc 15, 0, r0, cr0, cr2, \{6\}
+ [0-9a-f]+: ee150f13 mrc 15, 0, r0, cr5, cr3, \{0\}
+ [0-9a-f]+: ee150f33 mrc 15, 0, r0, cr5, cr3, \{1\}
+ [0-9a-f]+: ee051f33 mcr 15, 0, r1, cr5, cr3, \{1\}
+ [0-9a-f]+: ee150f14 mrc 15, 0, r0, cr5, cr4, \{0\}
+ [0-9a-f]+: ee150f34 mrc 15, 0, r0, cr5, cr4, \{1\}
+ [0-9a-f]+: ee051f34 mcr 15, 0, r1, cr5, cr4, \{1\}
+ [0-9a-f]+: ee150f54 mrc 15, 0, r0, cr5, cr4, \{2\}
+ [0-9a-f]+: ee051f54 mcr 15, 0, r1, cr5, cr4, \{2\}
+ [0-9a-f]+: ee150f74 mrc 15, 0, r0, cr5, cr4, \{3\}
+ [0-9a-f]+: ee051f74 mcr 15, 0, r1, cr5, cr4, \{3\}
+ [0-9a-f]+: ee150f94 mrc 15, 0, r0, cr5, cr4, \{4\}
+ [0-9a-f]+: ee150fb4 mrc 15, 0, r0, cr5, cr4, \{5\}
+ [0-9a-f]+: ee051fb4 mcr 15, 0, r1, cr5, cr4, \{5\}
+ [0-9a-f]+: ee150ff4 mrc 15, 0, r0, cr5, cr4, \{7\}
+ [0-9a-f]+: ee051ff4 mcr 15, 0, r1, cr5, cr4, \{7\}
+ [0-9a-f]+: ee150f15 mrc 15, 0, r0, cr5, cr5, \{0\}
+ [0-9a-f]+: ee051f15 mcr 15, 0, r1, cr5, cr5, \{0\}
+ [0-9a-f]+: ee150f35 mrc 15, 0, r0, cr5, cr5, \{1\}
+ [0-9a-f]+: ee051f35 mcr 15, 0, r1, cr5, cr5, \{1\}
+ [0-9a-f]+: ee150f95 mrc 15, 0, r0, cr5, cr5, \{4\}
+ [0-9a-f]+: ee051f95 mcr 15, 0, r1, cr5, cr5, \{4\}
+ [0-9a-f]+: ee150fb5 mrc 15, 0, r0, cr5, cr5, \{5\}
+ [0-9a-f]+: ee051fb5 mcr 15, 0, r1, cr5, cr5, \{5\}
+ [0-9a-f]+: ee1c0f31 mrc 15, 0, r0, cr12, cr1, \{1\}
+ [0-9a-f]+: ee0c1f31 mcr 15, 0, r1, cr12, cr1, \{1\}
+ [0-9a-f]+: ee910f91 mrc 15, 4, r0, cr1, cr1, \{4\}
+ [0-9a-f]+: ee811f91 mcr 15, 4, r1, cr1, cr1, \{4\}
+ [0-9a-f]+: ee950f72 mrc 15, 4, r0, cr5, cr2, \{3\}
+ [0-9a-f]+: ee851f72 mcr 15, 4, r1, cr5, cr2, \{3\}
+ [0-9a-f]+: ee910f31 mrc 15, 4, r0, cr1, cr1, \{1\}
+ [0-9a-f]+: ee811f31 mcr 15, 4, r1, cr1, cr1, \{1\}
+ [0-9a-f]+: ee9c0f31 mrc 15, 4, r0, cr12, cr1, \{1\}
+ [0-9a-f]+: ee8c1f31 mcr 15, 4, r1, cr12, cr1, \{1\}
+ [0-9a-f]+: eed10f11 mrc 15, 6, r0, cr1, cr1, \{0\}
+ [0-9a-f]+: eec11f11 mcr 15, 6, r1, cr1, cr1, \{0\}
diff --git a/gas/testsuite/gas/arm/armv8_2-a.s b/gas/testsuite/gas/arm/armv8_2-a.s
new file mode 100644
index 0000000..a27ac63
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_2-a.s
@@ -0,0 +1,44 @@
+ /* ARMv8.2 features. */
+
+ /* RAS instructions. */
+A1:
+ .arm
+ esb
+T1: .thumb
+ esb
+
+ /* RAS system registers. */
+ .macro test_sysreg Opc1 CRn CRm Opc2 rw
+ mrc p15, \Opc1,\() r0, \CRn\(), \CRm\(), \Opc2\()
+ .if \rw
+ mcr p15, \Opc1\(), r1, \CRn\(), \CRm\(), \Opc2\()
+ .endif
+ .endm
+
+A2:
+ .arm
+ test_sysreg 0 c0 c1 0 0
+ test_sysreg 0 c0 c2 6 0
+ test_sysreg 0 c5 c3 0 0
+ test_sysreg 0 c5 c3 1 1
+
+ test_sysreg 0 c5 c4 0 0
+ test_sysreg 0 c5 c4 1 1
+ test_sysreg 0 c5 c4 2 1
+ test_sysreg 0 c5 c4 3 1
+ test_sysreg 0 c5 c4 4 0
+ test_sysreg 0 c5 c4 5 1
+ test_sysreg 0 c5 c4 7 1
+
+ test_sysreg 0 c5 c5 0 1
+ test_sysreg 0 c5 c5 1 1
+ test_sysreg 0 c5 c5 4 1
+ test_sysreg 0 c5 c5 5 1
+
+ test_sysreg 0 c12 c1 1 1
+ test_sysreg 4 c1 c1 4 1
+ test_sysreg 4 c5 c2 3 1
+ test_sysreg 4 c1 c1 1 1
+ test_sysreg 4 c12 c1 1 1
+
+ test_sysreg 6 c1 c1 0 1