diff options
Diffstat (limited to 'gas/testsuite')
-rw-r--r-- | gas/testsuite/ChangeLog | 7 | ||||
-rw-r--r-- | gas/testsuite/gas/arm/shift-bad.d | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/arm/shift-bad.l | 6 | ||||
-rw-r--r-- | gas/testsuite/gas/arm/shift-bad.s | 10 |
4 files changed, 26 insertions, 0 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index db2ff76..8932f9a 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2011-06-13 Nick Clifton <nickc@redhat.com> + + PR gas/12854 + * gas/arm/shift-bad.s: New test. + * gas/arm/shift-bad.l: Expcted error output. + * gas/arm/shift-bad.s: New control file. + 2011-06-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-10-lzcnt.d: Updated. diff --git a/gas/testsuite/gas/arm/shift-bad.d b/gas/testsuite/gas/arm/shift-bad.d new file mode 100644 index 0000000..7d4cac1 --- /dev/null +++ b/gas/testsuite/gas/arm/shift-bad.d @@ -0,0 +1,3 @@ +# name: PR 12854: Extraneous shifts +# as: +# error-output: shift-bad.l diff --git a/gas/testsuite/gas/arm/shift-bad.l b/gas/testsuite/gas/arm/shift-bad.l new file mode 100644 index 0000000..6db9583 --- /dev/null +++ b/gas/testsuite/gas/arm/shift-bad.l @@ -0,0 +1,6 @@ +.*shift-bad.s: Assembler messages: +.*shift-bad.s:3: Error: extraneous shift as part of operand to shift insn -- `asr r0,r1,r2,ror#5' +.*shift-bad.s:4: Error: extraneous shift as part of operand to shift insn -- `ror r0,r1,r2,lsl r3' +.*shift-bad.s:8: Error: extraneous shift as part of operand to shift insn -- `ror r0,r1,r2,lsl#1' +.*shift-bad.s:9: Error: extraneous shift as part of operand to shift insn -- `lsl r0,r1,r2,lsl#1' +.*shift-bad.s:10: Error: extraneous shift as part of operand to shift insn -- `lsl r0,r1,r2,asr r0' diff --git a/gas/testsuite/gas/arm/shift-bad.s b/gas/testsuite/gas/arm/shift-bad.s new file mode 100644 index 0000000..6e6a795 --- /dev/null +++ b/gas/testsuite/gas/arm/shift-bad.s @@ -0,0 +1,10 @@ + .syntax unified + + asr r0, r1, r2, ror #5 + ror r0, r1, r2, lsl r3 + + .thumb_func +foo: + ror r0, r1, r2, lsl #1 + lsl r0, r1, r2, lsl #1 + lsl r0, r1, r2, asr r0 |