diff options
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/gas/all/itbl-test.c | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/tic4x/opclasses.h | 10 |
2 files changed, 6 insertions, 6 deletions
diff --git a/gas/testsuite/gas/all/itbl-test.c b/gas/testsuite/gas/all/itbl-test.c index 97b8601..f6f2fd3 100644 --- a/gas/testsuite/gas/all/itbl-test.c +++ b/gas/testsuite/gas/all/itbl-test.c @@ -116,7 +116,7 @@ test_reg (e_processor processor, e_type type, char *name, printf ("name=%s found for processor=%d, type=%d, val=%d\n", n, processor, type, val); - /* We require that names be unique amoung processors and types. */ + /* We require that names be unique among processors and types. */ if (! itbl_get_reg_val (name, &v) || v != val) printf ("Error - reg val not found for processor=%d, type=%d, name=%s\n", diff --git a/gas/testsuite/gas/tic4x/opclasses.h b/gas/testsuite/gas/tic4x/opclasses.h index 3fb3524..b12cc65 100644 --- a/gas/testsuite/gas/tic4x/opclasses.h +++ b/gas/testsuite/gas/tic4x/opclasses.h @@ -324,7 +324,7 @@ nameb##_J: &\ .endif -/* LL: Load-load parallell operation +/* LL: Load-load parallel operation Syntax: <i> src2, dst2 || <i> src1, dst1 src1 = Indirect 0,1,IR0,IR1 (J) dst1 = Register 0-7 (K) @@ -352,7 +352,7 @@ name##_LL_enh: &\ -/* LS: Store-store parallell operation +/* LS: Store-store parallel operation Syntax: <i> src2, dst2 || <i> src1, dst1 src1 = Register 0-7 (H) dst1 = Indirect 0,1,IR0,IR1 (J) @@ -645,7 +645,7 @@ nameb##3_##namea##3_M_enh: nameb##3 AR0, R0, R2 &|| namea##3 R0, AR0, R0 /* i;H;M|K;j;N */ &\ .endif -/* P: General 2-operand operation with parallell store +/* P: General 2-operand operation with parallel store Syntax: <ia> src2, dst1 || <ib> src3, dst2 src2 = Indirect 0,1,IR0,IR1, ENH: register (i) dst1 = Register 0-7 (L) @@ -671,7 +671,7 @@ namea##_##nameb##_P_enh: &\ .endif -/* Q: General 3-operand operation with parallell store +/* Q: General 3-operand operation with parallel store Syntax: <ia> src1, src2, dst1 || <ib> src3, dst2 src1 = Register 0-7 (K) src2 = Indirect 0,1,IR0,IR1, ENH: register (i) @@ -708,7 +708,7 @@ namea##3_##nameb##_Q_enh: .endif -/* QC: General commutative 3-operand operation with parallell store +/* QC: General commutative 3-operand operation with parallel store Syntax: <ia> src2, src1, dst1 || <ib> src3, dst2 <ia> src1, src2, dst1 || <ib> src3, dst2 - Manual src1 = Register 0-7 (K) |