diff options
Diffstat (limited to 'gas/doc')
| -rw-r--r-- | gas/doc/as.texinfo | 15 | ||||
| -rw-r--r-- | gas/doc/c-mips.texi | 19 |
2 files changed, 20 insertions, 14 deletions
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo index 251b6d5..f93c044 100644 --- a/gas/doc/as.texinfo +++ b/gas/doc/as.texinfo @@ -403,8 +403,8 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. [@b{-modd-spreg}] [@b{-mno-odd-spreg}] [@b{-march}=@var{CPU}] [@b{-mtune}=@var{CPU}] [@b{-mips1}] [@b{-mips2}] [@b{-mips3}] [@b{-mips4}] [@b{-mips5}] [@b{-mips32}] [@b{-mips32r2}] - [@b{-mips32r3}] [@b{-mips32r5}] [@b{-mips64}] [@b{-mips64r2}] - [@b{-mips64r3}] [@b{-mips64r5}] + [@b{-mips32r3}] [@b{-mips32r5}] [@b{-mips32r6}] [@b{-mips64}] [@b{-mips64r2}] + [@b{-mips64r3}] [@b{-mips64r5}] [@b{-mips64r6}] [@b{-construct-floats}] [@b{-no-construct-floats}] [@b{-mnan=@var{encoding}}] [@b{-trap}] [@b{-no-break}] [@b{-break}] [@b{-no-trap}] @@ -1277,19 +1277,22 @@ Generate ``little endian'' format output. @itemx -mips32r2 @itemx -mips32r3 @itemx -mips32r5 +@itemx -mips32r6 @itemx -mips64 @itemx -mips64r2 @itemx -mips64r3 @itemx -mips64r5 +@itemx -mips64r6 Generate code for a particular MIPS Instruction Set Architecture level. @samp{-mips1} is an alias for @samp{-march=r3000}, @samp{-mips2} is an alias for @samp{-march=r6000}, @samp{-mips3} is an alias for @samp{-march=r4000} and @samp{-mips4} is an alias for @samp{-march=r8000}. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3}, -@samp{-mips32r5}, @samp{-mips64}, @samp{-mips64r2}, @samp{-mips64r3}, and -@samp{-mips64r5} correspond to generic MIPS V, MIPS32, MIPS32 Release 2, -MIPS32 Release 3, MIPS32 Release 5, MIPS64, MIPS64 Release 2, -MIPS64 Release 3, and MIPS64 Release 5 ISA processors, respectively. +@samp{-mips32r5}, @samp{-mips32r6}, @samp{-mips64}, @samp{-mips64r2}, +@samp{-mips64r3}, @samp{-mips64r5}, and @samp{-mips64r6} correspond to generic +MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 +Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and +MIPS64 Release 6 ISA processors, respectively. @item -march=@var{cpu} Generate code for a particular MIPS CPU. diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi index 1e52e09..cafd832 100644 --- a/gas/doc/c-mips.texi +++ b/gas/doc/c-mips.texi @@ -84,21 +84,24 @@ VxWorks-style position-independent macro expansions. @itemx -mips32r2 @itemx -mips32r3 @itemx -mips32r5 +@itemx -mips32r6 @itemx -mips64 @itemx -mips64r2 @itemx -mips64r3 @itemx -mips64r5 +@itemx -mips64r6 Generate code for a particular MIPS Instruction Set Architecture level. @samp{-mips1} corresponds to the R2000 and R3000 processors, @samp{-mips2} to the R6000 processor, @samp{-mips3} to the R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors. -@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3}, -@samp{-mips32r5}, @samp{-mips64}, @samp{-mips64r2}, @samp{-mips64r3}, and -@samp{-mips64r5} correspond to generic MIPS V, MIPS32, MIPS32 Release 2, -MIPS32 Release 3, MIPS32 Release 5, MIPS64, and MIPS64 Release 2, -MIPS64 Release 3, and MIPS64 Release 5 ISA processors, respectively. You -can also switch instruction sets during the assembly; see @ref{MIPS ISA, -Directives to override the ISA level}. +@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3}, +@samp{-mips32r5}, @samp{-mips32r6}, @samp{-mips64}, @samp{-mips64r2}, +@samp{-mips64r3}, @samp{-mips64r5}, and @samp{-mips64r6} correspond to +generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 +Release 5, MIPS32 Release 6, MIPS64, and MIPS64 Release 2, MIPS64 +Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, +respectively. You can also switch instruction sets during the assembly; +see @ref{MIPS ISA, Directives to override the ISA level}. @item -mgp32 @itemx -mfp32 @@ -676,7 +679,7 @@ Small data is not supported for SVR4-style PIC. @sc{gnu} @code{@value{AS}} supports an additional directive to change the MIPS Instruction Set Architecture level on the fly: @code{.set mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 32r3, -32r5, 64, 64r2, 64r3 or 64r5. +32r5, 32r6, 64, 64r2, 64r3, 64r5 or 64r6. The values other than 0 make the assembler accept instructions for the corresponding ISA level, from that point on in the assembly. @code{.set mips@var{n}} affects not only which instructions |