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diff --git a/gas/doc/c-m68hc11.texi b/gas/doc/c-m68hc11.texi new file mode 100644 index 0000000..df80f8d --- /dev/null +++ b/gas/doc/c-m68hc11.texi @@ -0,0 +1,235 @@ +@c Copyright (C) 1991, 92, 93, 94, 95, 96, 1997 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC +@page +@node M68HC11-Dependent +@chapter M68HC11 and M68HC12 Dependent Features +@end ifset +@ifclear GENERIC +@node Machine Dependencies +@chapter M68HC11 and M68HC12 Dependent Features +@end ifclear + +@cindex M68HC11 and M68HC12 support +@menu +* M68HC11-Opts:: M68HC11 and M68HC12 Options +* M68HC11-Syntax:: Syntax +* M68HC11-Float:: Floating Point +* M68HC11-opcodes:: Opcodes +@end menu + +@node M68HC11-Opts +@section M68HC11 and M68HC12 Options + +@cindex options, M68HC11 +@cindex M68HC11 options +The Motorola 68HC11 and 68HC12 version of @code{@value{AS}} has a few machine +dependent options. + +@cindex @samp{-m68hc11} +This option switches the assembler in the M68HC11 mode. In this mode, +the assembler only accepts 68HC11 operands and mnemonics. It produces +code for the 68HC11. + +@cindex @samp{-m68hc12} +This option switches the assembler in the M68HC12 mode. In this mode, +the assembler also accepts 68HC12 operands and mnemonics. It produces +code for the 68HC12. A fiew 68HC11 instructions are replaced by +some 68HC12 instructions as recommended by Motorola specifications. + +@cindex @samp{--strict-direct-mode} +You can use the @samp{--strict-direct-mode} option to disable +the automatic translation of direct page mode addressing into +extended mode when the instruction does not support direct mode. +For example, the @samp{clr} instruction does not support direct page +mode addressing. When it is used with the direct page mode, +@code{@value{AS}} will ignore it and generate an absolute addressing. +This option prevents @code{@value{AS}} from doing this, and the wrong +usage of the direct page mode will raise an error. + +@cindex @samp{--short-branchs} +The @samp{--short-branchs} option turns off the translation of +relative branches into absolute branches when the branch offset is +out of range. By default @code{@value{AS}} transforms the relative +branch (@samp{bsr}, @samp{bgt}, @samp{bge}, @samp{beq}, @samp{bne}, +@samp{ble}, @samp{blt}, @samp{bhi}, @samp{bcc}, @samp{bls}, +@samp{bcs}, @samp{bmi}, @samp{bvs}, @samp{bvs}, @samp{bra}) into +an absolute branch when the offset is out of the -128 .. 127 range. +In that case, the @samp{bsr} instruction is translated into a +@samp{jsr}, the @samp{bra} instruction is translated into a +@samp{jmp} and the conditional branchs instructions are inverted and +followed by a @samp{jmp}. This option disables these translations +and @code{@value{AS}} will generate an error if a relative branch +is out of range. This option does not affect the optimization +associated to the @samp{jbra}, @samp{jbsr} and @samp{jbXX} pseudo opcodes. + +@cindex @samp{--force-long-branchs} +The @samp{--force-long-branchs} option forces the translation of +relative branches into absolute branches. This option does not affect +the optimization associated to the @samp{jbra}, @samp{jbsr} and +@samp{jbXX} pseudo opcodes. + +@cindex @samp{--print-insn-syntax} +You can use the @samp{--print-insn-syntax} option to obtain the +syntax description of the instruction when an error is detected. + +@cindex @samp{--print-opcodes} +The @samp{--print-opcodes} option prints the list of all the +instructions with their syntax. The first item of each line +represents the instruction name and the rest of the line indicates +the possible operands for that instruction. The list is printed +in alphabetical order. Once the list is printed @code{@value{AS}} +exits. + +@cindex @samp{--generate-example} +The @samp{--generate-example} option is similar to @samp{--print-opcodes} +but it generates an example for each instruction instead. + +@node M68HC11-Syntax +@section Syntax + +@cindex M68HC11 syntax +@cindex syntax, M68HC11 + +In the M68HC11 syntax, the instruction name comes first and it may +be followed by one or several operands (up to three). Operands are +separated by comma (@samp{,}). In the normal mode, +@code{@value{AS}} will complain if too many operands are specified for +a given instruction. In the MRI mode (turned on with @samp{-M} option), +it will treat them as comments. Example: + +@smallexample +inx +lda #23 +bset 2,x #4 +brclr *bot #8 foo +@end smallexample + +@cindex M68HC11 addressing modes +@cindex addressing modes, M68HC11 +The following addressing modes are understood: +@table @dfn +@item Immediate +@samp{#@var{number}} + +@item Address Register +@samp{@var{number},X}, @samp{@var{number},Y} + +The @var{number} may be omitted in which case 0 is assumed. + +@item Direct Addressing mode +@samp{*@var{symbol}}, or @samp{*@var{digits}} + +@item Absolute +@samp{@var{symbol}}, or @samp{@var{digits}} +@end table + +@node M68HC11-Float +@section Floating Point + +@cindex floating point, M68HC11 +@cindex M68HC11 floating point +Packed decimal (P) format floating literals are not supported. +Feel free to add the code! + +The floating point formats generated by directives are these. + +@table @code +@cindex @code{float} directive, M68HC11 +@item .float +@code{Single} precision floating point constants. + +@cindex @code{double} directive, M68HC11 +@item .double +@code{Double} precision floating point constants. + +@cindex @code{extend} directive M68HC11 +@cindex @code{ldouble} directive M68HC11 +@item .extend +@itemx .ldouble +@code{Extended} precision (@code{long double}) floating point constants. +@end table + +@need 2000 +@node M68HC11-opcodes +@section Opcodes + +@cindex M68HC11 opcodes +@cindex opcodes, M68HC11 +@cindex instruction set, M68HC11 + +@menu +* M68HC11-Branch:: Branch Improvement +@end menu + +@node M68HC11-Branch +@subsection Branch Improvement + +@cindex pseudo-opcodes, M68HC11 +@cindex M68HC11 pseudo-opcodes +@cindex branch improvement, M68HC11 +@cindex M68HC11 branch improvement + +Certain pseudo opcodes are permitted for branch instructions. +They expand to the shortest branch instruction that reach the +target. Generally these mnemonics are made by prepending @samp{j} to +the start of Motorola mnemonic. These pseudo opcodes are not affected +by the @samp{--short-branchs} or @samp{--force-long-branchs} options. + +The following table summarizes the pseudo-operations. + +@smallexample + Displacement Width + +-------------------------------------------------------------+ + | Options | + | --short-branchs --force-long-branchs | + +--------------------------+----------------------------------+ +Pseudo-Op |BYTE WORD | BYTE WORD | + +--------------------------+----------------------------------+ + bsr | bsr <pc-rel> <error> | jsr <abs> | + bra | bra <pc-rel> <error> | jmp <abs> | + jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> | + jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> | + bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> | + jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> | + | jmp <abs> | | + +--------------------------+----------------------------------+ +XX: condition +NX: negative of condition XX + +@end smallexample + +@table @code +@item jbsr +@itemx jbra +These are the simplest jump pseudo-operations; they always map to one +particular machine instruction, depending on the displacement to the +branch target. + +@item jb@var{XX} +Here, @samp{jb@var{XX}} stands for an entire family of pseudo-operations, +where @var{XX} is a conditional branch or condition-code test. The full +list of pseudo-ops in this family is: +@smallexample + jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo + jbcs jbne jblt jble jbls jbvc jbmi +@end smallexample + +For the cases of non-PC relative displacements and long displacements, +@code{@value{AS}} issues a longer code fragment in terms of +@var{NX}, the opposite condition to @var{XX}. For example, for the +non-PC relative case: +@smallexample + jb@var{XX} foo +@end smallexample +gives +@smallexample + b@var{NX}s oof + jmp foo + oof: +@end smallexample + +@end table + + |