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+@c Copyright (C) 2000 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@ifset GENERIC
+@page
+@node i860-Dependent
+@chapter Intel i860 Dependent Features
+@end ifset
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter Intel i860 Dependent Features
+@end ifclear
+
+@ignore
+@c FIXME: This is basically a stub for i860. There is tons more information
+that I will add later (jle@cygnus.com). The assembler is still being
+written. The i860 assembler that existed previously was never finished
+and doesn't even build. Further, its not BFD_ASSEMBLER and it doesn't
+do ELF (it doesn't do anything, but you get the point).
+@end ignore
+
+@cindex i860 support
+@menu
+* Options-i860::                i860 Command-line Options
+* Directives-i860::             i860 Machine Directives
+* Opcodes for i860::            i860 Opcodes
+@end menu
+
+@node Options-i860
+
+@section i860 Command-line Options
+@subsection SVR4 compatibility options 
+@table @code
+@item -V
+Print assembler version.
+@item -Qy
+Ignored.
+@item -Qn
+Ignored.
+@end table
+@subsection Other options 
+@table @code
+@item -EL
+Select little endian output (this is the default).
+@item -EB
+Select big endian output. Note that the i860 always reads instructions
+as little endian data, so this option only effects data and not
+instructions.
+@end table
+
+@node Directives-i860
+@section i860 Machine Directives
+
+@cindex machine directives, i860
+@cindex i860 machine directives
+
+@table @code
+@cindex @code{dual} directive, i860
+@item .dual
+Enter dual instruction mode. While this directive is supported, the
+preferred way to use dual instruction mode is to explicitly code
+the dual bit with the @code{d.} prefix.
+@end table
+
+@table @code
+@cindex @code{enddual} directive, i860
+@item .enddual
+Exit dual instruction mode. While this directive is supported, the
+preferred way to use dual instruction mode is to explicitly code
+the dual bit with the @code{d.} prefix.
+@end table
+
+@table @code
+@cindex @code{atmp} directive, i860
+@item .atmp
+Change the temporary register used when expanding pseudo operations. The
+default register is @code{r31}.
+@end table
+
+@node Opcodes for i860
+@section i860 Opcodes
+
+@cindex opcodes, i860
+@cindex i860 opcodes
+All of the Intel i860 machine instructions are supported.
+
+Some opcodes are processed beyond simply emitting a single corresponding
+instruction. For example, @samp{mov} and other instructions with larg
+displacements may be expanded into 2 or 3 instructions (FIXME: add details).
+