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diff --git a/gas/doc/as.info-4 b/gas/doc/as.info-4 deleted file mode 100644 index 4571cf8..0000000 --- a/gas/doc/as.info-4 +++ /dev/null @@ -1,874 +0,0 @@ -This is Info file as.info, produced by Makeinfo-1.55 from the input -file ./as.texinfo. - -START-INFO-DIR-ENTRY -* As:: The GNU assembler. -END-INFO-DIR-ENTRY - - This file documents the GNU Assembler "as". - - Copyright (C) 1991, 1992, 1993 Free Software Foundation, Inc. - - Permission is granted to make and distribute verbatim copies of this -manual provided the copyright notice and this permission notice are -preserved on all copies. - - Permission is granted to copy and distribute modified versions of -this manual under the conditions for verbatim copying, provided also -that the section entitled "GNU General Public License" is included -exactly as in the original, and provided that the entire resulting -derived work is distributed under the terms of a permission notice -identical to this one. - - Permission is granted to copy and distribute translations of this -manual into another language, under the above conditions for modified -versions, except that the section entitled "GNU General Public License" -may be included in a translation approved by the Free Software -Foundation instead of in the original English. - - -File: as.info, Node: M68K-Chars, Prev: M68K-Branch, Up: M68K-opcodes - -Special Characters -.................. - - The immediate character is `#' for Sun compatibility. The -line-comment character is `|'. If a `#' appears at the beginning of a -line, it is treated as a comment unless it looks like `# line file', in -which case it is treated normally. - - -File: as.info, Node: Sparc-Dependent, Next: Z8000-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies - -SPARC Dependent Features -======================== - -* Menu: - -* Sparc-Opts:: Options -* Sparc-Float:: Floating Point -* Sparc-Directives:: Sparc Machine Directives - - -File: as.info, Node: Sparc-Opts, Next: Sparc-Float, Up: Sparc-Dependent - -Options -------- - - The SPARC chip family includes several successive levels (or other -variants) of chip, using the same core instruction set, but including a -few additional instructions at each level. - - By default, `as' assumes the core instruction set (SPARC v6), but -"bumps" the architecture level as needed: it switches to successively -higher architectures as it encounters instructions that only exist in -the higher levels. - -`-Av6 | -Av7 | -Av8 | -Asparclite' - Use one of the `-A' options to select one of the SPARC - architectures explicitly. If you select an architecture - explicitly, `as' reports a fatal error if it encounters an - instruction or feature requiring a higher level. - -`-bump' - Permit the assembler to "bump" the architecture level as required, - but warn whenever it is necessary to switch to another level. - - -File: as.info, Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Opts, Up: Sparc-Dependent - -Floating Point --------------- - - The Sparc uses IEEE floating-point numbers. - - -File: as.info, Node: Sparc-Directives, Prev: Sparc-Float, Up: Sparc-Dependent - -Sparc Machine Directives ------------------------- - - The Sparc version of `as' supports the following additional machine -directives: - -`.common' - This must be followed by a symbol name, a positive number, and - `"bss"'. This behaves somewhat like `.comm', but the syntax is - different. - -`.half' - This is functionally identical to `.short'. - -`.proc' - This directive is ignored. Any text following it on the same line - is also ignored. - -`.reserve' - This must be followed by a symbol name, a positive number, and - `"bss"'. This behaves somewhat like `.lcomm', but the syntax is - different. - -`.seg' - This must be followed by `"text"', `"data"', or `"data1"'. It - behaves like `.text', `.data', or `.data 1'. - -`.skip' - This is functionally identical to the `.space' directive. - -`.word' - On the Sparc, the .word directive produces 32 bit values, instead - of the 16 bit values it produces on many other machines. - - -File: as.info, Node: i386-Dependent, Prev: Z8000-Dependent, Up: Machine Dependencies - -80386 Dependent Features -======================== - -* Menu: - -* i386-Options:: Options -* i386-Syntax:: AT&T Syntax versus Intel Syntax -* i386-Opcodes:: Opcode Naming -* i386-Regs:: Register Naming -* i386-prefixes:: Opcode Prefixes -* i386-Memory:: Memory References -* i386-jumps:: Handling of Jump Instructions -* i386-Float:: Floating Point -* i386-Notes:: Notes - - -File: as.info, Node: i386-Options, Next: i386-Syntax, Up: i386-Dependent - -Options -------- - - The 80386 has no machine dependent options. - - -File: as.info, Node: i386-Syntax, Next: i386-Opcodes, Prev: i386-Options, Up: i386-Dependent - -AT&T Syntax versus Intel Syntax -------------------------------- - - In order to maintain compatibility with the output of `gcc', `as' -supports AT&T System V/386 assembler syntax. This is quite different -from Intel syntax. We mention these differences because almost all -80386 documents used only Intel syntax. Notable differences between -the two syntaxes are: - - * AT&T immediate operands are preceded by `$'; Intel immediate - operands are undelimited (Intel `push 4' is AT&T `pushl $4'). - AT&T register operands are preceded by `%'; Intel register operands - are undelimited. AT&T absolute (as opposed to PC relative) - jump/call operands are prefixed by `*'; they are undelimited in - Intel syntax. - - * AT&T and Intel syntax use the opposite order for source and - destination operands. Intel `add eax, 4' is `addl $4, %eax'. The - `source, dest' convention is maintained for compatibility with - previous Unix assemblers. - - * In AT&T syntax the size of memory operands is determined from the - last character of the opcode name. Opcode suffixes of `b', `w', - and `l' specify byte (8-bit), word (16-bit), and long (32-bit) - memory references. Intel syntax accomplishes this by prefixes - memory operands (*not* the opcodes themselves) with `byte ptr', - `word ptr', and `dword ptr'. Thus, Intel `mov al, byte ptr FOO' - is `movb FOO, %al' in AT&T syntax. - - * Immediate form long jumps and calls are `lcall/ljmp $SECTION, - $OFFSET' in AT&T syntax; the Intel syntax is `call/jmp far - SECTION:OFFSET'. Also, the far return instruction is `lret - $STACK-ADJUST' in AT&T syntax; Intel syntax is `ret far - STACK-ADJUST'. - - * The AT&T assembler does not provide support for multiple section - programs. Unix style systems expect all programs to be single - sections. - - -File: as.info, Node: i386-Opcodes, Next: i386-Regs, Prev: i386-Syntax, Up: i386-Dependent - -Opcode Naming -------------- - - Opcode names are suffixed with one character modifiers which specify -the size of operands. The letters `b', `w', and `l' specify byte, -word, and long operands. If no suffix is specified by an instruction -and it contains no memory operands then `as' tries to fill in the -missing suffix based on the destination register operand (the last one -by convention). Thus, `mov %ax, %bx' is equivalent to `movw %ax, %bx'; -also, `mov $1, %bx' is equivalent to `movw $1, %bx'. Note that this is -incompatible with the AT&T Unix assembler which assumes that a missing -opcode suffix implies long operand size. (This incompatibility does -not affect compiler output since compilers always explicitly specify -the opcode suffix.) - - Almost all opcodes have the same names in AT&T and Intel format. -There are a few exceptions. The sign extend and zero extend -instructions need two sizes to specify them. They need a size to -sign/zero extend *from* and a size to zero extend *to*. This is -accomplished by using two opcode suffixes in AT&T syntax. Base names -for sign extend and zero extend are `movs...' and `movz...' in AT&T -syntax (`movsx' and `movzx' in Intel syntax). The opcode suffixes are -tacked on to this base name, the *from* suffix before the *to* suffix. -Thus, `movsbl %al, %edx' is AT&T syntax for "move sign extend *from* -%al *to* %edx." Possible suffixes, thus, are `bl' (from byte to long), -`bw' (from byte to word), and `wl' (from word to long). - - The Intel-syntax conversion instructions - - * `cbw' -- sign-extend byte in `%al' to word in `%ax', - - * `cwde' -- sign-extend word in `%ax' to long in `%eax', - - * `cwd' -- sign-extend word in `%ax' to long in `%dx:%ax', - - * `cdq' -- sign-extend dword in `%eax' to quad in `%edx:%eax', - -are called `cbtw', `cwtl', `cwtd', and `cltd' in AT&T naming. `as' -accepts either naming for these instructions. - - Far call/jump instructions are `lcall' and `ljmp' in AT&T syntax, -but are `call far' and `jump far' in Intel convention. - - -File: as.info, Node: i386-Regs, Next: i386-prefixes, Prev: i386-Opcodes, Up: i386-Dependent - -Register Naming ---------------- - - Register operands are always prefixes with `%'. The 80386 registers -consist of - - * the 8 32-bit registers `%eax' (the accumulator), `%ebx', `%ecx', - `%edx', `%edi', `%esi', `%ebp' (the frame pointer), and `%esp' - (the stack pointer). - - * the 8 16-bit low-ends of these: `%ax', `%bx', `%cx', `%dx', `%di', - `%si', `%bp', and `%sp'. - - * the 8 8-bit registers: `%ah', `%al', `%bh', `%bl', `%ch', `%cl', - `%dh', and `%dl' (These are the high-bytes and low-bytes of `%ax', - `%bx', `%cx', and `%dx') - - * the 6 section registers `%cs' (code section), `%ds' (data - section), `%ss' (stack section), `%es', `%fs', and `%gs'. - - * the 3 processor control registers `%cr0', `%cr2', and `%cr3'. - - * the 6 debug registers `%db0', `%db1', `%db2', `%db3', `%db6', and - `%db7'. - - * the 2 test registers `%tr6' and `%tr7'. - - * the 8 floating point register stack `%st' or equivalently - `%st(0)', `%st(1)', `%st(2)', `%st(3)', `%st(4)', `%st(5)', - `%st(6)', and `%st(7)'. - - -File: as.info, Node: i386-prefixes, Next: i386-Memory, Prev: i386-Regs, Up: i386-Dependent - -Opcode Prefixes ---------------- - - Opcode prefixes are used to modify the following opcode. They are -used to repeat string instructions, to provide section overrides, to -perform bus lock operations, and to give operand and address size -(16-bit operands are specified in an instruction by prefixing what would -normally be 32-bit operands with a "operand size" opcode prefix). -Opcode prefixes are usually given as single-line instructions with no -operands, and must directly precede the instruction they act upon. For -example, the `scas' (scan string) instruction is repeated with: - repne - scas - - Here is a list of opcode prefixes: - - * Section override prefixes `cs', `ds', `ss', `es', `fs', `gs'. - These are automatically added by specifying using the - SECTION:MEMORY-OPERAND form for memory references. - - * Operand/Address size prefixes `data16' and `addr16' change 32-bit - operands/addresses into 16-bit operands/addresses. Note that - 16-bit addressing modes (i.e. 8086 and 80286 addressing modes) are - not supported (yet). - - * The bus lock prefix `lock' inhibits interrupts during execution of - the instruction it precedes. (This is only valid with certain - instructions; see a 80386 manual for details). - - * The wait for coprocessor prefix `wait' waits for the coprocessor - to complete the current instruction. This should never be needed - for the 80386/80387 combination. - - * The `rep', `repe', and `repne' prefixes are added to string - instructions to make them repeat `%ecx' times. - - -File: as.info, Node: i386-Memory, Next: i386-jumps, Prev: i386-prefixes, Up: i386-Dependent - -Memory References ------------------ - - An Intel syntax indirect memory reference of the form - - SECTION:[BASE + INDEX*SCALE + DISP] - -is translated into the AT&T syntax - - SECTION:DISP(BASE, INDEX, SCALE) - -where BASE and INDEX are the optional 32-bit base and index registers, -DISP is the optional displacement, and SCALE, taking the values 1, 2, -4, and 8, multiplies INDEX to calculate the address of the operand. If -no SCALE is specified, SCALE is taken to be 1. SECTION specifies the -optional section register for the memory operand, and may override the -default section register (see a 80386 manual for section register -defaults). Note that section overrides in AT&T syntax *must* have be -preceded by a `%'. If you specify a section override which coincides -with the default section register, `as' will *not* output any section -register override prefixes to assemble the given instruction. Thus, -section overrides can be specified to emphasize which section register -is used for a given memory operand. - - Here are some examples of Intel and AT&T style memory references: - -AT&T: `-4(%ebp)', Intel: `[ebp - 4]' - BASE is `%ebp'; DISP is `-4'. SECTION is missing, and the default - section is used (`%ss' for addressing with `%ebp' as the base - register). INDEX, SCALE are both missing. - -AT&T: `foo(,%eax,4)', Intel: `[foo + eax*4]' - INDEX is `%eax' (scaled by a SCALE 4); DISP is `foo'. All other - fields are missing. The section register here defaults to `%ds'. - -AT&T: `foo(,1)'; Intel `[foo]' - This uses the value pointed to by `foo' as a memory operand. Note - that BASE and INDEX are both missing, but there is only *one* `,'. - This is a syntactic exception. - -AT&T: `%gs:foo'; Intel `gs:foo' - This selects the contents of the variable `foo' with section - register SECTION being `%gs'. - - Absolute (as opposed to PC relative) call and jump operands must be -prefixed with `*'. If no `*' is specified, `as' will always choose PC -relative addressing for jump/call labels. - - Any instruction that has a memory operand *must* specify its size -(byte, word, or long) with an opcode suffix (`b', `w', or `l', -respectively). - - -File: as.info, Node: i386-jumps, Next: i386-Float, Prev: i386-Memory, Up: i386-Dependent - -Handling of Jump Instructions ------------------------------ - - Jump instructions are always optimized to use the smallest possible -displacements. This is accomplished by using byte (8-bit) displacement -jumps whenever the target is sufficiently close. If a byte displacement -is insufficient a long (32-bit) displacement is used. We do not support -word (16-bit) displacement jumps (i.e. prefixing the jump instruction -with the `addr16' opcode prefix), since the 80386 insists upon masking -`%eip' to 16 bits after the word displacement is added. - - Note that the `jcxz', `jecxz', `loop', `loopz', `loope', `loopnz' -and `loopne' instructions only come in byte displacements, so that it -is possible that use of these instructions (`gcc' does not use them) -will cause the assembler to print an error message (and generate -incorrect code). The AT&T 80386 assembler tries to get around this -problem by expanding `jcxz foo' to - jcxz cx_zero - jmp cx_nonzero - cx_zero: jmp foo - cx_nonzero: - - -File: as.info, Node: i386-Float, Next: i386-Notes, Prev: i386-jumps, Up: i386-Dependent - -Floating Point --------------- - - All 80387 floating point types except packed BCD are supported. -(BCD support may be added without much difficulty). These data types -are 16-, 32-, and 64- bit integers, and single (32-bit), double -(64-bit), and extended (80-bit) precision floating point. Each -supported type has an opcode suffix and a constructor associated with -it. Opcode suffixes specify operand's data types. Constructors build -these data types into memory. - - * Floating point constructors are `.float' or `.single', `.double', - and `.tfloat' for 32-, 64-, and 80-bit formats. These correspond - to opcode suffixes `s', `l', and `t'. `t' stands for temporary - real, and that the 80387 only supports this format via the `fldt' - (load temporary real to stack top) and `fstpt' (store temporary - real and pop stack) instructions. - - * Integer constructors are `.word', `.long' or `.int', and `.quad' - for the 16-, 32-, and 64-bit integer formats. The corresponding - opcode suffixes are `s' (single), `l' (long), and `q' (quad). As - with the temporary real format the 64-bit `q' format is only - present in the `fildq' (load quad integer to stack top) and - `fistpq' (store quad integer and pop stack) instructions. - - Register to register operations do not require opcode suffixes, so -that `fst %st, %st(1)' is equivalent to `fstl %st, %st(1)'. - - Since the 80387 automatically synchronizes with the 80386 `fwait' -instructions are almost never needed (this is not the case for the -80286/80287 and 8086/8087 combinations). Therefore, `as' suppresses -the `fwait' instruction whenever it is implicitly selected by one of -the `fn...' instructions. For example, `fsave' and `fnsave' are -treated identically. In general, all the `fn...' instructions are made -equivalent to `f...' instructions. If `fwait' is desired it must be -explicitly coded. - - -File: as.info, Node: i386-Notes, Prev: i386-Float, Up: i386-Dependent - -Notes ------ - - There is some trickery concerning the `mul' and `imul' instructions -that deserves mention. The 16-, 32-, and 64-bit expanding multiplies -(base opcode `0xf6'; extension 4 for `mul' and 5 for `imul') can be -output only in the one operand form. Thus, `imul %ebx, %eax' does -*not* select the expanding multiply; the expanding multiply would -clobber the `%edx' register, and this would confuse `gcc' output. Use -`imul %ebx' to get the 64-bit product in `%edx:%eax'. - - We have added a two operand form of `imul' when the first operand is -an immediate mode expression and the second operand is a register. -This is just a shorthand, so that, multiplying `%eax' by 69, for -example, can be done with `imul $69, %eax' rather than `imul $69, %eax, -%eax'. - - -File: as.info, Node: Z8000-Dependent, Next: i386-Dependent, Prev: Sparc-Dependent, Up: Machine Dependencies - -Z8000 Dependent Features -======================== - - The Z8000 as supports both members of the Z8000 family: the -unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with -24 bit addresses. - - When the assembler is in unsegmented mode (specified with the -`unsegm' directive), an address will take up one word (16 bit) sized -register. When the assembler is in segmented mode (specified with the -`segm' directive), a 24-bit address takes up a long (32 bit) register. -*Note Assembler Directives for the Z8000: Z8000 Directives, for a list -of other Z8000 specific assembler directives. - -* Menu: - -* Z8000 Options:: No special command-line options for Z8000 -* Z8000 Syntax:: Assembler syntax for the Z8000 -* Z8000 Directives:: Special directives for the Z8000 -* Z8000 Opcodes:: Opcodes - - -File: as.info, Node: Z8000 Options, Next: Z8000 Syntax, Up: Z8000-Dependent - -Options -------- - - `as' has no additional command-line options for the Zilog Z8000 -family. - - -File: as.info, Node: Z8000 Syntax, Next: Z8000 Directives, Prev: Z8000 Options, Up: Z8000-Dependent - -Syntax ------- - -* Menu: - -* Z8000-Chars:: Special Characters -* Z8000-Regs:: Register Names -* Z8000-Addressing:: Addressing Modes - - -File: as.info, Node: Z8000-Chars, Next: Z8000-Regs, Up: Z8000 Syntax - -Special Characters -.................. - - `!' is the line comment character. - - You can use `;' instead of a newline to separate statements. - - -File: as.info, Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, Up: Z8000 Syntax - -Register Names -.............. - - The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can -refer to different sized groups of registers by register number, with -the prefix `r' for 16 bit registers, `rr' for 32 bit registers and `rq' -for 64 bit registers. You can also refer to the contents of the first -eight (of the sixteen 16 bit registers) by bytes. They are named `rNh' -and `rNl'. - -*byte registers* - r0l r0h r1h r1l r2h r2l r3h r3l - r4h r4l r5h r5l r6h r6l r7h r7l -*word registers* - r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 -*long word registers* - rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14 -*quad word registers* - rq0 rq4 rq8 rq12 - - -File: as.info, Node: Z8000-Addressing, Prev: Z8000-Regs, Up: Z8000 Syntax - -Addressing Modes -................ - - as understands the following addressing modes for the Z8000: - -`rN' - Register direct - -`@rN' - Indirect register - -`ADDR' - Direct: the 16 bit or 24 bit address (depending on whether the - assembler is in segmented or unsegmented mode) of the operand is - in the instruction. - -`address(rN)' - Indexed: the 16 or 24 bit address is added to the 16 bit register - to produce the final address in memory of the operand. - -`rN(#IMM)' - Base Address: the 16 or 24 bit register is added to the 16 bit sign - extended immediate displacement to produce the final address in - memory of the operand. - -`rN(rM)' - Base Index: the 16 or 24 bit register rN is added to the sign - extended 16 bit index register rM to produce the final address in - memory of the operand. - -`#XX' - Immediate data XX. - - -File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent - -Assembler Directives for the Z8000 ----------------------------------- - - The Z8000 port of as includes these additional assembler directives, -for compatibility with other Z8000 assemblers. As shown, these do not -begin with `.' (unlike the ordinary as directives). - -`segm' - Generates code for the segmented Z8001. - -`unsegm' - Generates code for the unsegmented Z8002. - -`name' - Synonym for `.file' - -`global' - Synonum for `.global' - -`wval' - Synonym for `.word' - -`lval' - Synonym for `.long' - -`bval' - Synonym for `.byte' - -`sval' - Assemble a string. `sval' expects one string literal, delimited by - single quotes. It assembles each byte of the string into - consecutive addresses. You can use the escape sequence `%XX' - (where XX represents a two-digit hexadecimal number) to represent - the character whose ASCII value is XX. Use this feature to - describe single quote and other characters that may not appear in - string literals as themselves. For example, the C statement - `char *a = "he said \"it's 50% off\"";' is represented in Z8000 - assembly language (shown with the assembler output in hex at the - left) as - - 68652073 sval 'he said %22it%27s 50%25 off%22%00' - 61696420 - 22697427 - 73203530 - 25206F66 - 662200 - -`rsect' - synonym for `.section' - -`block' - synonym for `.space' - -`even' - synonym for `.align 1' - - -File: as.info, Node: Z8000 Opcodes, Prev: Z8000 Directives, Up: Z8000-Dependent - -Opcodes -------- - - For detailed information on the Z8000 machine instruction set, see -`Z8000 Technical Manual'. - - The following table summarizes the opcodes and their arguments: - - rs 16 bit source register - rd 16 bit destination register - rbs 8 bit source register - rbd 8 bit destination register - rrs 32 bit source register - rrd 32 bit destination register - rqs 64 bit source register - rqd 64 bit destination register - addr 16/24 bit address - imm immediate data - - adc rd,rs clrb addr cpsir @rd,@rs,rr,cc - adcb rbd,rbs clrb addr(rd) cpsirb @rd,@rs,rr,cc - add rd,@rs clrb rbd dab rbd - add rd,addr com @rd dbjnz rbd,disp7 - add rd,addr(rs) com addr dec @rd,imm4m1 - add rd,imm16 com addr(rd) dec addr(rd),imm4m1 - add rd,rs com rd dec addr,imm4m1 - addb rbd,@rs comb @rd dec rd,imm4m1 - addb rbd,addr comb addr decb @rd,imm4m1 - addb rbd,addr(rs) comb addr(rd) decb addr(rd),imm4m1 - addb rbd,imm8 comb rbd decb addr,imm4m1 - addb rbd,rbs comflg flags decb rbd,imm4m1 - addl rrd,@rs cp @rd,imm16 di i2 - addl rrd,addr cp addr(rd),imm16 div rrd,@rs - addl rrd,addr(rs) cp addr,imm16 div rrd,addr - addl rrd,imm32 cp rd,@rs div rrd,addr(rs) - addl rrd,rrs cp rd,addr div rrd,imm16 - and rd,@rs cp rd,addr(rs) div rrd,rs - and rd,addr cp rd,imm16 divl rqd,@rs - and rd,addr(rs) cp rd,rs divl rqd,addr - and rd,imm16 cpb @rd,imm8 divl rqd,addr(rs) - and rd,rs cpb addr(rd),imm8 divl rqd,imm32 - andb rbd,@rs cpb addr,imm8 divl rqd,rrs - andb rbd,addr cpb rbd,@rs djnz rd,disp7 - andb rbd,addr(rs) cpb rbd,addr ei i2 - andb rbd,imm8 cpb rbd,addr(rs) ex rd,@rs - andb rbd,rbs cpb rbd,imm8 ex rd,addr - bit @rd,imm4 cpb rbd,rbs ex rd,addr(rs) - bit addr(rd),imm4 cpd rd,@rs,rr,cc ex rd,rs - bit addr,imm4 cpdb rbd,@rs,rr,cc exb rbd,@rs - bit rd,imm4 cpdr rd,@rs,rr,cc exb rbd,addr - bit rd,rs cpdrb rbd,@rs,rr,cc exb rbd,addr(rs) - bitb @rd,imm4 cpi rd,@rs,rr,cc exb rbd,rbs - bitb addr(rd),imm4 cpib rbd,@rs,rr,cc ext0e imm8 - bitb addr,imm4 cpir rd,@rs,rr,cc ext0f imm8 - bitb rbd,imm4 cpirb rbd,@rs,rr,cc ext8e imm8 - bitb rbd,rs cpl rrd,@rs ext8f imm8 - bpt cpl rrd,addr exts rrd - call @rd cpl rrd,addr(rs) extsb rd - call addr cpl rrd,imm32 extsl rqd - call addr(rd) cpl rrd,rrs halt - calr disp12 cpsd @rd,@rs,rr,cc in rd,@rs - clr @rd cpsdb @rd,@rs,rr,cc in rd,imm16 - clr addr cpsdr @rd,@rs,rr,cc inb rbd,@rs - clr addr(rd) cpsdrb @rd,@rs,rr,cc inb rbd,imm16 - clr rd cpsi @rd,@rs,rr,cc inc @rd,imm4m1 - clrb @rd cpsib @rd,@rs,rr,cc inc addr(rd),imm4m1 - inc addr,imm4m1 ldb rbd,rs(rx) mult rrd,addr(rs) - inc rd,imm4m1 ldb rd(imm16),rbs mult rrd,imm16 - incb @rd,imm4m1 ldb rd(rx),rbs mult rrd,rs - incb addr(rd),imm4m1 ldctl ctrl,rs multl rqd,@rs - incb addr,imm4m1 ldctl rd,ctrl multl rqd,addr - incb rbd,imm4m1 ldd @rs,@rd,rr multl rqd,addr(rs) - ind @rd,@rs,ra lddb @rs,@rd,rr multl rqd,imm32 - indb @rd,@rs,rba lddr @rs,@rd,rr multl rqd,rrs - inib @rd,@rs,ra lddrb @rs,@rd,rr neg @rd - inibr @rd,@rs,ra ldi @rd,@rs,rr neg addr - iret ldib @rd,@rs,rr neg addr(rd) - jp cc,@rd ldir @rd,@rs,rr neg rd - jp cc,addr ldirb @rd,@rs,rr negb @rd - jp cc,addr(rd) ldk rd,imm4 negb addr - jr cc,disp8 ldl @rd,rrs negb addr(rd) - ld @rd,imm16 ldl addr(rd),rrs negb rbd - ld @rd,rs ldl addr,rrs nop - ld addr(rd),imm16 ldl rd(imm16),rrs or rd,@rs - ld addr(rd),rs ldl rd(rx),rrs or rd,addr - ld addr,imm16 ldl rrd,@rs or rd,addr(rs) - ld addr,rs ldl rrd,addr or rd,imm16 - ld rd(imm16),rs ldl rrd,addr(rs) or rd,rs - ld rd(rx),rs ldl rrd,imm32 orb rbd,@rs - ld rd,@rs ldl rrd,rrs orb rbd,addr - ld rd,addr ldl rrd,rs(imm16) orb rbd,addr(rs) - ld rd,addr(rs) ldl rrd,rs(rx) orb rbd,imm8 - ld rd,imm16 ldm @rd,rs,n orb rbd,rbs - ld rd,rs ldm addr(rd),rs,n out @rd,rs - ld rd,rs(imm16) ldm addr,rs,n out imm16,rs - ld rd,rs(rx) ldm rd,@rs,n outb @rd,rbs - lda rd,addr ldm rd,addr(rs),n outb imm16,rbs - lda rd,addr(rs) ldm rd,addr,n outd @rd,@rs,ra - lda rd,rs(imm16) ldps @rs outdb @rd,@rs,rba - lda rd,rs(rx) ldps addr outib @rd,@rs,ra - ldar rd,disp16 ldps addr(rs) outibr @rd,@rs,ra - ldb @rd,imm8 ldr disp16,rs pop @rd,@rs - ldb @rd,rbs ldr rd,disp16 pop addr(rd),@rs - ldb addr(rd),imm8 ldrb disp16,rbs pop addr,@rs - ldb addr(rd),rbs ldrb rbd,disp16 pop rd,@rs - ldb addr,imm8 ldrl disp16,rrs popl @rd,@rs - ldb addr,rbs ldrl rrd,disp16 popl addr(rd),@rs - ldb rbd,@rs mbit popl addr,@rs - ldb rbd,addr mreq rd popl rrd,@rs - ldb rbd,addr(rs) mres push @rd,@rs - ldb rbd,imm8 mset push @rd,addr - ldb rbd,rbs mult rrd,@rs push @rd,addr(rs) - ldb rbd,rs(imm16) mult rrd,addr push @rd,imm16 - push @rd,rs set addr,imm4 subl rrd,imm32 - pushl @rd,@rs set rd,imm4 subl rrd,rrs - pushl @rd,addr set rd,rs tcc cc,rd - pushl @rd,addr(rs) setb @rd,imm4 tccb cc,rbd - pushl @rd,rrs setb addr(rd),imm4 test @rd - res @rd,imm4 setb addr,imm4 test addr - res addr(rd),imm4 setb rbd,imm4 test addr(rd) - res addr,imm4 setb rbd,rs test rd - res rd,imm4 setflg imm4 testb @rd - res rd,rs sinb rbd,imm16 testb addr - resb @rd,imm4 sinb rd,imm16 testb addr(rd) - resb addr(rd),imm4 sind @rd,@rs,ra testb rbd - resb addr,imm4 sindb @rd,@rs,rba testl @rd - resb rbd,imm4 sinib @rd,@rs,ra testl addr - resb rbd,rs sinibr @rd,@rs,ra testl addr(rd) - resflg imm4 sla rd,imm8 testl rrd - ret cc slab rbd,imm8 trdb @rd,@rs,rba - rl rd,imm1or2 slal rrd,imm8 trdrb @rd,@rs,rba - rlb rbd,imm1or2 sll rd,imm8 trib @rd,@rs,rbr - rlc rd,imm1or2 sllb rbd,imm8 trirb @rd,@rs,rbr - rlcb rbd,imm1or2 slll rrd,imm8 trtdrb @ra,@rb,rbr - rldb rbb,rba sout imm16,rs trtib @ra,@rb,rr - rr rd,imm1or2 soutb imm16,rbs trtirb @ra,@rb,rbr - rrb rbd,imm1or2 soutd @rd,@rs,ra trtrb @ra,@rb,rbr - rrc rd,imm1or2 soutdb @rd,@rs,rba tset @rd - rrcb rbd,imm1or2 soutib @rd,@rs,ra tset addr - rrdb rbb,rba soutibr @rd,@rs,ra tset addr(rd) - rsvd36 sra rd,imm8 tset rd - rsvd38 srab rbd,imm8 tsetb @rd - rsvd78 sral rrd,imm8 tsetb addr - rsvd7e srl rd,imm8 tsetb addr(rd) - rsvd9d srlb rbd,imm8 tsetb rbd - rsvd9f srll rrd,imm8 xor rd,@rs - rsvdb9 sub rd,@rs xor rd,addr - rsvdbf sub rd,addr xor rd,addr(rs) - sbc rd,rs sub rd,addr(rs) xor rd,imm16 - sbcb rbd,rbs sub rd,imm16 xor rd,rs - sc imm8 sub rd,rs xorb rbd,@rs - sda rd,rs subb rbd,@rs xorb rbd,addr - sdab rbd,rs subb rbd,addr xorb rbd,addr(rs) - sdal rrd,rs subb rbd,addr(rs) xorb rbd,imm8 - sdl rd,rs subb rbd,imm8 xorb rbd,rbs - sdlb rbd,rs subb rbd,rbs xorb rbd,rbs - sdll rrd,rs subl rrd,@rs - set @rd,imm4 subl rrd,addr - set addr(rd),imm4 subl rrd,addr(rs) - - -File: as.info, Node: Acknowledgements, Next: Index, Prev: Copying, Up: Top - -Acknowledgements -**************** - - If you've contributed to `as' and your name isn't listed here, it is -not meant as a slight. We just don't know about it. Send mail to the -maintainer, and we'll correct the situation. Currently (June 1993), the -maintainer is Ken Raeburn (email address `raeburn@cygnus.com'). - - Dean Elsner wrote the original GNU assembler for the VAX.(1) - - Jay Fenlason maintained GAS for a while, adding support for -gdb-specific debug information and the 68k series machines, most of the -preprocessing pass, and extensive changes in messages.c, input-file.c, -write.c. - - K. Richard Pixley maintained GAS for a while, adding various -enhancements and many bug fixes, including merging support for several -processors, breaking GAS up to handle multiple object file format -backends (including heavy rewrite, testing, an integration of the coff -and b.out backends), adding configuration including heavy testing and -verification of cross assemblers and file splits and renaming, -converted GAS to strictly ansi C including full prototypes, added -support for m680[34]0 & cpu32, considerable work on i960 including a -COFF port (including considerable amounts of reverse engineering), a -SPARC opcode file rewrite, DECstation, rs6000, and hp300hpux host -ports, updated "know" assertions and made them work, much other -reorganization, cleanup, and lint. - - Ken Raeburn wrote the high-level BFD interface code to replace most -of the code in format-specific I/O modules. - - The original VMS support was contributed by David L. Kashtan. Eric -Youngdale has done much work with it since. - - The Intel 80386 machine description was written by Eliot Dresselhaus. - - Minh Tran-Le at IntelliCorp contributed some AIX 386 support. - - The Motorola 88k machine description was contributed by Devon Bowen -of Buffalo University and Torbjorn Granlund of the Swedish Institute of -Computer Science. - - Keith Knowles at the Open Software Foundation wrote the original -MIPS back end (tc-mips.c, tc-mips.h), and contributed Rose format -support (which hasn't been merged in yet). Ralph Campbell worked with -the MIPS code to support a.out format. - - Support for the Zilog Z8k and Hitachi H8/300 and H8/500 processors -(tc-z8k, tc-h8300, tc-h8500), and IEEE 695 object file format -(obj-ieee), was written by Steve Chamberlain of Cygnus Support. Steve -also modified the COFF back end to use BFD for some low-level -operations, for use with the H8/300 and AMD 29k targets. - - John Gilmore built the AMD 29000 support, added .include support, and -simplified the configuration of which versions accept which pseudo-ops. -He updated the 68k machine description so that Motorola's opcodes -always produced fixed-size instructions (e.g. jsr), while synthetic -instructions remained shrinkable (jbsr). John fixed many bugs, -including true tested cross-compilation support, and one bug in -relaxation that took a week and required the apocryphal one-bit fix. - - Ian Lance Taylor of Cygnus Support merged the Motorola and MIT -syntaxes for the 68k, completed support for some COFF targets (68k, -i386 SVR3, and SCO Unix), and made a few other minor patches. - - Steve Chamberlain made `as' able to generate listings. - - Support for the HP9000/300 was contributed by Hewlett-Packard. - - Support for ELF format files has been worked on by Mark Eichin of -Cygnus Support (original, incomplete implementation for SPARC), Pete -Hoogenboom and Jeff Law at the University of Utah (HPPA mainly), -Michael Meissner of the Open Software Foundation (i386 mainly), and Ken -Raeburn of Cygnus Support (sparc, and some initial 64-bit support). - - Several engineers at Cygnus Support have also provided many small -bug fixes and configuration enhancements. - - Many others have contributed large or small bugfixes and -enhancements. If you've contributed significant work and are not -mentioned on this list, and want to be, let us know. Some of the -history has been lost; we aren't intentionally leaving anyone out. - - ---------- Footnotes ---------- - - (1) Any more details? - |